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Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2023-01-09 11:30:08 -05:00
parent 62e2ad1cea fe33066d24
commit cebdfc22da
2483 changed files with 62769 additions and 32768 deletions
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4
include/config_fallbacks.h
View File

@@ -17,8 +17,8 @@
#endif
#endif
#ifndef CONFIG_SYS_BAUDRATE_TABLE
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#ifndef CFG_SYS_BAUDRATE_TABLE
#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
#endif /* __CONFIG_FALLBACKS_H */

21
include/config_uncmd_spl.h
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@@ -1,21 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012
* Ilya Yanok, ilya.yanok@gmail.com
*/
#ifndef __CONFIG_UNCMD_SPL_H__
#define __CONFIG_UNCMD_SPL_H__
#ifdef CONFIG_SPL_BUILD
/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
#ifndef CONFIG_SPL_DM
#undef CONFIG_DM_SERIAL
#undef CONFIG_DM_I2C
#endif
#undef CONFIG_DM_STDIO
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_UNCMD_SPL_H__ */

6
include/configs/10m50_devboard.h
View File

@@ -15,7 +15,6 @@
/*
* SERIAL
*/
#define CONFIG_SYS_NS16550_MEM32
/*
* Flash
@@ -31,8 +30,7 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
#define CONFIG_SYS_SDRAM_BASE 0xc8000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#define CFG_SYS_SDRAM_BASE 0xc8000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
#endif /* __CONFIG_H */

5
include/configs/3c120_devboard.h
View File

@@ -26,8 +26,7 @@
* -The heap is placed below the monitor
* -The stack is placed below the heap (&grows down).
*/
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_MONITOR_IS_IN_RAM
#define CFG_SYS_SDRAM_BASE 0xD0000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
#endif /* __CONFIG_H */

74
include/configs/M5208EVBE.h
View File

@@ -13,21 +13,11 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
#define CFG_SYS_UART_PORT (0)
/* I2C */
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME "M5208EVBe"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
@@ -39,13 +29,13 @@
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR 0x36
#define CONFIG_SYS_PLL_FDR 0x7D
#define CFG_SYS_CLK 166666666 /* CPU Core Clock */
#define CFG_SYS_PLL_ODR 0x36
#define CFG_SYS_PLL_FDR 0x7D
#define CONFIG_SYS_MBAR 0xFC000000
#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
@@ -53,36 +43,36 @@
* You should know what you are doing if you make changes here.
*/
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x43711630
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1002000
#define CFG_SYS_SDRAM_EMOD 0x80010000
#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* Configuration for environment
@@ -95,15 +85,15 @@
/* Cache Configuration */
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -117,8 +107,8 @@
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x007F0001
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
#define CFG_SYS_CS0_BASE 0
#define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
#endif /* _M5208EVBE_H */

73
include/configs/M5235EVB.h
View File

@@ -18,25 +18,16 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CFG_SYS_UART_PORT (0)
/* I2C */
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
#define CFG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CFG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CFG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG COMMANDS (if any) */
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME "M5235EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
@@ -48,12 +39,12 @@
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_CLK 75000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CFG_SYS_CLK 75000000
#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 2
#define CONFIG_SYS_MBAR 0x40000000
#define CFG_SYS_MBAR 0x40000000
/*
* Low Level Configuration Settings
@@ -63,17 +54,17 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_CTRL 0x21
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
@@ -81,16 +72,16 @@
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -104,15 +95,15 @@
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINV)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -130,13 +121,13 @@
* CS7 - Available
*/
#ifdef CONFIG_NORFLASH_PS32BIT
# define CONFIG_SYS_CS0_BASE 0xFFC00000
# define CONFIG_SYS_CS0_MASK 0x003f0001
# define CONFIG_SYS_CS0_CTRL 0x00001D00
# define CFG_SYS_CS0_BASE 0xFFC00000
# define CFG_SYS_CS0_MASK 0x003f0001
# define CFG_SYS_CS0_CTRL 0x00001D00
#else
# define CONFIG_SYS_CS0_BASE 0xFFE00000
# define CONFIG_SYS_CS0_MASK 0x001f0001
# define CONFIG_SYS_CS0_CTRL 0x00001D80
# define CFG_SYS_CS0_BASE 0xFFE00000
# define CFG_SYS_CS0_MASK 0x001f0001
# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
#endif /* _M5329EVB_H */

78
include/configs/M5249EVB.h
View File

@@ -18,17 +18,15 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
#define CFG_SYS_UART_PORT (0)
/*
* Clock configuration: enable only one of the following options
*/
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CFG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
#define CFG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
/*
* Low Level Configuration Settings
@@ -36,14 +34,14 @@
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_MBAR2 0x80000000
#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_SYS_MBAR2 0x80000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
@@ -52,14 +50,14 @@
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#define CFG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif
/*
@@ -67,33 +65,33 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*-----------------------------------------------------------------------
@@ -101,25 +99,25 @@
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
#define CFG_SYS_CS0_BASE 0xffe00000
#define CFG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
#define CFG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CONFIG_SYS_CS1_BASE 0xe0000000
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
#define CFG_SYS_CS1_BASE 0xe0000000
#define CFG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CFG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* M5249 */

102
include/configs/M5253DEMO.h
View File

@@ -8,7 +8,7 @@
#include <linux/stringify.h>
#define CONFIG_SYS_UART_PORT (0)
#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
@@ -20,15 +20,7 @@
env/embedded.o(.text*);
#ifdef CONFIG_DRIVER_DM9000
# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
# define CONFIG_DM9000_BYTE_SWAPPED
# define CONFIG_OVERWRITE_ETHADDR_ONCE
# define CONFIG_EXTRA_ENV_SETTINGS \
# define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=10000\0" \
@@ -42,21 +34,19 @@
""
#endif
#define CONFIG_HOSTNAME "M5253DEMO"
/* I2C */
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET (0)
#define CFG_SYS_I2C_PINMUX_REG (*(u32 *) (CFG_SYS_MBAR+0x19C))
#define CFG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CFG_SYS_I2C_PINMUX_SET (0)
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
# define CONFIG_SYS_PLLCR 0x1243E054
# define CONFIG_SYS_CLK 140000000
#undef CFG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CFG_SYS_FAST_CLK
#ifdef CFG_SYS_FAST_CLK
# define CFG_SYS_PLLCR 0x1243E054
# define CFG_SYS_CLK 140000000
#else
# define CONFIG_SYS_PLLCR 0x135a4140
# define CONFIG_SYS_CLK 70000000
# define CFG_SYS_PLLCR 0x135a4140
# define CFG_SYS_CLK 70000000
#endif
/*
@@ -65,32 +55,32 @@
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CFG_SYS_FLASH_BASE (CFG_SYS_CS0_BASE)
#define FLASH_SST6401B 0x200
#define SST_ID_xF6401B 0x236D236D
@@ -101,45 +91,45 @@
* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
* 0x30 is block erase in SST
*/
# define CONFIG_SYS_FLASH_SIZE 0x800000
# define CFG_SYS_FLASH_SIZE 0x800000
#else
# define CONFIG_SYS_SST_SECT 2048
# define CONFIG_SYS_SST_SECTSZ 0x1000
# define CFG_SYS_SST_SECT 2048
# define CFG_SYS_SST_SECTSZ 0x1000
#endif
/* Cache Configuration */
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK 0x007F0021
#define CONFIG_SYS_CS0_CTRL 0x00001D80
#define CFG_SYS_CS0_BASE 0xFF800000
#define CFG_SYS_CS0_MASK 0x007F0021
#define CFG_SYS_CS0_CTRL 0x00001D80
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK 0x00000001
#define CONFIG_SYS_CS1_CTRL 0x00003DD8
#define CFG_SYS_CS1_BASE 0xE0000000
#define CFG_SYS_CS1_MASK 0x00000001
#define CFG_SYS_CS1_CTRL 0x00003DD8
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
#define CFG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CFG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
#define CFG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CFG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CFG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253DEMO_H */

70
include/configs/M5272C3.h
View File

@@ -17,11 +17,7 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -31,15 +27,7 @@
. = DEFINED(env_offset) ? env_offset : .; \
env/embedded.o(.text);
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME "M5272C3"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
@@ -51,59 +39,59 @@
"save\0" \
""
#define CONFIG_SYS_CLK 66000000
#define CFG_SYS_CLK 66000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_SCR 0x0003
#define CONFIG_SYS_SPR 0xffff
#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CFG_SYS_SCR 0x0003
#define CFG_SYS_SPR 0xffff
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CFG_SYS_FLASH_BASE 0xffe00000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -111,11 +99,11 @@
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_PACNT 0x00000000
#define CONFIG_SYS_PADDR 0x0000
#define CONFIG_SYS_PADAT 0x0000
#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CONFIG_SYS_PBDDR 0x0000
#define CONFIG_SYS_PBDAT 0x0000
#define CONFIG_SYS_PDCNT 0x00000000
#define CFG_SYS_PACNT 0x00000000
#define CFG_SYS_PADDR 0x0000
#define CFG_SYS_PADAT 0x0000
#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CFG_SYS_PBDDR 0x0000
#define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000
#endif /* _M5272C3_H */

62
include/configs/M5275EVB.h
View File

@@ -21,7 +21,7 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -34,15 +34,11 @@
/* Available command configuration */
/* I2C */
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CFG_SYS_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"uboot=u-boot.bin\0" \
@@ -54,7 +50,7 @@
"save\0" \
""
#define CONFIG_SYS_CLK 150000000
#define CFG_SYS_CLK 150000000
/*
* Low Level Configuration Settings
@@ -62,49 +58,49 @@
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x40000000
#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_SIZE 0x200000
#define CFG_SYS_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
@@ -112,12 +108,12 @@
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CFG_SYS_CS0_BASE 0xffe00000
#define CFG_SYS_CS0_CTRL 0x00001980
#define CFG_SYS_CS0_MASK 0x001F0001
#define CONFIG_SYS_CS1_BASE 0x30000000
#define CONFIG_SYS_CS1_CTRL 0x00001900
#define CONFIG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_BASE 0x30000000
#define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001
#endif /* _M5275EVB_H */

94
include/configs/M5282EVB.h
View File

@@ -17,9 +17,7 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#define CFG_SYS_UART_PORT (0)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -29,15 +27,7 @@
. = DEFINED(env_offset) ? env_offset : .; \
env/embedded.o(.text*);
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME "M5282EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
@@ -49,98 +39,92 @@
"save\0" \
""
#define CONFIG_SYS_CLK 64000000
#define CFG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
#define CFG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
#define CFG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x40000000
#define CFG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
#define CFG_SYS_INT_FLASH_BASE 0xf0000000
#define CFG_SYS_INT_FLASH_ENABLE 0x21
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DBWE | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CFG_SYS_CS0_BASE 0xFFE00000
#define CFG_SYS_CS0_CTRL 0x00001980
#define CFG_SYS_CS0_MASK 0x001F0001
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
#define CONFIG_SYS_PADDR 0x0000000
#define CONFIG_SYS_PADAT 0x0000000
#define CFG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
#define CFG_SYS_PADDR 0x0000000
#define CFG_SYS_PADAT 0x0000000
#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
#define CONFIG_SYS_PBDDR 0x0000000
#define CONFIG_SYS_PBDAT 0x0000000
#define CFG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
#define CFG_SYS_PBDDR 0x0000000
#define CFG_SYS_PBDAT 0x0000000
#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
#define CONFIG_SYS_PCDDR 0x0000000
#define CONFIG_SYS_PCDAT 0x0000000
#define CFG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
#define CONFIG_SYS_PCDDR 0x0000000
#define CONFIG_SYS_PCDAT 0x0000000
#define CONFIG_SYS_PEHLPAR 0xC0
#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CONFIG_SYS_DDRUA 0x05
#define CONFIG_SYS_PJPAR 0xFF
#define CFG_SYS_PEHLPAR 0xC0
#define CFG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
#endif /* _CONFIG_M5282EVB_H */

87
include/configs/M53017EVB.h
View File

@@ -18,29 +18,19 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000
#define CFG_SYS_UART_PORT (0)
#ifdef CONFIG_MCFFEC
# define CONFIG_SYS_TX_ETH_BUFFER 8
# define CONFIG_SYS_FEC_BUF_USE_SRAM
# define CFG_SYS_TX_ETH_BUFFER 8
# define CFG_SYS_FEC_BUF_USE_SRAM
#endif
#define CONFIG_SYS_RTC_CNT (0x8000)
#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
#define CFG_SYS_RTC_CNT (0x8000)
#define CFG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
/* I2C */
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME "M53017"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
@@ -52,12 +42,12 @@
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CFG_SYS_CLK 80000000
#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
#define CONFIG_SYS_MBAR 0xFC000000
#define CFG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
@@ -67,39 +57,38 @@
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x43711630
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1092000
#define CFG_SYS_SDRAM_EMOD 0x80010000
#define CFG_SYS_SDRAM_MODE 0x00CD0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_SPANSION_S29WS_N 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +102,15 @@
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
@@ -135,12 +124,12 @@
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x00FF0001
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
#define CFG_SYS_CS0_BASE 0
#define CFG_SYS_CS0_MASK 0x00FF0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
#define CONFIG_SYS_CS1_BASE 0xC0000000
#define CONFIG_SYS_CS1_MASK 0x00070001
#define CONFIG_SYS_CS1_CTRL 0x00001FA0
#define CFG_SYS_CS1_BASE 0xC0000000
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0
#endif /* _M53017EVB_H */

91
include/configs/M5329EVB.h
View File

@@ -18,21 +18,11 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CFG_SYS_UART_PORT (0)
/* I2C */
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME "M5329EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
@@ -44,14 +34,14 @@
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CFG_SYS_CLK 80000000
#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
#define CONFIG_SYS_MBAR 0xFC000000
#define CFG_SYS_MBAR 0xFC000000
#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
@@ -61,45 +51,44 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_CTRL 0x221
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x53722730
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x53722730
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1092000
#define CFG_SYS_SDRAM_EMOD 0x40010000
#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
#ifdef CONFIG_CMD_NAND
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +102,15 @@
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
@@ -135,18 +124,18 @@
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x007f0001
#define CONFIG_SYS_CS0_CTRL 0x00001fa0
#define CFG_SYS_CS0_BASE 0
#define CFG_SYS_CS0_MASK 0x007f0001
#define CFG_SYS_CS0_CTRL 0x00001fa0
#define CONFIG_SYS_CS1_BASE 0x10000000
#define CONFIG_SYS_CS1_MASK 0x001f0001
#define CONFIG_SYS_CS1_CTRL 0x002A3780
#define CFG_SYS_CS1_BASE 0x10000000
#define CFG_SYS_CS1_MASK 0x001f0001
#define CFG_SYS_CS1_CTRL 0x002A3780
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_CS2_BASE 0x20000000
#define CONFIG_SYS_CS2_MASK (16 << 20)
#define CONFIG_SYS_CS2_CTRL 0x00001f60
#define CFG_SYS_CS2_BASE 0x20000000
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
#endif /* _M5329EVB_H */

91
include/configs/M5373EVB.h
View File

@@ -20,21 +20,11 @@
* (easy to change)
*/
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
#define CFG_SYS_UART_PORT (0)
/* I2C */
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME "M5373EVB"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
@@ -46,14 +36,14 @@
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CFG_SYS_CLK 80000000
#define CFG_SYS_CPU_CLK CFG_SYS_CLK * 3
#define CONFIG_SYS_MBAR 0xFC000000
#define CFG_SYS_MBAR 0xFC000000
#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
#define CFG_SYS_LATCH_ADDR (CFG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
@@ -63,43 +53,42 @@
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CFG_SYS_INIT_RAM_CTRL 0x221
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
* Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x53722730
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_SDRAM_CFG1 0x53722730
#define CFG_SYS_SDRAM_CFG2 0x56670000
#define CFG_SYS_SDRAM_CTRL 0xE1092000
#define CFG_SYS_SDRAM_EMOD 0x40010000
#define CFG_SYS_SDRAM_MODE 0x018D0000
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#endif
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define CFG_SYS_NAND_BASE CFG_SYS_CS2_BASE
# define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -113,15 +102,15 @@
* Cache Configuration
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
@@ -135,16 +124,16 @@
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x007f0001
#define CONFIG_SYS_CS0_CTRL 0x00001fa0
#define CFG_SYS_CS0_BASE 0
#define CFG_SYS_CS0_MASK 0x007f0001
#define CFG_SYS_CS0_CTRL 0x00001fa0
#define CONFIG_SYS_CS1_BASE 0x10000000
#define CONFIG_SYS_CS1_MASK 0x001f0001
#define CONFIG_SYS_CS1_CTRL 0x002A3780
#define CFG_SYS_CS1_BASE 0x10000000
#define CFG_SYS_CS1_MASK 0x001f0001
#define CFG_SYS_CS1_CTRL 0x002A3780
#define CONFIG_SYS_CS2_BASE 0x20000000
#define CONFIG_SYS_CS2_MASK (16 << 20)
#define CONFIG_SYS_CS2_CTRL 0x00001f60
#define CFG_SYS_CS2_BASE 0x20000000
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif /* _M5373EVB_H */

20
include/configs/MCR3000.h
View File

@@ -9,7 +9,7 @@
/* High Level Configuration Options */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"sdram_type=SDRAM\0" \
"flash_type=AM29LV160DB\0" \
"loadaddr=0x400000\0" \
@@ -52,28 +52,24 @@
"${ofl_args}; " \
"bootm ${loadaddr} - 0xf00000\0"
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_NETMASK 255.0.0.0
/* Miscellaneous configurable options */
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
#define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800)
#define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800)
/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */
#define CFG_SYS_SDRAM_BASE 0x00000000
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_TEXT_BASE
#define CFG_SYS_FLASH_BASE CONFIG_TEXT_BASE
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CFG_SYS_BOOTMAPSZ (8 << 20)
/* Environment Configuration */
@@ -82,6 +78,6 @@
/* Ethernet configuration part */
/* NAND configuration part */
#define CONFIG_SYS_NAND_BASE 0x0C000000
#define CFG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */

149
include/configs/MPC837XERDB.h
View File

@@ -14,31 +14,24 @@
* High Level Configuration Options
*/
#define CONFIG_HWCONFIG
/*
* On-board devices
*/
#define CONFIG_VSC7385_ENET
/* System performance - define the value i.e. CONFIG_SYS_XXX
*/
/* System Clock Configuration Register */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
#define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
#define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
#define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x08200000
#define CONFIG_SYS_SICRL 0x00000000
#define CFG_SYS_SICRH 0x08200000
#define CFG_SYS_SICRL 0x00000000
/*
* Output Buffer Impedance
*/
#define CONFIG_SYS_OBIR 0x30100000
#define CFG_SYS_OBIR 0x30100000
/*
* Device configurations
@@ -48,36 +41,32 @@
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#define CFG_VSC7385_IMAGE 0xFE7FE000
#define CFG_VSC7385_IMAGE_SIZE 8192
#endif
/*
* DDR Setup
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
#define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
/*
* Manually set up DDR parameters
*/
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
#define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
#define CFG_SYS_DDR_TIMING_3 0x00000000
#define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
@@ -86,7 +75,7 @@
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00260802 */ /* DDR400 */
#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
#define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
@@ -95,7 +84,7 @@
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3937d322 */
#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
#define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (5 << TIMING_CFG2_CPO_SHIFT) \
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
@@ -104,23 +93,23 @@
| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x02984cc8 */
#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
#define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x06090100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
#define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2)
/* 0x43000000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
#define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
| (0x0442 << SDRAM_MODE_SD_SHIFT))
/* 0x04400442 */ /* DDR400 */
#define CONFIG_SYS_DDR_MODE2 0x00000000
#define CFG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
*/
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#undef CFG_SYS_DRAM_TEST /* memory test, takes time */
/*
* The reserved memory
@@ -129,93 +118,63 @@
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
#define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
/*
* NAND Flash on the Local Bus
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000
#define CFG_SYS_NAND_BASE 0xE0600000
/* Vitesse 7385 */
#define CONFIG_SYS_VSC7385_BASE 0xF0000000
#define CFG_SYS_VSC7385_BASE 0xF0000000
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* SERDES */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
#define CONFIG_FSL_SERDES2 0xe3100
#define CFG_FSL_SERDES1 0xe3000
#define CFG_FSL_SERDES2 0xe3100
/* I2C */
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
#define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
#define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000
#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xB8000000
#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
/*
* TSEC
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_GMII /* MII PHY management */
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC2_PHY_ADDR 0x1c
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHYIDX 0
#endif
#endif
#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000
#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
#endif
@@ -228,22 +187,16 @@
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
#define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
*/
#define CONFIG_NETDEV "eth1"
#define FDTFILE "mpc8379_rdb.dtb"
#define CONFIG_HOSTNAME "mpc837x_rdb"
#define CONFIG_ROOTPATH "/nfsroot"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
#define CFG_EXTRA_ENV_SETTINGS \
"netdev=eth1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
"protect off " __stringify(CONFIG_TEXT_BASE) \
@@ -257,7 +210,7 @@
"cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
" $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"fdtfile=" FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"console=ttyS0\0" \

157
include/configs/MPC8548CDS.h
View File

@@ -13,34 +13,21 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_SYS_CCSRBAR 0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#define CFG_SYS_CCSRBAR 0xe0000000
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
@@ -115,32 +102,30 @@
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CFG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
#define CFG_SYS_FLASH_BASE_PHYS 0xfff000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CFG_SYS_FLASH_BANKS_LIST \
{CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
/*
* SDRAM on the Local Bus
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CFG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
#define CFG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
#else
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
#define CFG_SYS_LBC_SDRAM_BASE_PHYS CFG_SYS_LBC_SDRAM_BASE
#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CFG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
* The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -152,12 +137,12 @@
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
* The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
@@ -170,10 +155,10 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
#define CFG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CFG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* Common settings for all Local Bus SDRAM commands.
@@ -181,7 +166,7 @@
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
#define CFG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| LSDMR_PRETOACT7 \
| LSDMR_ACTTORW7 \
| LSDMR_BL8 \
@@ -220,8 +205,6 @@
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CONFIG_FSL_CADMUS
#define CADMUS_BASE_ADDR 0xf8000000
#ifdef CONFIG_PHYS_64BIT
#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
@@ -229,103 +212,69 @@
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CFG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/*
* I2C
*/
#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#define CFG_SYS_I2C_NOPROBES { {0, 0x69} }
#endif
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
#define CFG_SYS_PCI1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCI1_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
#define CFG_SYS_PCI1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CFG_SYS_PCI1_IO_VIRT 0xe2000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
#else
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CFG_SYS_PCI1_IO_PHYS 0xe2000000
#endif
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
#define CFG_SYS_PCIE1_IO_VIRT 0xe3000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
#define CFG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CFG_SYS_PCIE1_IO_PHYS 0xe3000000
#endif
#endif
/*
* RapidIO MMU
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC4_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#endif /* CONFIG_TSEC_ENET */
#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
/*
* Miscellaneous configurable options
@@ -336,26 +285,16 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
/*
* Environment Configuration
*/
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=off\0" \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " __stringify(CONFIG_TEXT_BASE) \
" +$filesize; " \

303
include/configs/P1010RDB.h
View File

@@ -16,48 +16,47 @@
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_SDCARD
#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CFG_SYS_MMC_U_BOOT_SIZE (512 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CFG_SYS_MMC_U_BOOT_START (0x11000000)
#define CFG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#endif
#ifdef CONFIG_SPIFLASH
#ifdef CONFIG_NXP_ESBC
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
#else
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#endif
#endif
#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#else
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CFG_SYS_NAND_U_BOOT_START 0xD0000000
#endif
#endif
#endif
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#define CFG_RESET_VECTOR_ADDRESS 0x110bfffc
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */
@@ -68,54 +67,46 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, Slot 1, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
#define CFG_SYS_PCIE1_IO_VIRT 0xffc00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#define CFG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#define CFG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
#define CFG_SYS_PCIE2_IO_VIRT 0xffc10000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#define CFG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#define CFG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
#endif
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
/* DDR Setup */
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_CCSRBAR 0xffe00000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
#define CFG_SYS_CCSRBAR 0xffe00000
#define CFG_SYS_CCSRBAR_PHYS_LOW CFG_SYS_CCSRBAR
/*
* Memory map
@@ -136,54 +127,51 @@ extern unsigned long get_sdram_size(void);
*/
/* NOR Flash on IFC */
#define CONFIG_SYS_FLASH_BASE 0xee000000
#define CFG_SYS_FLASH_BASE 0xee000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
#define CFG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
#define CFG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5)
#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
#define CFG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
FTIM1_NOR_TRAD_NOR(0x0f)
#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
#define CFG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWP(0x1c)
#define CONFIG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* CFI for NOR Flash */
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_MTD_PARTITION
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_NAND \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_P1010RDB_PA)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
@@ -192,7 +180,7 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
#elif defined(CONFIG_TARGET_P1010RDB_PB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -201,141 +189,133 @@ extern unsigned long get_sdram_size(void);
| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_TARGET_P1010RDB_PA)
/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
FTIM0_NAND_TWP(0x0C) | \
FTIM0_NAND_TWCHT(0x04) | \
FTIM0_NAND_TWH(0x05)
#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
FTIM1_NAND_TWBE(0x1d) | \
FTIM1_NAND_TRR(0x07) | \
FTIM1_NAND_TRP(0x0c)
#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
FTIM2_NAND_TREH(0x05) | \
FTIM2_NAND_TWHRE(0x0f)
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
#elif defined(CONFIG_TARGET_P1010RDB_PB)
/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#endif
#define CONFIG_SYS_NAND_DDR_LAW 11
/* Set up IFC registers for boot location NOR/NAND */
#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffb00000
#define CFG_SYS_CPLD_BASE 0xffb00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
#define CFG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
#else
#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
#define CFG_SYS_CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
#endif
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3 0x0
#define CFG_SYS_AMASK3 IFC_AMASK(64*1024)
#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
#define CFG_SYS_CS3_FTIM3 0x0
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CFG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Config the L2 Cache as L2 SRAM
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CFG_SYS_INIT_L2_ADDR 0xD0000000
#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CFG_SYS_INIT_L2_ADDR 0xD0000000
#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#else
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CFG_SYS_INIT_L2_ADDR 0xD0000000
#define CFG_SYS_INIT_L2_ADDR_PHYS CFG_SYS_INIT_L2_ADDR
#define CFG_SYS_INIT_L2_END (CFG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#endif
#endif
/* Serial Port */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
#define CFG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x4500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x4600)
/* I2C */
#define I2C_PCA9557_ADDR1 0x18
@@ -349,8 +329,7 @@ extern unsigned long get_sdram_size(void);
/* enable read and write access to EEPROM */
/* RTC */
#define CONFIG_RTC_PT7C4338
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* SPI interface will not be available in case of NAND boot SPI CS0 will be
@@ -360,37 +339,6 @@ extern unsigned long get_sdram_size(void);
/* eSPI - Enhanced SPI */
#endif
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 1
#define TSEC2_PHY_ADDR 0
#define TSEC3_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
/* TBI PHY configuration for SGMII mode */
#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
@@ -400,7 +348,7 @@ extern unsigned long get_sdram_size(void);
*/
#if defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#define SPL_ENV_ADDR (CFG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
#endif
@@ -417,19 +365,16 @@ extern unsigned long get_sdram_size(void);
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"loadaddr=1000000\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \

254
include/configs/P2041RDB.h
View File

@@ -12,31 +12,24 @@
#define __CONFIG_H
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
/* High Level Configuration Options */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
@@ -45,56 +38,53 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
#define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
CONFIG_RAMBOOT_TEXT_BASE)
#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE)
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
#endif
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CFG_SYS_DCSRBAR 0xf0000000
#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* Local Bus Definitions
*/
/* Set the local bus clock 1/8 of platform clock */
#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
/*
* This board doesn't have a promjet connector.
* However, it uses commone corenet board LAW and TLB.
* It is necessary to use the same start address with proper offset.
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CFG_SYS_FLASH_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_FSL_CPLD
#define CPLD_BASE 0xffdf0000 /* CPLD registers */
#ifdef CONFIG_PHYS_64BIT
#define CPLD_BASE_PHYS 0xfffdf0000ull
@@ -107,26 +97,24 @@
#define PIXIS_LBMAP_SHIFT 4
#define PIXIS_LBMAP_ALTBANK 0x40
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BASE 0xffa00000
#define CFG_SYS_NAND_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
@@ -136,44 +124,39 @@
| OR_FCM_EHTR)
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_HWCONFIG
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CFG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -181,49 +164,49 @@
/*
* RapidIO
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#else
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000
#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
@@ -236,75 +219,68 @@
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CFG_SYS_BMAN_NUM_PORTALS 10
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
#define CFG_SYS_BMAN_MEM_SIZE 0x00200000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_NUM_PORTALS 10
#define CFG_SYS_QMAN_MEM_BASE 0xf4200000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
#else
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CFG_SYS_QMAN_MEM_SIZE 0x00200000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
#define CONFIG_SYS_TBIPA_VALUE 8
#define CFG_SYS_TBIPA_VALUE 8
#endif
#ifdef CONFIG_MMC
@@ -320,21 +296,19 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH u-boot.bin
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1\0" \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \

20
include/configs/SBx81LIFKW.h
View File

@@ -7,15 +7,13 @@
#define _CONFIG_SBX81LIFKW_H
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
* Serial Port configuration
@@ -23,7 +21,6 @@
* for your console driver.
*/
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
#define MTDPARTS_MTDOOPS "errlog"
/*
@@ -34,19 +31,10 @@
* U-Boot bootcode configuration
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
#include <asm/arch/config.h>
/* There is no PHY directly connected so don't ask it for link status */
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_SBX81LIFKW_H */

20
include/configs/SBx81LIFXCAT.h
View File

@@ -7,15 +7,13 @@
#define _CONFIG_SBX81LIFXCAT_H
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
#define CFG_SYS_NS16550_CLK CFG_SYS_TCLK
#define CFG_SYS_NS16550_COM1 KW_UART0_BASE
/*
* Serial Port configuration
@@ -23,7 +21,6 @@
* for your console driver.
*/
#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
#define MTDPARTS_MTDOOPS "errlog"
/*
@@ -39,19 +36,10 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */
#include <asm/arch/config.h>
/* There is no PHY directly connected so don't ask it for link status */
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_SBX81LIFXCAT_H */

357
include/configs/T102xRDB.h
View File

@@ -15,195 +15,187 @@
/* High Level Configuration Options */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* PCIe Boot - Master */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#else
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#endif
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#else
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
#endif
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* PCIe Boot - Slave */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
/* Set 1M boot space for PCIe boot */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CFG_SYS_DCSRBAR 0xf0000000
#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#if defined(CONFIG_TARGET_T1024RDB)
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_SDRAM_SIZE 2048
#define CFG_SYS_SDRAM_SIZE 2048
#endif
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe8000000
#define CFG_SYS_FLASH_BASE 0xe8000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
#define CFG_SYS_NOR0_CSPR_EXT (0xf)
#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
#ifdef CONFIG_TARGET_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
#define CFG_SYS_CPLD_BASE 0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR2_EXT (0xf)
#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2 0x0
#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
#define CFG_SYS_CS2_FTIM3 0x0
#endif
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#else
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
#endif
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -211,7 +203,7 @@
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#elif defined(CONFIG_TARGET_T1023RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
@@ -221,91 +213,85 @@
#endif
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#else
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
#define CFG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
#endif
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CFG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -318,9 +304,7 @@
/*
* RTC configuration
*/
#define RTC
#define CONFIG_RTC_DS1337 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CFG_SYS_I2C_RTC_ADDR 0x68
/*
* eSPI - Enhanced SPI
@@ -334,26 +318,24 @@
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#endif
#endif /* CONFIG_PCI */
@@ -370,40 +352,37 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CFG_SYS_BMAN_NUM_PORTALS 10
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#else
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
#endif
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_NUM_PORTALS 10
#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#else
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
#endif
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -432,13 +411,11 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE utmi
#ifdef CONFIG_ARCH_T1024
@@ -453,11 +430,11 @@
"fdtfile=t1023rdb/t1023rdb.dtb\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
ARCH_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
"netdev=eth0\0" \

384
include/configs/T104xRDB.h
View File

@@ -20,92 +20,82 @@
#ifdef CONFIG_MTD_RAW_NAND
#ifdef CONFIG_NXP_ESBC
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image.
*/
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
CONFIG_U_BOOT_HDR_SIZE)
#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + (16 << 10))
#else
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#endif
#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
#define CFG_SYS_NAND_U_BOOT_DST 0x30000000
#define CFG_SYS_NAND_U_BOOT_START 0x30000000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x30000FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x30000000)
#define CFG_SYS_MMC_U_BOOT_START (0x30000000)
#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif
/* High Level Configuration Options */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
/*
* For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
* Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
* (CONFIG_SYS_INIT_L3_VADDR) will be different.
* For Secure Boot CFG_SYS_INIT_L3_ADDR will be redefined and hence
* Physical address (CFG_SYS_INIT_L3_ADDR) and virtual address
* (CFG_SYS_INIT_L3_VADDR) will be different.
*/
#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
#define CFG_SYS_INIT_L3_VADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CFG_SYS_DCSRBAR 0xf0000000
#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe8000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CFG_SYS_FLASH_BASE 0xe8000000
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
#define CFG_SYS_NOR_CSPR_EXT (0xf)
#define CFG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/*
* TDM Definition
@@ -113,22 +103,20 @@
#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS}
/* CPLD on IFC */
#define CPLD_LBMAP_MASK 0x3F
@@ -139,56 +127,42 @@
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#if defined(CONFIG_TARGET_T1042RDB_PI)
#define CPLD_DIU_SEL_DFP 0x80
#elif defined(CONFIG_TARGET_T1042D4RDB)
#if defined(CONFIG_TARGET_T1042D4RDB)
#define CPLD_DIU_SEL_DFP 0xc0
#endif
#if defined(CONFIG_TARGET_T1040D4RDB)
#define CPLD_INT_MASK_ALL 0xFF
#define CPLD_INT_MASK_THERM 0x80
#define CPLD_INT_MASK_DVI_DFP 0x40
#define CPLD_INT_MASK_QSGMII1 0x20
#define CPLD_INT_MASK_QSGMII2 0x10
#define CPLD_INT_MASK_SGMI1 0x08
#define CPLD_INT_MASK_SGMI2 0x04
#define CPLD_INT_MASK_TDMR1 0x02
#define CPLD_INT_MASK_TDMR2 0x01
#endif
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
#define CFG_SYS_CPLD_BASE 0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR2_EXT (0xf)
#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2 0x0
#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
@@ -197,105 +171,93 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NOR_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NOR_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x8
#if defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042D4RDB)
#if defined(CONFIG_TARGET_T1042D4RDB)
/*
* RTC configuration
*/
#define RTC
#define CONFIG_RTC_DS1337 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CFG_SYS_I2C_RTC_ADDR 0x68
/*DVI encoder*/
#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
#endif
/*
@@ -310,34 +272,30 @@
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#ifdef CONFIG_PCIE2
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#ifdef CONFIG_PCIE3
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
#endif
/* controller 4, Base address 203000 */
#ifdef CONFIG_PCIE4
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000
#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
#endif
#endif /* CONFIG_PCI */
@@ -351,65 +309,39 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CFG_SYS_BMAN_NUM_PORTALS 10
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_NUM_PORTALS 10
#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
#elif defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
#elif defined(CONFIG_TARGET_T1042D4RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
#if defined(CONFIG_TARGET_T1042D4RDB)
#define CFG_SYS_SGMII1_PHY_ADDR 0x02
#define CFG_SYS_SGMII2_PHY_ADDR 0x03
#define CFG_SYS_SGMII3_PHY_ADDR 0x01
#endif
#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
#else
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#endif
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
#define CONFIG_VSC9953
#ifdef CONFIG_TARGET_T1040RDB
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
#else
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
#endif
#endif
#define CFG_SYS_RGMII1_PHY_ADDR 0x01
#define CFG_SYS_RGMII2_PHY_ADDR 0x02
#endif
/*
@@ -421,7 +353,7 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Dynamic MTD Partition support with mtdparts
@@ -430,30 +362,20 @@
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
#define __USB_PHY_TYPE utmi
#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
#ifdef CONFIG_TARGET_T1040RDB
#define FDTFILE "t1040rdb/t1040rdb.dtb"
#elif defined(CONFIG_TARGET_T1042RDB_PI)
#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
#elif defined(CONFIG_TARGET_T1042RDB)
#define FDTFILE "t1042rdb/t1042rdb.dtb"
#elif defined(CONFIG_TARGET_T1040D4RDB)
#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
#elif defined(CONFIG_TARGET_T1042D4RDB)
#if defined(CONFIG_TARGET_T1042D4RDB)
#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \

389
include/configs/T208xQDS.h
View File

@@ -13,81 +13,67 @@
#include <linux/stringify.h>
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#endif
#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
/* High Level Configuration Options */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CFG_SYS_DCSRBAR 0xf0000000
#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
@@ -96,39 +82,37 @@
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
#define CFG_SYS_FLASH_BASE 0xe0000000
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR0_CSPR_EXT (0xf)
#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
#define CFG_SYS_NOR1_CSPR_EXT (0xf)
#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
#define QIXIS_BASE 0xffdf0000
#define QIXIS_LBMAP_SWITCH 6
@@ -147,36 +131,36 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
#define CFG_SYS_CSPR3_EXT (0xf)
#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3 0x0
#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CFG_SYS_CSOR3 0x0
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
#define CFG_SYS_CS3_FTIM3 0x0
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@@ -185,100 +169,94 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR1_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_SIZE 0x00004000
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
@@ -304,39 +282,39 @@
/*
* RapidIO
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
@@ -348,60 +326,49 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000
#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000
#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS 18
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS 18
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CFG_SYS_BMAN_NUM_PORTALS 18
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_NUM_PORTALS 18
#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -438,23 +405,21 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:" \
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
"bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \

350
include/configs/T208xRDB.h
View File

@@ -13,76 +13,67 @@
#include <linux/stringify.h>
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
/* High Level Configuration Options */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CFG_SYS_NAND_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_NAND_U_BOOT_DST 0x00200000
#define CFG_SYS_NAND_U_BOOT_START 0x00200000
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
#define CFG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
#define CFG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST (0x00200000)
#define CFG_SYS_MMC_U_BOOT_START (0x00200000)
#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif /* CONFIG_RAMBOOT_PBL */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CFG_SYS_DCSRBAR 0xf0000000
#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
@@ -91,68 +82,66 @@
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe8000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
#define CFG_SYS_FLASH_BASE 0xe8000000
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
#define CFG_SYS_NOR0_CSPR_EXT (0xf)
#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS }
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
#define CFG_SYS_CPLD_BASE 0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR2_EXT (0xf)
#define CFG_SYS_CSPR2 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR2 0x0
#define CFG_SYS_AMASK2 IFC_AMASK(64*1024)
#define CFG_SYS_CSOR2 0x0
/* CPLD Timing parameters for IFC CS2 */
#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CFG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
#define CFG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
#define CFG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
#define CFG_SYS_CS2_FTIM3 0x0
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@@ -161,84 +150,78 @@
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_SIZE 0x00004000
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/*
* I2C
@@ -258,39 +241,39 @@
/*
* RapidIO
*/
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
@@ -302,60 +285,49 @@
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000
#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CFG_SYS_PCIE4_MEM_VIRT 0xc0000000
#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS 18
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS 18
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CFG_SYS_BMAN_NUM_PORTALS 18
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_NUM_PORTALS 18
#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -399,23 +371,21 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:" \
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
"bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \

316
include/configs/T4240RDB.h
View File

@@ -12,22 +12,21 @@
#include <linux/stringify.h>
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CFG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
#ifndef CONFIG_SDCARD
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CFG_RESET_VECTOR_ADDRESS 0xfffffffc
#else
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#ifdef CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#define CFG_RESET_VECTOR_ADDRESS 0x200FFC
#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CFG_SYS_MMC_U_BOOT_DST 0x00200000
#define CFG_SYS_MMC_U_BOOT_START 0x00200000
#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
#endif
#endif
@@ -35,71 +34,58 @@
/* High Level Configuration Options */
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#ifndef CFG_RESET_VECTOR_ADDRESS
#define CFG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
/*
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
#define CFG_SYS_INIT_L3_ADDR 0xFFFC0000
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#define CFG_SYS_DCSRBAR 0xf0000000
#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
/*
* DDR Setup
*/
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
/*
* IFC Definitions
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CONFIG_HWCONFIG
#define CFG_SYS_FLASH_BASE 0xe0000000
#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#define CFG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
#define CFG_SYS_INIT_RAM_ADDR_PHYS \
((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CFG_SYS_INIT_RAM_SIZE 0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
/* I2C */
@@ -109,27 +95,24 @@
*/
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
#define CFG_SYS_PCIE4_MEM_BUS 0xe0000000
#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
/*
* Miscellaneous configurable options
@@ -140,13 +123,11 @@
* have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
/*
* Environment Configuration
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
#define HVBOOT \
"setenv bootargs config-addr=0x60000000; " \
@@ -159,57 +140,53 @@
#define SPD_EEPROM_ADDRESS2 0x54
#define SPD_EEPROM_ADDRESS3 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
/*
* IFC Definitions
*/
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
#define CFG_SYS_NOR0_CSPR_EXT (0xf)
#define CFG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
#define CFG_SYS_NOR1_CSPR_EXT (0xf)
#define CFG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_16 | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CFG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
#define CFG_SYS_NOR_FTIM3 0x0
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS \
+ 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE 0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
#define CFG_SYS_NAND_BASE 0xff800000
#define CFG_SYS_NAND_BASE_PHYS (0xf00000000ull | CFG_SYS_NAND_BASE)
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
#define CFG_SYS_NAND_CSPR_EXT (0xf)
#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
| CSPR_MSEL_NAND /* MSEL = NAND */ \
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
@@ -218,88 +195,87 @@
| CSOR_NAND_PB(128)) /*Page Per Block = 128*/
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
FTIM0_NAND_TWCHT(0x07) | \
FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
FTIM1_NAND_TWBE(0x39) | \
FTIM1_NAND_TRR(0x0e) | \
FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
FTIM2_NAND_TREH(0x0a) | \
FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3 0x0
#define CFG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_DDR_LAW 11
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR2 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
#define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
#define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR
#define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR1_EXT CFG_SYS_NAND_CSPR_EXT
#define CFG_SYS_CSPR1 CFG_SYS_NAND_CSPR
#define CFG_SYS_AMASK1 CFG_SYS_NAND_AMASK
#define CFG_SYS_CSOR1 CFG_SYS_NAND_CSOR
#define CFG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
#define CFG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
#define CFG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
#define CFG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
#define CFG_SYS_CSPR2_EXT CFG_SYS_NOR1_CSPR_EXT
#define CFG_SYS_CSPR2 CFG_SYS_NOR1_CSPR
#define CFG_SYS_AMASK2 CFG_SYS_NOR_AMASK
#define CFG_SYS_CSOR2 CFG_SYS_NOR_CSOR
#define CFG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
#define CFG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
#define CFG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
#define CFG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR3_EXT (0xf)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
#define CFG_SYS_CPLD_BASE 0xffdf0000
#define CFG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CFG_SYS_CPLD_BASE)
#define CFG_SYS_CSPR3_EXT (0xf)
#define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3 0x0
#define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
#define CFG_SYS_CSOR3 0x0
/* CPLD Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
#define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
FTIM0_GPCM_TEADC(0x0e) | \
FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
#define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
#define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
#define CFG_SYS_CS3_FTIM3 0x0
/* I2C */
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
@@ -326,36 +302,28 @@
/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS 50
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS 50
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN
#define CFG_SYS_BMAN_NUM_PORTALS 50
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
#define CFG_SYS_BMAN_MEM_SIZE 0x02000000
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
CFG_SYS_BMAN_CENA_SIZE)
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
#define CFG_SYS_QMAN_NUM_PORTALS 50
#define CFG_SYS_QMAN_MEM_BASE 0xf6000000
#define CFG_SYS_QMAN_MEM_PHYS 0xff6000000ull
#define CFG_SYS_QMAN_MEM_SIZE 0x02000000
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
CFG_SYS_QMAN_CENA_SIZE)
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
@@ -400,13 +368,13 @@
#define CTRL_INTLV_PREFERED cacheline
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:" \
"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
"bank_intlv=auto;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \

17
include/configs/alt.h
View File

@@ -20,20 +20,17 @@
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* FLASH */
#define CONFIG_SPI_FLASH_QUAD
/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CFG_SH_ETHER_USE_PORT 0
#define CFG_SH_ETHER_PHY_ADDR 0x1
#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CFG_SH_ETHER_CACHE_WRITEBACK
#define CFG_SH_ETHER_CACHE_INVALIDATE
#define CFG_SH_ETHER_ALIGNE_SIZE 64
/* Board Clock */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"usb_pgood_delay=2000\0"

27
include/configs/am335x_evm.h
View File

@@ -78,7 +78,7 @@
#ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"fdtfile=undefined\0" \
"finduuid=part uuid mmc 0:2 uuid\0" \
@@ -158,20 +158,17 @@
#endif
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
#define CONFIG_POWER_TPS65910
#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -179,8 +176,8 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#endif /* !CONFIG_MTD_RAW_NAND */
/* USB Device Firmware Update support */
@@ -205,8 +202,8 @@
* 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
*/
#if defined(CONFIG_NOR)
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CFG_SYS_FLASH_BASE (0x08000000)
#define CFG_SYS_FLASH_SIZE 0x01000000
#endif /* NOR support */
#endif /* ! __CONFIG_AM335X_EVM_H */

21
include/configs/am335x_guardian.h
View File

@@ -45,7 +45,7 @@
"main_pcba_aux_3=0\0" \
"main_pcba_aux_4=0\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
AM335XX_BOARD_FDTFILE \
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV \
@@ -83,15 +83,15 @@
#define CONSOLE_COLOR_RED 0x001F
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -113,9 +113,8 @@
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define MTDIDS_DEFAULT "nand0=nand.0"
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 26
#endif /* CONFIG_MTD_RAW_NAND */

10
include/configs/am335x_igep003x.h
View File

@@ -20,7 +20,7 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
@@ -88,14 +88,14 @@
"echo WARNING: Could not determine device tree to use; fi; \0"
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
/* Ethernet support */
/* NAND support */
/* NAND config */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -103,7 +103,7 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#endif /* ! __CONFIG_IGEP003X_H */

16
include/configs/am335x_shc.h
View File

@@ -20,10 +20,8 @@
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_HSMMC2_8BIT
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"kloadaddr=0x84000000\0" \
"fdtaddr=0x85000000\0" \
@@ -136,11 +134,11 @@
#endif /* Regular Boot */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CFG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#endif /* ! __CONFIG_AM335X_SHC_H */

21
include/configs/am335x_sl50.h
View File

@@ -30,24 +30,17 @@
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
AM335XX_BOARD_FDTFILE \
MEM_LAYOUT_ENV_SETTINGS \
BOOTENV
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
#define CONFIG_POWER_TPS65910
/* SPL */
/* Network. */
#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#endif /* ! __CONFIG_AM335X_SL50_H */

14
include/configs/am3517_evm.h
View File

@@ -16,18 +16,16 @@
/* Board NAND Info. */
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
11, 12, 13, 14, 16, 17, 18, 19, 20, \
21, 22, 23, 24, 25, 26, 27, 28, 30, \
31, 32, 33, 34, 35, 36, 37, 38, 39, \
40, 41, 42, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56 }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 13
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
* MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000
@@ -40,7 +38,7 @@
#endif /* CONFIG_MTD_RAW_NAND */
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS2,115200n8\0" \
"fdtfile=am3517-evm.dtb\0" \
@@ -91,7 +89,7 @@
/* on one chip */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#define CFG_SYS_FLASH_BASE NAND_BASE
#endif
#endif /* __CONFIG_H */

32
include/configs/am43xx_evm.h
View File

@@ -8,28 +8,16 @@
#ifndef __CONFIG_AM43XX_EVM_H
#define __CONFIG_AM43XX_EVM_H
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CFG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CFG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_CLK 48000000
#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_SERIAL
#endif
/* I2C Configuration */
/* Power */
#define CONFIG_POWER_TPS65218
#define CONFIG_POWER_TPS62362
/* SPL defines. */
#define CFG_SYS_NS16550_CLK 48000000
/* Enabling L2 Cache */
#define CONFIG_SYS_PL310_BASE 0x48242000
#define CFG_SYS_PL310_BASE 0x48242000
/*
* When building U-Boot such that there is no previous loader
@@ -45,7 +33,7 @@
#define V_SCLK (V_OSCK)
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#ifndef CONFIG_SPL_BUILD
/* USB Device Firmware Update support */
@@ -78,7 +66,7 @@
#ifndef CONFIG_SPL_BUILD
#include <environment/ti/dfu.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"fdtfile=undefined\0" \
"finduuid=part uuid mmc 0:2 uuid\0" \
@@ -120,7 +108,7 @@
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
@@ -142,8 +130,8 @@
190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 26
#define NANDARGS \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
@@ -164,7 +152,7 @@
#if defined(CONFIG_TI_SECURE_DEVICE)
/* Avoid relocating onto firewalled area at end of DRAM */
#define CONFIG_PRAM (64 * 1024)
#define CFG_PRAM (64 * 1024)
#endif /* CONFIG_TI_SECURE_DEVICE */
#endif /* __CONFIG_AM43XX_EVM_H */

19
include/configs/am57xx_evm.h
View File

@@ -14,13 +14,9 @@
#include <environment/ti/dfu.h>
#include <linux/sizes.h>
#define CONFIG_IODELAY_RECALIBRATION
#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#define CONFIG_SYS_OMAP_ABE_SYSCK
#define CFG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */
#define CFG_SYS_NS16550_COM2 UART2_BASE /* UART2 */
#define CFG_SYS_NS16550_COM3 UART3_BASE /* UART3 */
#ifndef CONFIG_SPL_BUILD
#define DFUARGS \
@@ -39,9 +35,6 @@
#include <configs/ti_omap5_common.h>
/* Enhance our eMMC support / experience. */
#define CONFIG_HSMMC2_8BIT
/* CPSW Ethernet */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
@@ -55,9 +48,9 @@
* 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
* 0x9E0000 - 0x2000000 : USERLAND
*/
#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#define CFG_SYS_SPI_KERNEL_OFFS 0x1E0000
#define CFG_SYS_SPI_ARGS_OFFS 0x140000
#define CFG_SYS_SPI_ARGS_SIZE 0x80000
/* SPI SPL */

68
include/configs/am62ax_evm.h Normal file
View File

@@ -0,0 +1,68 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration header file for K3 AM62Ax SoC family
*
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __CONFIG_AM62AX_EVM_H
#define __CONFIG_AM62AX_EVM_H
#include <linux/sizes.h>
#include <config_distro_bootcmd.h>
#include <environment/ti/mmc.h>
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" \
/* U-Boot general configuration */
#define EXTRA_ENV_AM62A7_BOARD_SETTINGS \
"default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"findfdt=" \
"setenv name_fdt ${default_device_tree};" \
"setenv fdtfile ${name_fdt}\0" \
"name_kern=Image\0" \
"console=ttyS2,115200n8\0" \
"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \
"${mtdparts}\0" \
"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
/* U-Boot MMC-specific configuration */
#define EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \
"boot=mmc\0" \
"mmcdev=1\0" \
"bootpart=1:2\0" \
"bootdir=/boot\0" \
"rd_spec=-\0" \
"init_mmc=run args_all args_mmc\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \
"get_overlay_mmc=" \
"fdt address ${fdtaddr};" \
"fdt resize 0x100000;" \
"for overlay in $name_overlays;" \
"do;" \
"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
"fdt apply ${dtboaddr};" \
"done;\0" \
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
"${bootdir}/${name_kern}\0" \
"get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
"${bootdir}/${name_fit}\0" \
"partitions=" PARTS_DEFAULT
/* Incorporate settings into the U-Boot environment */
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_AM62A7_BOARD_SETTINGS \
EXTRA_ENV_AM62A7_BOARD_SETTINGS_MMC \
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
#endif /* __CONFIG_AM62A7_EVM_H */

4
include/configs/am62x_evm.h
View File

@@ -13,7 +13,7 @@
#include <environment/ti/mmc.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
@@ -55,7 +55,7 @@
"partitions=" PARTS_DEFAULT
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_AM625_BOARD_SETTINGS \

4
include/configs/am64x_evm.h
View File

@@ -16,7 +16,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
@@ -95,7 +95,7 @@
DFU_ALT_INFO_OSPI
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_AM642_BOARD_SETTINGS \

4
include/configs/am65x_evm.h
View File

@@ -15,7 +15,7 @@
#include <environment/ti/k3_dfu.h>
/* DDR Configuration */
#define CONFIG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define PARTS_DEFAULT \
/* Linux partitions */ \
@@ -88,7 +88,7 @@
#endif
/* Incorporate settings into the U-Boot environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
DEFAULT_MMC_TI_ARGS \
DEFAULT_FIT_TI_ARGS \

52
include/configs/amcore.h
View File

@@ -8,11 +8,9 @@
#ifndef __AMCORE_CONFIG_H
#define __AMCORE_CONFIG_H
#define CONFIG_HOSTNAME "AMCORE"
#define CFG_SYS_UART_PORT 0
#define CONFIG_SYS_UART_PORT 0
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"upgrade_uboot=loady; " \
"protect off 0xffc00000 0xffc1ffff; " \
"erase 0xffc00000 0xffc1ffff; " \
@@ -24,21 +22,21 @@
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
#define CONFIG_SYS_CLK 45000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
#define CFG_SYS_CLK 45000000
#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 2)
/* Register Base Addrs */
#define CONFIG_SYS_MBAR 0x10000000
#define CFG_SYS_MBAR 0x10000000
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CFG_SYS_INIT_RAM_ADDR 0x20000000
/* size of internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CFG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_FLASH_BASE 0xffc00000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 0x1000000
#define CFG_SYS_FLASH_BASE 0xffc00000
/* amcore design has flash data bytes wired swapped */
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#define CFG_SYS_WRITE_SWAPPED_DATA
/* reserve 128-4KB */
#define LDS_BOARD_TEXT \
@@ -46,7 +44,7 @@
env/embedded.o(.text*);
/* memory map space for linux boot data */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CFG_SYS_BOOTMAPSZ (8 << 20)
/*
* Cache Configuration
@@ -56,25 +54,25 @@
* sdram - single region - no masks
*/
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CFG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \
CF_ACR_EN)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \
CF_CACR_EC)
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
#define CFG_SYS_CS0_BASE (CFG_SYS_FLASH_BASE>>16)
/* 4MB, AA=0,V=1 C/I BIT for errata */
#define CONFIG_SYS_CS0_MASK 0x003f0001
#define CFG_SYS_CS0_MASK 0x003f0001
/* WS=10, AA=1, PS=16bit (10) */
#define CONFIG_SYS_CS0_CTRL 0x1980
#define CFG_SYS_CS0_CTRL 0x1980
/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
#define CONFIG_SYS_CS1_BASE 0x3000
#define CONFIG_SYS_CS1_MASK 0x00070001
#define CONFIG_SYS_CS1_CTRL 0x0100
#define CFG_SYS_CS1_BASE 0x3000
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x0100
#endif /* __AMCORE_CONFIG_H */

6
include/configs/ap121.h
View File

@@ -6,10 +6,10 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Miscellaneous configurable options */

8
include/configs/ap143.h
View File

@@ -6,15 +6,15 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
#define CFG_SYS_INIT_RAM_SIZE 0x2000
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_CLK 25000000
#define CFG_SYS_NS16550_CLK 25000000
/* Miscellaneous configurable options */

8
include/configs/ap152.h
View File

@@ -6,15 +6,15 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
#define CFG_SYS_INIT_RAM_ADDR 0xbd000000
#define CFG_SYS_INIT_RAM_SIZE 0x2000
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_CLK 25000000
#define CFG_SYS_NS16550_CLK 25000000
/* Miscellaneous configurable options */

7
include/configs/apalis-imx8.h
View File

@@ -14,9 +14,6 @@
#define USDHC2_BASE_ADDR 0x5b020000
/* Networking */
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x84000000\0" \
@@ -34,7 +31,7 @@
#define BOOTENV_RUN_NET_USB_START ""
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
@@ -63,7 +60,7 @@
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */

9
include/configs/apalis-tk1.h
View File

@@ -13,8 +13,7 @@
#include "tegra124-common.h"
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define FDT_MODULE "apalis-v1.2"
#define FDT_MODULE_V1_0 "apalis"
@@ -33,12 +32,6 @@
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#undef CONFIG_IPADDR
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
"boot part 0 1 mmcpart 0; " \
"rootfs part 0 2 mmcpart 0; " \

28
include/configs/apalis_imx6.h
View File

@@ -15,11 +15,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
#ifdef CONFIG_SPL
#include "imx6_spl.h"
#endif
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CFG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR 0
@@ -30,23 +26,13 @@
/* USB Configs */
/* Host */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
/* Client */
#define CONFIG_USBD_HS
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* Framebuffer and LCD */
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
/* Command definition */
#undef CONFIG_IPADDR
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
@@ -76,7 +62,7 @@
"ramdisk_addr_r=0x18400000\0" \
"scriptaddr=0x18280000\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
"boot_file=zImage\0" \
"boot_script_dhcp=boot.scr\0" \
@@ -110,8 +96,8 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */

3
include/configs/apalis_t30.h
View File

@@ -20,8 +20,7 @@
* Apalis UART3: NVIDIA UARTB
* Apalis UART4: NVIDIA UARTC
*/
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define UBOOT_UPDATE \
"uboot_hwpart=1\0" \

2
include/configs/apple.h
View File

@@ -27,7 +27,7 @@
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
ENV_DEVICE_SETTINGS \
BOOTENV

10
include/configs/arbel.h
View File

@@ -6,13 +6,13 @@
#ifndef __CONFIG_ARBEL_H
#define __CONFIG_ARBEL_H
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_BOOTMAPSZ (20 << 20)
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#define CFG_SYS_SDRAM_BASE 0x0
#define CFG_SYS_BOOTMAPSZ (20 << 20)
#define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE
#define CFG_SYS_INIT_RAM_SIZE 0x8000
/* Default environemnt variables */
#define CONFIG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \

28
include/configs/aristainetos2.h
View File

@@ -11,8 +11,6 @@
#ifndef __ARISTAINETOS2_CONFIG_H
#define __ARISTAINETOS2_CONFIG_H
#define CONFIG_HOSTNAME "aristainetos2"
#if (CONFIG_SYS_BOARD_VERSION == 5)
#define CONSOLE_DEV "ttymxc1"
#elif (CONFIG_SYS_BOARD_VERSION == 6)
@@ -20,7 +18,7 @@
#endif
/* Framebuffer */
#define CONFIG_SYS_LDB_CLOCK 28341000
#define CFG_SYS_LDB_CLOCK 28341000
#include "mx6_common.h"
@@ -28,9 +26,7 @@
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define CFG_FEC_MXC_PHYADDR 0
#ifdef CONFIG_IMX_HAB
#define HAB_EXTRA_SETTINGS \
@@ -98,7 +94,7 @@
"done\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"disable_giga=yes\0" \
"usb_pgood_delay=2000\0" \
"nor_bootdelay=-2\0" \
@@ -408,27 +404,21 @@
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_FSL_USDHC_NUM 2
/* DMA stuff, needed for GPMI/MXS NAND support */
/* USB Configs */
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_MXC_USB_FLAGS 0
/* UBI support */
/* Framebuffer */
/* check this console not needed, after test remove it */
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_IMX6_PWM_PER_CLK 66000000
#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \
#define CFG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \
"sysnum:dw,panel:sw,ipaddr:iw,serverip:iw"
#endif /* __ARISTAINETOS2_CONFIG_H */

4
include/configs/arndale.h
View File

@@ -16,9 +16,9 @@
/* Miscellaneous configurable options */
#define CONFIG_SMP_PEN_ADDR 0x02020000
#define CFG_SMP_PEN_ADDR 0x02020000
/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000
#define CFG_ARM_GIC_BASE_ADDRESS 0x10480000
#endif /* __CONFIG_H */

10
include/configs/aspeed-common.h
View File

@@ -14,14 +14,14 @@
/* Misc CPU related */
#define CONFIG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#define CFG_SYS_SDRAM_BASE ASPEED_DRAM_BASE
#ifdef CONFIG_PRE_CON_BUF_SZ
#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE + CONFIG_PRE_CON_BUF_SZ)
#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE - CONFIG_PRE_CON_BUF_SZ)
#else
#define CONFIG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
#define CONFIG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
#define CFG_SYS_INIT_RAM_ADDR (ASPEED_SRAM_BASE)
#define CFG_SYS_INIT_RAM_SIZE (ASPEED_SRAM_SIZE)
#endif
/*

113
include/configs/astro_mcf5373l.h
View File

@@ -38,16 +38,6 @@
#error No card type defined!
#endif
/*
* CONFIG_RAM defines if u-boot is loaded via BDM (or started from
* a different bootloader that has already performed RAM setup) or
* started directly from flash, which is the regular case for production
* boards.
*/
#ifdef CONFIG_RAM
#define CONFIG_MONITOR_IS_IN_RAM
#endif
/* I2C */
/*
@@ -55,44 +45,19 @@
* interface etc.
*/
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3)
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SYS_CLK 80000000
#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3)
#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
/*
* Define baudrate for UART1 (console output, tftp, ...)
* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
* CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
* CFG_SYS_BAUDRATE_TABLE defines values that can be selected
* in u-boot command interface
*/
#define CONFIG_SYS_UART_PORT (2)
#define CONFIG_SYS_UART2_ALT3_GPIO
/*
* Watchdog configuration; Watchdog is disabled for running from RAM
* and set to highest possible value else. Beware there is no check
* in the watchdog code to validate the timeout value set here!
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */
#endif
/*
* Configuration for environment
* Environment is located in the last sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#else
/*
* environment in RAM - This is used to use a single PC-based application
* to load an image, load U-Boot, load an environment and then start U-Boot
* to execute the commands from the environment. Feedback is done via setting
* and reading memory locations.
*/
#endif
#define CFG_SYS_UART_PORT (2)
#define CFG_SYS_UART2_ALT3_GPIO
/* here we put our FPGA configuration... */
@@ -106,7 +71,7 @@
* u-boot: 'set' command
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"loaderversion=11\0" \
"card_id="__stringify(ASTRO_ID)"\0" \
"alterafile=0\0" \
@@ -125,7 +90,7 @@
* it needs non-blocking CFI routines.
*/
#define CONFIG_SYS_FPGA_WAIT 1000
#define CFG_SYS_FPGA_WAIT 1000
/* End of user parameters to be customized */
@@ -139,26 +104,26 @@
/* Base register address */
#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */
/* System Conf. Reg. & System Protection Reg. */
#define CONFIG_SYS_SCR 0x0003;
#define CONFIG_SYS_SPR 0xffff;
#define CFG_SYS_SCR 0x0003;
#define CFG_SYS_SPR 0xffff;
/*
* Definitions for initial stack pointer and data area (in internal SRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x8000
#define CFG_SYS_INIT_RAM_CTRL 0x221
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CFG_SYS_SDRAM_BASE 0x40000000
/*
* Chipselect bank definitions
@@ -170,23 +135,23 @@
* CS4 - unused
* CS5 - unused
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x00ff0001
#define CONFIG_SYS_CS0_CTRL 0x00001fc0
#define CFG_SYS_CS0_BASE 0
#define CFG_SYS_CS0_MASK 0x00ff0001
#define CFG_SYS_CS0_CTRL 0x00001fc0
#define CONFIG_SYS_CS1_BASE 0x01000000
#define CONFIG_SYS_CS1_MASK 0x00ff0001
#define CONFIG_SYS_CS1_CTRL 0x00001fc0
#define CFG_SYS_CS1_BASE 0x01000000
#define CFG_SYS_CS1_MASK 0x00ff0001
#define CFG_SYS_CS1_CTRL 0x00001fc0
#define CONFIG_SYS_CS2_BASE 0x20000000
#define CONFIG_SYS_CS2_MASK 0x00ff0001
#define CONFIG_SYS_CS2_CTRL 0x0000fec0
#define CFG_SYS_CS2_BASE 0x20000000
#define CFG_SYS_CS2_MASK 0x00ff0001
#define CFG_SYS_CS2_CTRL 0x0000fec0
#define CONFIG_SYS_CS3_BASE 0x21000000
#define CONFIG_SYS_CS3_MASK 0x00ff0001
#define CONFIG_SYS_CS3_CTRL 0x0000fec0
#define CFG_SYS_CS3_BASE 0x21000000
#define CFG_SYS_CS3_MASK 0x00ff0001
#define CFG_SYS_CS3_CTRL 0x0000fec0
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CFG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */
@@ -195,12 +160,12 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
(CONFIG_SYS_SDRAM_SIZE << 20))
#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
(CFG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_FLASH_SIZE 0x2000000
#define CFG_SYS_FLASH_SIZE 0x2000000
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
@@ -208,15 +173,15 @@
/* Cache Configuration */
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 4)
#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
#endif /* _CONFIG_ASTRO_MCF5373L_H */

4
include/configs/at91-sama5_common.h
View File

@@ -12,7 +12,7 @@
#include <linux/kconfig.h>
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768
#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#endif

27
include/configs/at91sam9260ek.h
View File

@@ -24,34 +24,33 @@
*/
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
/*
* SDRAM: 1 bank, min 32, max 128 MB
* Initialized before u-boot gets started.
*/
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
#ifdef CONFIG_AT91SAM9XE
# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
#else
# define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
# define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
#endif
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC13
#endif
/* USB */
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#endif

32
include/configs/at91sam9261ek.h
View File

@@ -11,38 +11,30 @@
#define __CONFIG_H
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CFG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#include <asm/hardware.h>
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
#define CFG_SYS_NAND_MASK_CLE (1 << 21)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC15
#endif
/* Ethernet */
#define CONFIG_DM9000_BASE 0x30000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT
#define CONFIG_DM9000_NO_SROM
/* USB */
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#define CFG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
#endif

97
include/configs/at91sam9263ek.h
View File

@@ -19,24 +19,24 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CFG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM1
/* NOR flash, if populated */
#ifdef CONFIG_SYS_USE_NORFLASH
#define PHYS_FLASH_1 0x10000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Primary Environment Sector */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=" \
"protect off ${monitor_base} +${filesize};" \
@@ -50,9 +50,9 @@
#define MASTER_PLL_OUT 3
/* clocks */
#define CONFIG_SYS_MOR_VAL \
#define CFG_SYS_MOR_VAL \
(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
#define CONFIG_SYS_PLLAR_VAL \
#define CFG_SYS_PLLAR_VAL \
(AT91_PMC_PLLAR_29 | \
AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
AT91_PMC_PLLXR_PLLCOUNT(63) | \
@@ -60,31 +60,31 @@
AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
#define CFG_SYS_MCKR1_VAL \
(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
#define CFG_SYS_MCKR2_VAL \
(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
AT91_PMC_MCKR_MDIV_2)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
#define CFG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
#define CFG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
#define CFG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
AT91_MATRIX_CSA_EBI_CS1A)
/* SDRAM */
/* SDRAMC_MR Mode register */
#define CONFIG_SYS_SDRC_MR_VAL1 0
#define CFG_SYS_SDRC_MR_VAL1 0
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
#define CFG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
#define CFG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
@@ -98,47 +98,47 @@
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
#define CFG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CFG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
#define CFG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
#define CFG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
#define CFG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
#define CFG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
#define CFG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
#define CFG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
#define CFG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
#define CFG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
#define CFG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
#define CFG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC0_SETUP0_VAL \
#define CFG_SYS_SMC0_SETUP0_VAL \
(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
#define CONFIG_SYS_SMC0_PULSE0_VAL \
#define CFG_SYS_SMC0_PULSE0_VAL \
(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
#define CONFIG_SYS_SMC0_CYCLE0_VAL \
#define CFG_SYS_SMC0_CYCLE0_VAL \
(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
#define CONFIG_SYS_SMC0_MODE0_VAL \
#define CFG_SYS_SMC0_MODE0_VAL \
(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
AT91_SMC_MODE_DBW_16 | \
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
#define CFG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_MR_URSTEN | \
AT91_RSTC_MR_ERSTL(15))
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
#define CFG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
AT91_WDT_MR_WDV(0xfff) | \
AT91_WDT_MR_WDDIS | \
@@ -150,17 +150,16 @@
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PA22
#endif
/* USB */
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#define CFG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
#endif

35
include/configs/at91sam9m10g45ek.h
View File

@@ -11,40 +11,39 @@
#define __CONFIG_H
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768
#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE 0x70000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
#ifdef CONFIG_SD_BOOT
#elif CONFIG_NAND_BOOT
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CFG_SYS_NAND_U_BOOT_SIZE 0x80000
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
#define CFG_SYS_NAND_ECCSIZE 256
#define CFG_SYS_NAND_ECCBYTES 3
#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52, 53, 54, 55, \
56, 57, 58, 59, 60, 61, 62, 63, }
#endif
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define CFG_SYS_MASTER_CLOCK 132096000
#define CFG_SYS_AT91_PLLA 0x20c73f03
#define CFG_SYS_MCKR 0x1301
#define CFG_SYS_MCKR_CSS 0x1302
#endif

28
include/configs/at91sam9n12ek.h
View File

@@ -10,34 +10,34 @@
#define __AT91SAM9N12_CONFIG_H_
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CFG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */
/* Misc CPU related */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x08000000
/* DataFlash */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#define CFG_SYS_NAND_BASE 0x40000000
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4)
#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PD(5)
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
/* SPL */
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20953f03
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define CFG_SYS_MASTER_CLOCK 132096000
#define CFG_SYS_AT91_PLLA 0x20953f03
#define CFG_SYS_MCKR 0x1301
#define CFG_SYS_MCKR_CSS 0x1302
#endif

23
include/configs/at91sam9rlek.h
View File

@@ -13,26 +13,25 @@
#include <asm/hardware.h>
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000
#define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CFG_SYS_SDRAM_SIZE 0x04000000
#define CONFIG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
#define CFG_SYS_INIT_RAM_SIZE (16 * 1024)
#define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8 1
#define CFG_SYS_NAND_BASE ATMEL_BASE_CS3
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17
#endif

27
include/configs/at91sam9x5ek.h
View File

@@ -9,8 +9,8 @@
#define __CONFIG_H__
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CFG_SYS_AT91_SLOW_CLOCK 32768
#define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
/* general purpose I/O */
@@ -20,28 +20,27 @@
*/
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
#define CFG_SYS_SDRAM_BASE 0x20000000
#define CFG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* DataFlash */
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CFG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CFG_SYS_NAND_MASK_CLE (1 << 22)
#define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CFG_SYS_NAND_READY_PIN AT91_PIN_PD5
#endif
/* SPL */
#define CONFIG_SYS_MASTER_CLOCK 132096000
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define CFG_SYS_MASTER_CLOCK 132096000
#define CFG_SYS_AT91_PLLA 0x20c73f03
#define CFG_SYS_MCKR 0x1301
#define CFG_SYS_MCKR_CSS 0x1302
#endif

21
include/configs/ax25-ae350.h
View File

@@ -28,33 +28,26 @@
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_0
/*
* Serial console configuration
*/
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#endif
#define CONFIG_SYS_NS16550_CLK 19660800
#define CFG_SYS_NS16550_CLK 19660800
/* Init Stack Pointer */
/* support JEDEC */
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
#define CFG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
/* max number of memory banks */
/*
* There are 4 banks supported for this Controller,
* but we have only 1 bank connected to flash on board
*/
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
#define CFG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* environments */
@@ -67,7 +60,7 @@
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
#define CFG_SYS_BOOTMAPSZ (64 << 20)
/* Increase max gunzip size */
/* Support autoboot from RAM (kernel image is loaded via debug port) */
@@ -89,7 +82,7 @@
func(RAM, ram, na)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x00080000\0" \
"pxefile_addr_r=0x01f00000\0" \
"scriptaddr=0x01f00000\0" \

12
include/configs/axs10x.h
View File

@@ -19,16 +19,14 @@
* Memory configuration
*/
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_512M
#define CFG_SYS_DDR_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
#define CFG_SYS_SDRAM_SIZE SZ_512M
/*
* UART configuration
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 33333333
#define CONFIG_SYS_NS16550_MEM32
#define CFG_SYS_NS16550_CLK 33333333
/*
* Ethernet PHY configuration
@@ -41,7 +39,7 @@
/*
* Environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"upgrade=if mmc rescan && " \
"fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \
"iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \

25
include/configs/baltos.h
View File

@@ -49,7 +49,7 @@
#define NANDARGS ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"boot_fdt=try\0" \
"bootpart=0:2\0" \
@@ -181,21 +181,18 @@
/*DFUARGS*/
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* PMIC support */
#define CONFIG_POWER_TPS65910
#define CFG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CFG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CFG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CFG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CFG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CFG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
/* SPL */
#ifndef CONFIG_NOR_BOOT
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
@@ -203,9 +200,9 @@
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#define CFG_SYS_NAND_ECCSIZE 512
#define CFG_SYS_NAND_ECCBYTES 14
#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
#endif
#endif

2
include/configs/bayleybay.h
View File

@@ -12,7 +12,7 @@
#include <configs/x86-common.h>
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
#define CFG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"

4
include/configs/bcm7260.h
View File

@@ -10,9 +10,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_NS16550_COM1 0xf040c000
#define CFG_SYS_NS16550_COM1 0xf040c000
#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000
#define CFG_SYS_INIT_RAM_ADDR 0x10200000
#include "bcmstb.h"

4
include/configs/bcm7445.h
View File

@@ -10,9 +10,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_NS16550_COM1 0xf040ab00
#define CFG_SYS_NS16550_COM1 0xf040ab00
#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000
#define CFG_SYS_INIT_RAM_ADDR 0x80200000
#include "bcmstb.h"

2
include/configs/bcm947622.h
View File

@@ -6,7 +6,7 @@
#ifndef __BCM947622_H
#define __BCM947622_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define COUNTER_FREQUENCY 50000000
#endif

2
include/configs/bcm94908.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM94908_H
#define __BCM94908_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm94912.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM94912_H
#define __BCM94912_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

4
include/configs/bcm963138.h
View File

@@ -6,7 +6,7 @@
#ifndef __BCM963138_H
#define __BCM963138_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_HZ_CLOCK 500000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_HZ_CLOCK 500000000
#endif

2
include/configs/bcm963146.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963146_H
#define __BCM963146_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963148.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963148_H
#define __BCM963148_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963158.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963158_H
#define __BCM963158_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm963178.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM963178_H
#define __BCM963178_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96756.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96756_H
#define __BCM96756_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96813.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96813_H
#define __BCM96813_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96846.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96846_H
#define __BCM96846_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96855.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96855_H
#define __BCM96855_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96856.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96856_H
#define __BCM96856_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96858.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96858_H
#define __BCM96858_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

2
include/configs/bcm96878.h
View File

@@ -6,6 +6,6 @@
#ifndef __BCM96878_H
#define __BCM96878_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#endif

8
include/configs/bcm_ns3.h
View File

@@ -9,13 +9,11 @@
#include <linux/sizes.h>
#define CONFIG_HOSTNAME "NS3"
/* Physical Memory Map */
#define V2M_BASE 0x80000000
#define PHYS_SDRAM_1 V2M_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
/*
* Initial SP before reloaction is placed at end of first DRAM bank,
@@ -26,7 +24,7 @@
/* 12MB Malloc size */
/* console configuration */
#define CONFIG_SYS_NS16550_CLK 25000000
#define CFG_SYS_NS16550_CLK 25000000
/*
* Increase max uncompressed/gunzip size, keeping size same as EMMC linux
@@ -795,7 +793,7 @@
QSPI_FLASH \
FLASH_IMAGES
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
ARCH_ENV_SETTINGS
#endif /* __BCM_NS3_H */

12
include/configs/bcmstb.h
View File

@@ -81,8 +81,8 @@ extern phys_addr_t prior_stage_fdt_address;
* MiB. However, BOLT can be configured to allow loading larger
* initramfs images, in which case this limitation is eliminated.
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x100000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_INIT_RAM_SIZE 0x100000
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.
@@ -97,14 +97,12 @@ extern phys_addr_t prior_stage_fdt_address;
*/
#define V_NS16550_CLK 81000000
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CFG_SYS_NS16550_CLK V_NS16550_CLK
/*
* Serial console configuration.
*/
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
#define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
/*
@@ -133,7 +131,7 @@ extern phys_addr_t prior_stage_fdt_address;
/*
* Enable in-place RFS with this initrd_high setting.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0" \
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0"

4
include/configs/beacon-rzg2m.h
View File

@@ -8,9 +8,9 @@
#include "rcar-gen3-common.h"
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CFG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"usb_pgood_delay=2000\0" \
"script=boot.scr\0" \
"image=Image\0" \

12
include/configs/beaver.h
View File

@@ -10,19 +10,11 @@
#include "tegra30-common.h"
/* VDD core PMIC */
#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
/* High-level configuration options */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver"
#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver"
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* SPI */
#define CONFIG_TEGRA_SLINK_CTRLS 6
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#include "tegra-common-post.h"

6
include/configs/bitmain_antminer_s9.h
View File

@@ -6,10 +6,10 @@
#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H
#define __CONFIG_BITMAIN_ANTMINER_S9_H
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
#define CFG_SYS_SDRAM_BASE 0x00000000
#define CFG_SYS_SDRAM_SIZE 0x40000000
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
"pxefile_addr_r=0x2000000\0" \
"scriptaddr=0x3000000\0" \
"kernel_addr_r=0x2000000\0" \

8
include/configs/bk4r1.h
View File

@@ -57,7 +57,7 @@
/* boot command, including the target-defined one if any */
/* Extra env settings (including the target-defined ones if any) */
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CFG_EXTRA_ENV_SETTINGS \
BK4_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
@@ -199,8 +199,8 @@
#define PHYS_SDRAM (0x80000000)
#define PHYS_SDRAM_SIZE (SZ_512M)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
#endif /* __CONFIG_H */

13
include/configs/blanche.h
View File

@@ -22,14 +22,11 @@
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
/* FLASH */
#if !defined(CONFIG_MTD_NOR_FLASH)
#define CONFIG_SH_QSPI_BASE 0xE6B10000
#else
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_FLASH_BASE 0x00000000
#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) }
#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) }
#if defined(CONFIG_MTD_NOR_FLASH)
#define CFG_SYS_FLASH_BASE 0x00000000
#define CFG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */
#define CFG_SYS_FLASH_BANKS_LIST { (CFG_SYS_FLASH_BASE) }
#define CFG_SYS_FLASH_BANKS_SIZES { (CFG_SYS_FLASH_SIZE) }
#endif
/* Board Clock */

4
include/configs/bmips_bcm3380.h
View File

@@ -9,12 +9,12 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM3380_H */

4
include/configs/bmips_bcm6318.h
View File

@@ -9,12 +9,12 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6318_H */

4
include/configs/bmips_bcm63268.h
View File

@@ -9,12 +9,12 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM63268_H */

4
include/configs/bmips_bcm6328.h
View File

@@ -9,12 +9,12 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6328_H */

6
include/configs/bmips_bcm6338.h
View File

@@ -9,14 +9,14 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6338_H */

6
include/configs/bmips_bcm6348.h
View File

@@ -9,14 +9,14 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
#define CFG_SYS_FLASH_BASE 0xbfc00000
#endif /* __CONFIG_BMIPS_BCM6348_H */

6
include/configs/bmips_bcm6358.h
View File

@@ -9,14 +9,14 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#define CONFIG_SYS_FLASH_BASE 0xbe000000
#define CFG_SYS_FLASH_BASE 0xbe000000
#endif /* __CONFIG_BMIPS_BCM6358_H */

4
include/configs/bmips_bcm6362.h
View File

@@ -9,12 +9,12 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6362_H */

6
include/configs/bmips_bcm6368.h
View File

@@ -9,14 +9,14 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#define CONFIG_SYS_FLASH_BASE 0xb8000000
#define CFG_SYS_FLASH_BASE 0xb8000000
#endif /* __CONFIG_BMIPS_BCM6368_H */

4
include/configs/bmips_bcm6838.h
View File

@@ -9,12 +9,12 @@
#include <linux/sizes.h>
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K
#define CFG_SYS_INIT_SP_OFFSET SZ_8K
#endif
#endif /* __CONFIG_BMIPS_BCM6838_H */

2
include/configs/bmips_common.h
View File

@@ -9,7 +9,7 @@
#include <linux/sizes.h>
/* UART */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 500000, 1500000 }
#endif /* __CONFIG_BMIPS_COMMON_H */

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