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synced 2026-06-13 15:03:58 +03:00
- Various minor fixes for x86 - Switch to ACPI mode on Intel edison - Support run-time configuration for NS16550 driver - Update coreboot and slimbootloader serial drivers to use NS16550 run-time configuration - ICH SPI driver fixes to hardware sequencing erase case - Move ITSS from Apollo Lake to a more generic location - Intel GPIO driver bug fixes - Move to vs2017-win2016 platform build host for Azure pipelines
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@@ -8,19 +8,6 @@
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#include <configs/x86-common.h>
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/*
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* By default, CONFIG_SYS_NS16550_PORT_MAPPED is enabled for port io serial.
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* To use mmio base serial, enable CONFIG_SYS_NS16550_MEM32 and disable
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* CONFIG_SYS_NS16550_PORT_MAPPED until ns16550 driver supports serial port
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* configuration in run-time.
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*
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* #define CONFIG_SYS_NS16550_MEM32
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* #undef CONFIG_SYS_NS16550_PORT_MAPPED
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*/
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#ifdef CONFIG_SYS_NS16550_MEM32
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#undef CONFIG_SYS_NS16550_PORT_MAPPED
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#endif
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#define CONFIG_STD_DEVICES_SETTINGS \
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"stdin=serial,i8042-kbd,usbkbd\0" \
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"stdout=serial\0" \
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@@ -31,6 +31,9 @@
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#define CONFIG_SYS_NS16550_REG_SIZE (-1)
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#endif
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#ifdef CONFIG_NS16550_DYNAMIC
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#define UART_REG(x) unsigned char x
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#else
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#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
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#error "Please define NS16550 registers size."
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#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
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@@ -44,14 +47,24 @@
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unsigned char x; \
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unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
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#endif
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#endif /* CONFIG_NS16550_DYNAMIC */
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enum ns16550_flags {
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NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */
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NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */
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NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */
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};
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/**
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* struct ns16550_platdata - information about a NS16550 port
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*
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* @base: Base register address
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* @reg_width: IO accesses size of registers (in bytes)
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* @reg_width: IO accesses size of registers (in bytes, 1 or 4)
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* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
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* @reg_offset: Offset to start of registers (normally 0)
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* @clock: UART base clock speed in Hz
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* @fcr: Offset of FCR register (normally UART_FCR_DEFVAL)
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* @flags: A few flags (enum ns16550_flags)
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* @bdf: PCI slot/function (pci_dev_t)
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*/
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struct ns16550_platdata {
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@@ -61,6 +74,7 @@ struct ns16550_platdata {
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int reg_offset;
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int clock;
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u32 fcr;
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int flags;
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#if defined(CONFIG_PCI) && defined(CONFIG_SPL)
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int bdf;
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#endif
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