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mpc83xx: Introduce ARCH_MPC834*
Replace CONFIG_MPC834* with proper CONFIG_ARCH_MPC834* Kconfig options. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
@@ -16,8 +16,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC834x 1 /* MPC834x family */
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#define CONFIG_MPC8349 1 /* MPC8349 specific */
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#define CONFIG_PCI_66M
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#ifdef CONFIG_PCI_66M
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@@ -46,9 +46,6 @@
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
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#define CONFIG_MPC8349 /* MPC8349 specific */
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#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
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#define CONFIG_MISC_INIT_F
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@@ -15,8 +15,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC834x 1 /* MPC834x specific */
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#define CONFIG_MPC8349 1 /* MPC8349 specific */
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/* IMMR Base Address Register, use Freescale default: 0xff400000 */
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#define CONFIG_SYS_IMMR 0xff400000
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@@ -18,8 +18,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC834x 1 /* MPC834x family */
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#define CONFIG_MPC8349 1 /* MPC8349 specific */
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/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
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#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
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@@ -28,8 +28,6 @@
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_MPC834x 1 /* MPC834x family */
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#define CONFIG_MPC8349 1 /* MPC8349 specific */
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#define CONFIG_VME8349 1 /* ESD VME8349 board specific */
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/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
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@@ -55,7 +55,7 @@
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#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
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#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
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#define REVID_MINOR(spridr) (spridr & 0x000000FF)
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#else
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@@ -108,7 +108,7 @@
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#define SPCR_COREPR 0x00300000
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#define SPCR_COREPR_SHIFT (31-11)
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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/* SPCR bits - MPC8349 specific */
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/* TSEC1 data priority */
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#define SPCR_TSEC1DP 0x00003000
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@@ -145,7 +145,7 @@
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/* SICRL/H - System I/O Configuration Register Low/High
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*/
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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/* SICRL bits - MPC8349 specific */
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#define SICRL_LDP_A 0x80000000
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#define SICRL_USB1 0x40000000
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@@ -720,7 +720,7 @@
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#define HRCWH_PCI_HOST_SHIFT 31
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#define HRCWH_PCI_AGENT 0x00000000
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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#define HRCWH_32_BIT_PCI 0x00000000
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#define HRCWH_64_BIT_PCI 0x40000000
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#endif
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@@ -731,7 +731,7 @@
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#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
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#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
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#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
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@@ -755,7 +755,7 @@
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#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
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#define HRCWH_ROM_LOC_PCI1 0x00100000
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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#define HRCWH_ROM_LOC_PCI2 0x00200000
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#endif
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#if defined(CONFIG_MPC837x)
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@@ -790,7 +790,7 @@
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#define HRCWH_TSEC2M_IN_SGMII 0x00001800
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#endif
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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#define HRCWH_TSEC1M_IN_RGMII 0x00000000
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#define HRCWH_TSEC1M_IN_RTBI 0x00004000
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#define HRCWH_TSEC1M_IN_GMII 0x00008000
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@@ -937,8 +937,8 @@
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#define SCCR_PCICM 0x00010000
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#define SCCR_PCICM_SHIFT 16
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#if defined(CONFIG_MPC834x)
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/* SCCR bits - MPC834x specific */
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#if defined(CONFIG_ARCH_MPC834X)
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/* SCCR bits - MPC834X specific */
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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#define SCCR_TSEC1CM_0 0x00000000
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@@ -147,7 +147,7 @@
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#if defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
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#if defined(CONFIG_MPC834x)
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#if defined(CONFIG_ARCH_MPC834X)
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#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
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#else
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#define CONFIG_SYS_FSL_USB2_ADDR 0
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