mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
powerpc: remove MBX and MBX860T boards support
Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/mbx8xx/*
- Remove include/configs/{MBX.h,MBX860T.h}
- Clean-up if defined(CONFIG_MBX)
- Move the entries from boards.cfg to doc/README.scrapyard
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
committed by
Tom Rini
Tom Rini
parent
a146e8b189
commit
d6b11fd1f0
@@ -511,13 +511,6 @@ void rpxclassic_init (void);
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void rpxlite_init (void);
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#ifdef CONFIG_MBX
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/* $(BOARD)/mbx8xx.c */
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void mbx_init (void);
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void board_serial_init (void);
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void board_ether_init (void);
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#endif
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#ifdef CONFIG_HERMES
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/* $(BOARD)/hermes.c */
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void hermes_start_lxt980 (int speed);
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@@ -12,10 +12,6 @@
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* CPM capabilities. I (or someone else) will add definitions as they
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* are needed. -- Dan
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*
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* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
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* bytes of the DP RAM and relocates the I2C parameter area to the
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* IDMA1 space. The remaining DP RAM is available for buffer descriptors
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* or other use.
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*/
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#ifndef __CPM_8XX__
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#define __CPM_8XX__
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@@ -135,7 +131,6 @@ typedef struct cpm_buf_desc {
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#define PROFF_SMC2 ((uint)0x0380)
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/* Define enough so I can at least use the serial port as a UART.
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* The MBX uses SMC1 as the host serial port.
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*/
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typedef struct smc_uart {
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ushort smc_rbase; /* Rx Buffer descriptor base address */
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@@ -888,33 +883,6 @@ typedef struct scc_enet {
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#define SICR_ENET_CLKRT ((uint)0x00003E00)
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#endif /* CONFIG_LWMON */
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/*** MBX ************************************************************/
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#ifdef CONFIG_MBX
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/* Bits in parallel I/O port registers that have to be set/cleared
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* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
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* to the MBX860 board. Any two of the four available clocks could be
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* used, and the MPC860 cookbook manual has an example using different
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* clock pins.
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*/
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#define PROFF_ENET PROFF_SCC1
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#define CPM_CR_ENET CPM_CR_CH_SCC1
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#define SCC_ENET 0
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#define PA_ENET_RXD ((ushort)0x0001)
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#define PA_ENET_TXD ((ushort)0x0002)
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#define PA_ENET_TCLK ((ushort)0x0200)
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#define PA_ENET_RCLK ((ushort)0x0800)
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#define PC_ENET_TENA ((ushort)0x0001)
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#define PC_ENET_CLSN ((ushort)0x0010)
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#define PC_ENET_RENA ((ushort)0x0020)
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/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
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* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
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*/
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#define SICR_ENET_MASK ((uint)0x000000ff)
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#define SICR_ENET_CLKRT ((uint)0x0000003d)
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#endif /* CONFIG_MBX */
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/*** KM8XX *********************************************************/
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/* The KM8XX Service Module uses SCC3 for Ethernet */
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@@ -1,290 +0,0 @@
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/*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Configuation settings for the MBX8xx board.
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*
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* -----------------------------------------------------------------
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Changed 2002-10-01
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* Added PCMCIA defines mostly taken from other U-Boot boards that
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* have PCMCIA already working. If you find any bugs, incorrect assumptions
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* feel free to fix them yourself and submit a patch.
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* Rod Boyce <rod_boyce@stratexnet.com.
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
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#define CONFIG_MBX 1 /* ...on an MBX module */
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#define CONFIG_SYS_TEXT_BASE 0xfe000000
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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/* Define this to use the PCI bus */
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#undef CONFIG_USE_PCI
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#define CONFIG_8xx_GCLK_FREQ (50000000UL)
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#if 1
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
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#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
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"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
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"nfsaddrs=10.0.0.99:10.0.0.2"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_PCMCIA
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#define CONFIG_CMD_IDE
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#define CONFIG_DOS_PARTITION
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Physical memory map as defined by the MBX PGM
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*/
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#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
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#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */
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#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
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#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */
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#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
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#define CONFIG_SYS_PCIMEM_OR 0xA0000108
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#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
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#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
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#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
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/*-----------------------------------------------------------------------
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* Offset in DPMEM where we keep the VPD data
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*/
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#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xfe000000
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#ifdef DEBUG
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#else
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#endif
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#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* NVRAM Configuration
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*
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* Note: the MBX is special because there is already a firmware on this
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* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
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* access the NVRAM at the offset 0x1000.
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*/
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000)
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#define CONFIG_ENV_SIZE 0x1000
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit - leave PLL multiplication factor unchanged !
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*/
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#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
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#define CONFIG_SYS_SCCR SCCR_TBS
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/*-----------------------------------------------------------------------
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* PCMCIA stuff
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
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#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
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#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
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#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
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#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
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#define CONFIG_PCMCIA_SLOT_A 1
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/*-----------------------------------------------------------------------
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* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
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#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
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/*-----------------------------------------------------------------------
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* Debug Entry Mode
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_DER 0
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#endif /* __CONFIG_H */
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@@ -1,395 +0,0 @@
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/*
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T MBX board.
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* Copied from the FADS stuff, which was originally copied from the MBX stuff!
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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* Rob Taylor coverted it back to MBX
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_MBX 1
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#define CONFIG_SYS_TEXT_BASE 0xfe000000
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#define CONFIG_8xx_CPUCLOCK 40
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#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK)
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#define TARGET_SYSTEM_FREQUENCY 40
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#define CONFIG_BAUDRATE 9600
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#define MPC8XX_FACT 10 /* Multiply by 10 */
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#define MPC8XX_XIN 40000000 /* 50 MHz in */
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#if 1
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#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */
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#define CONFIG_8xx_TFTP_MODE
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#else
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#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_8xx_TFTP_MODE
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#endif
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#define CONFIG_MISC_INIT_R
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#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */
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#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
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#define CONFIG_BOOTARGS " "
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/*
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* Miscellaneous configurable options
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*/
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#undef CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFFA00000
|
||||
#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
|
||||
#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */
|
||||
#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
|
||||
#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */
|
||||
#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
|
||||
#define CONFIG_SYS_PCIMEM_OR 0xA0000108
|
||||
#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
|
||||
#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
|
||||
#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Offset in DPMEM where we keep the VPD data
|
||||
*/
|
||||
#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
||||
/*0xFE000000*/
|
||||
#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_HWINFO_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_SYS_HWINFO_LEN)
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM Configuration
|
||||
*
|
||||
* Note: the MBX is special because there is already a firmware on this
|
||||
* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
|
||||
* access the NVRAM at the offset 0x1000.
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit - leave PLL multiplication factor unchanged !
|
||||
*/
|
||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
|
||||
#define CONFIG_SYS_SCCR SCCR_TBS
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/* Because of the way the 860 starts up and assigns CS0 the
|
||||
* entire address space, we have to set the memory controller
|
||||
* differently. Normally, you write the option register
|
||||
* first, and then enable the chip select by writing the
|
||||
* base register. For CS0, you must write the base register
|
||||
* first, followed by the option register.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
/* the other CS:s are determined by looking at parameters in BCSRx */
|
||||
|
||||
|
||||
#define BCSR_ADDR ((uint) 0xFF010000)
|
||||
#define BCSR_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */
|
||||
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
|
||||
#define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_V )
|
||||
|
||||
/* BCSRx - Board Control and Status Registers */
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4
|
||||
#define CONFIG_SYS_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V )
|
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
#define CONFIG_SYS_MAMR 0x13821000
|
||||
|
||||
/* values according to the manual */
|
||||
|
||||
|
||||
#define PCMCIA_MEM_ADDR ((uint)0xff020000)
|
||||
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
|
||||
|
||||
#define BCSR0 ((uint) (BCSR_ADDR + 00))
|
||||
#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
|
||||
#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
|
||||
#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
|
||||
#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
|
||||
|
||||
/* FADS bitvalues by Helmut Buchsbaum
|
||||
* see MPC8xxADS User's Manual for a proper description
|
||||
* of the following structures
|
||||
*/
|
||||
|
||||
#define BCSR0_ERB ((uint)0x80000000)
|
||||
#define BCSR0_IP ((uint)0x40000000)
|
||||
#define BCSR0_BDIS ((uint)0x10000000)
|
||||
#define BCSR0_BPS_MASK ((uint)0x0C000000)
|
||||
#define BCSR0_ISB_MASK ((uint)0x01800000)
|
||||
#define BCSR0_DBGC_MASK ((uint)0x00600000)
|
||||
#define BCSR0_DBPC_MASK ((uint)0x00180000)
|
||||
#define BCSR0_EBDF_MASK ((uint)0x00060000)
|
||||
|
||||
#define BCSR1_FLASH_EN ((uint)0x80000000)
|
||||
#define BCSR1_DRAM_EN ((uint)0x40000000)
|
||||
#define BCSR1_ETHEN ((uint)0x20000000)
|
||||
#define BCSR1_IRDEN ((uint)0x10000000)
|
||||
#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
|
||||
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
|
||||
#define BCSR1_BCSR_EN ((uint)0x02000000)
|
||||
#define BCSR1_RS232EN_1 ((uint)0x01000000)
|
||||
#define BCSR1_PCCEN ((uint)0x00800000)
|
||||
#define BCSR1_PCCVCC0 ((uint)0x00400000)
|
||||
#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
|
||||
#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
|
||||
#define BCSR1_RS232EN_2 ((uint)0x00040000)
|
||||
#define BCSR1_SDRAM_EN ((uint)0x00020000)
|
||||
#define BCSR1_PCCVCC1 ((uint)0x00010000)
|
||||
|
||||
#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
|
||||
#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
|
||||
#define BCSR2_DRAM_PD_SHIFT (23)
|
||||
#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
|
||||
#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
|
||||
|
||||
#define BCSR3_DBID_MASK ((ushort)0x3800)
|
||||
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
|
||||
#define BCSR3_BREVNR0 ((ushort)0x0080)
|
||||
#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
|
||||
#define BCSR3_BREVN1 ((ushort)0x0008)
|
||||
#define BCSR3_BREVN2_MASK ((ushort)0x0003)
|
||||
|
||||
#define BCSR4_ETHLOOP ((uint)0x80000000)
|
||||
#define BCSR4_TFPLDL ((uint)0x40000000)
|
||||
#define BCSR4_TPSQEL ((uint)0x20000000)
|
||||
#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
|
||||
#ifdef CONFIG_MPC823
|
||||
#define BCSR4_USB_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC823 */
|
||||
#ifdef CONFIG_MPC860SAR
|
||||
#define BCSR4_UTOPIA_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC860SAR */
|
||||
#ifdef CONFIG_MPC860T
|
||||
#define BCSR4_FETH_EN ((uint)0x08000000)
|
||||
#endif /* CONFIG_MPC860T */
|
||||
#define BCSR4_USB_SPEED ((uint)0x04000000)
|
||||
#define BCSR4_VCCO ((uint)0x02000000)
|
||||
#define BCSR4_VIDEO_ON ((uint)0x00800000)
|
||||
#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
|
||||
#define BCSR4_VIDEO_RST ((uint)0x00200000)
|
||||
#define BCSR4_MODEM_EN ((uint)0x00100000)
|
||||
#define BCSR4_DATA_VOICE ((uint)0x00080000)
|
||||
|
||||
#define CONFIG_DRAM_40MHZ 1
|
||||
|
||||
#ifdef CONFIG_MPC860T
|
||||
|
||||
/* Interrupt level assignments.
|
||||
*/
|
||||
#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
|
||||
|
||||
#endif /* CONFIG_MPC860T */
|
||||
|
||||
/* We don't use the 8259.
|
||||
*/
|
||||
#define NR_8259_INTS 0
|
||||
|
||||
#define CONFIG_CMD_NET
|
||||
/*
|
||||
* MPC8xx CPM Options
|
||||
*/
|
||||
#define CONFIG_SCC_ENET 1
|
||||
#define CONFIG_SCC1_ENET 1
|
||||
#define CONFIG_FEC_ENET 1
|
||||
#undef CONFIG_CPM_IIC
|
||||
#undef CONFIG_UCODE_PATCH
|
||||
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
|
||||
|
||||
/* PCMCIA configuration */
|
||||
|
||||
#define PCMCIA_MAX_SLOTS 2
|
||||
|
||||
#ifdef CONFIG_MPC860
|
||||
#define PCMCIA_SLOT_A 1
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user