mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-02 09:46:37 +03:00
arm64: dts: renesas: Switch to upstream DT on Renesas R-Car X5H R8A78000
Enable OF_UPSTREAM to use upstream Linux kernel DT source as a base for U-Boot control DT. Retain currently present parts of the DT which are not yet part of upstream Linux kernel DT in -u-boot.dtsi files until they get replaced by upstream equivalents. Add renesas/ prefix to the DEFAULT_DEVICE_TREE as part of the switch. Unused i2c2..i2c8 nodes have been removed, and will become available once upstream Linux kernel DT adds those nodes. The DRAM_RSV_SIZE has been updated to cover first 518 MiB of DRAM, which are reserved for firmware and other use. Note that all DT parts in -u-boot.dtsi are not considered stable DT bindings and may change before they land in Linux kernel and become stable DT ABI. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
@@ -899,13 +899,6 @@ dtb-$(CONFIG_RZA1) += \
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r7s72100-genmai.dtb \
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r7s72100-gr-peach.dtb
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dtb-$(CONFIG_RCAR_GEN5) += \
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r8a78000-ironhide.dtb
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ifdef CONFIG_RCAR_GEN5
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DTC_FLAGS += -R 4 -p 0x1000
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endif
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dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
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dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
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@@ -5,4 +5,178 @@
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#include <dt-bindings/net/ti-dp83869.h>
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#include "r8a78000-u-boot.dtsi"
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/ {
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &mmc0;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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ð_pcs {
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phys = <&mp_phy 2 1>;
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status = "okay";
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-0 = <&mmc0_pins>;
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pinctrl-1 = <&mmc0_pins>;
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pinctrl-names = "default", "state_uhs";
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bus-width = <8>;
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full-pwr-cycle-in-suspend;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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status = "okay";
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};
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&mp_phy {
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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eth25g2_pins: eth25g2 {
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groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
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function = "eth25g2";
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drive-strength = <24>;
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};
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ethes0_pins: ethes0 {
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groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
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function = "ethes0";
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drive-strength = <24>;
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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mmc0_pins: mmc0 {
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groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
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function = "mmc0";
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drive-strength = <24>;
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};
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rsw3_pins: rsw3 {
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groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
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function = "rsw3";
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drive-strength = <24>;
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};
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scif_clk_pins: scif-clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&rswitch3 {
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pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>;
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pinctrl-names = "default";
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status = "okay";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* NOTE: Only port@4 is configured for R-Car X5H board.
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* Other ports (0-3, 5-12) are currently unused or not
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* connected.
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*/
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port@4 {
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reg = <4>;
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renesas,connect_to_xpcs;
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phy-handle = <&dp83869_phy>;
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phy-mode = "sgmii";
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phys = <ð_pcs 5>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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dp83869_phy: ethernet-phy@2 {
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reg = <2>;
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ti,sgmii-interface;
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ti,max-output-impedance;
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ti,refclk-output-enable;
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ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
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};
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};
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};
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};
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};
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&ufs0 {
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status = "okay";
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};
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&ufs1 {
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status = "okay";
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};
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@@ -1,257 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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/*
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* Device Tree Source for the Ironhide board
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a78000.dtsi"
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#include <dt-bindings/net/ti-dp83869.h>
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/ {
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model = "Renesas Ironhide board based on r8a78000";
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compatible = "renesas,ironhide", "renesas,r8a78000";
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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mmc0 = &mmc0;
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serial0 = &hscif0;
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};
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chosen {
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stdout-path = "serial0:1843200n8";
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0x0 0x80000000>;
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};
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memory@1080000000 {
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device_type = "memory";
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reg = <0x10 0x80000000 0x0 0x80000000>;
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};
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memory@1200000000 {
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device_type = "memory";
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reg = <0x12 0x00000000 0x1 0x00000000>;
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};
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memory@1400000000 {
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device_type = "memory";
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reg = <0x14 0x00000000 0x1 0x00000000>;
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};
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memory@1600000000 {
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device_type = "memory";
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reg = <0x16 0x00000000 0x1 0x00000000>;
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};
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memory@1800000000 {
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device_type = "memory";
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reg = <0x18 0x00000000 0x1 0x00000000>;
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};
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memory@1a00000000 {
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device_type = "memory";
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reg = <0x1a 0x00000000 0x1 0x00000000>;
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};
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memory@1c00000000 {
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device_type = "memory";
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reg = <0x1c 0x00000000 0x1 0x00000000>;
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};
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memory@1e00000000 {
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device_type = "memory";
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reg = <0x1e 0x00000000 0x1 0x00000000>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&extal_clk {
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clock-frequency = <16666600>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&hscif0 {
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pinctrl-0 = <&hscif0_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&i2c0 {
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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eeprom@50 {
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compatible = "rohm,br24g01", "atmel,24c01";
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reg = <0x50>;
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pagesize = <8>;
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};
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};
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&i2c1 {
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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status = "okay";
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};
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ð_pcs {
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phys = <&mp_phy 2 1>;
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status = "okay";
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};
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&mmc0 {
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pinctrl-0 = <&mmc0_pins>;
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pinctrl-1 = <&mmc0_pins>;
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pinctrl-names = "default", "state_uhs";
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bus-width = <8>;
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full-pwr-cycle-in-suspend;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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no-sd;
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no-sdio;
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non-removable;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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status = "okay";
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};
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&ufs0 {
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status = "okay";
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};
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&ufs1 {
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status = "okay";
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};
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&mp_phy {
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status = "okay";
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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eth25g2_pins: eth25g2 {
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groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
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function = "eth25g2";
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drive-strength = <24>;
|
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};
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ethes0_pins: ethes0 {
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groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
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function = "ethes0";
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drive-strength = <24>;
|
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};
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hscif0_pins: hscif0 {
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groups = "hscif0_data", "hscif0_ctrl";
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function = "hscif0";
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};
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i2c0_pins: i2c0 {
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groups = "i2c0";
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function = "i2c0";
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};
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i2c1_pins: i2c1 {
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groups = "i2c1";
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function = "i2c1";
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};
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mmc0_pins: mmc0 {
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groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
|
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function = "mmc0";
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drive-strength = <24>;
|
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};
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rsw3_pins: rsw3 {
|
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groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
|
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function = "rsw3";
|
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drive-strength = <24>;
|
||||
};
|
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|
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scif_clk_pins: scif-clk {
|
||||
groups = "scif_clk";
|
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function = "scif_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&rswitch3 {
|
||||
pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* NOTE: Only port@4 is configured for R-Car X5H board.
|
||||
* Other ports (0-3, 5-12) are currently unused or not
|
||||
* connected.
|
||||
*/
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
renesas,connect_to_xpcs;
|
||||
phy-handle = <&dp83869_phy>;
|
||||
phy-mode = "sgmii";
|
||||
phys = <ð_pcs 5>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dp83869_phy: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
ti,sgmii-interface;
|
||||
ti,max-output-impedance;
|
||||
ti,refclk-output-enable;
|
||||
ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&scif_clk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
@@ -5,9 +5,41 @@
|
||||
* Copyright (C) 2025 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/r8a78000-clock-scmi.h>
|
||||
#include <dt-bindings/power/r8a78000-power-scmi.h>
|
||||
#include <dt-bindings/reset/r8a78000-reset-scmi.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
bootph-all;
|
||||
firmware {
|
||||
scmi {
|
||||
compatible = "arm,scmi";
|
||||
arm,poll-transport;
|
||||
mbox-names = "tx", "rx";
|
||||
mboxes = <&mailbox 0>, <&mailbox 1>;
|
||||
shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_devpd: protocol@11 {
|
||||
reg = <0x11>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_reset: protocol@16 {
|
||||
reg = <0x16>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* Placeholder clock until the clock provider is in place */
|
||||
@@ -38,10 +70,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&cpg {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
bootph-all;
|
||||
};
|
||||
@@ -50,90 +78,297 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio6 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio8 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio9 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&gpio10 {
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clocks = <&clk_stub_i2c0>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&i2c8 {
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
clocks = <&clk_stub_mmc>;
|
||||
};
|
||||
|
||||
&prr {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&soc {
|
||||
bootph-all;
|
||||
|
||||
mailbox: mfis_mbox@18842000 {
|
||||
compatible = "renesas,mfis-mbox";
|
||||
#mbox-cells = <1>;
|
||||
reg = <0 0x18842004 0 0x8>;
|
||||
interrupts = <GIC_SPI 4362 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pfc: pinctrl@c0400000 {
|
||||
compatible = "renesas,pfc-r8a78000";
|
||||
reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>,
|
||||
<0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>,
|
||||
<0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>,
|
||||
<0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>,
|
||||
<0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>,
|
||||
<0 0xc9b00800 0 0x104>;
|
||||
};
|
||||
|
||||
mmc0: mmc@c0880000 {
|
||||
compatible = "renesas,rcar-gen5-sdhi";
|
||||
reg = <0 0xc0880000 0 0x2000>;
|
||||
clock-names = "core";
|
||||
max-frequency = <200000000>;
|
||||
clocks = <&clk_stub_mmc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs0: ufs@c0a80000 {
|
||||
compatible = "renesas,r8a78000-ufs";
|
||||
reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>;
|
||||
reg-names = "hcr", "phy";
|
||||
interrupts = <GIC_SPI 4284 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>;
|
||||
clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>;
|
||||
resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>;
|
||||
freq-table-hz = <38400000 38400000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ufs1: ufs@c0a90000 {
|
||||
compatible = "renesas,r8a78000-ufs";
|
||||
reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>;
|
||||
reg-names = "hcr", "phy";
|
||||
interrupts = <GIC_SPI 4285 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>;
|
||||
clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>;
|
||||
resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>;
|
||||
freq-table-hz = <38400000 38400000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scp: sram@c1000000 {
|
||||
compatible = "arm,rcar-sram-ns", "mmio-sram";
|
||||
reg = <0x0 0xc1000000 0x0 0x80000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0xc1000000 0x80000>;
|
||||
|
||||
cpu_scp_lpri0: scp-shmem@60000 {
|
||||
compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
|
||||
reg = <0x61200 0x0100>;
|
||||
};
|
||||
|
||||
cpu_scp_hpri0: scp-shmem@60300 {
|
||||
compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem";
|
||||
reg = <0x61300 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
cpg: clock-controller@c64f0000 {
|
||||
compatible = "renesas,r8a78000-cpg-mssr";
|
||||
reg = <0 0xc64f0000 0 0x4000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
i2c0: i2c@c11d0000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc11d0000 0 0x40>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk_stub_i2c0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@c06c0000 {
|
||||
compatible = "renesas,i2c-r8a78000",
|
||||
"renesas,rcar-gen5-i2c";
|
||||
reg = <0 0xc06c0000 0 0x40>;
|
||||
i2c-scl-internal-delay-ns = <110>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clk_stub_i2c1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@c1080110 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc1080110 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 0 28>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio1: gpio@c1080910 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc1080910 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 32 22>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio2: gpio@c1081110 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc1081110 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 64 29>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio3: gpio@c0800110 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc0800110 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 96 17>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio4: gpio@c0800910 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc0800910 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 128 16>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio5: gpio@c0400110 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc0400110 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 160 23>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio6: gpio@c0400910 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc0400910 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 192 31>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio7: gpio@c0401110 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc0401110 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 224 31>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio8: gpio@c0401910 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc0401910 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 256 32>;
|
||||
gpio-reserved-ranges = <16 10>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio9: gpio@c9b00110 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc9b00110 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 288 17>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
gpio10: gpio@c9b00910 {
|
||||
compatible = "renesas,gpio-r8a78000",
|
||||
"renesas,rcar-gen5-gpio";
|
||||
reg = <0 0xc9b00910 0 0xc0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pfc 0 320 14>;
|
||||
clocks = <&clk_stub_gpio>;
|
||||
};
|
||||
|
||||
mp_phy: mp_phy@c9a00000 {
|
||||
compatible = "renesas,r8a78000-multi-protocol-phy";
|
||||
reg = <0 0xc9a00000 0 0x100000>;
|
||||
#phy-cells = <2>;
|
||||
clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>;
|
||||
clock-names = "mpphy01", "mpphy11", "mpphy21",
|
||||
"mpphy31", "mpphy02";
|
||||
power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>,
|
||||
<&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>,
|
||||
<&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>,
|
||||
<&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>;
|
||||
resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rswitch3: ethernet@c9bc0000 {
|
||||
compatible = "renesas,r8a78000-ether-switch3",
|
||||
"renesas,etherswitch";
|
||||
reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>;
|
||||
reg-names = "base", "secure_base";
|
||||
power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>;
|
||||
clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>;
|
||||
clock-names = "rsw3", "rsw3tsn", "rsw3aes",
|
||||
"rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2",
|
||||
"rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5",
|
||||
"rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth_pcs: phy@c9c50000 {
|
||||
compatible = "renesas,r8a78000-ether-pcs";
|
||||
reg = <0 0xc9c50000 0 0x4000>;
|
||||
#phy-cells = <1>;
|
||||
clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>,
|
||||
<&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>;
|
||||
clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
|
||||
"xpcs4", "xpcs5", "xpcs6", "xpcs7";
|
||||
resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>,
|
||||
<&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>;
|
||||
reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3",
|
||||
"xpcs4", "xpcs5", "xpcs6", "xpcs7";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -5,12 +5,11 @@ CONFIG_ARCH_RENESAS=y
|
||||
CONFIG_RCAR_GEN5=y
|
||||
CONFIG_TARGET_IRONHIDE=y
|
||||
|
||||
# CONFIG_OF_UPSTREAM is not set
|
||||
CONFIG_ARMV8_PSCI=y
|
||||
CONFIG_ARM_SMCCC=y
|
||||
CONFIG_BAUDRATE=1843200
|
||||
CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a78000-ironhide"
|
||||
CONFIG_CLK_CCF=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_SCMI=y
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 }
|
||||
|
||||
/* Memory */
|
||||
#define DRAM_RSV_SIZE 0x08000000
|
||||
#define DRAM_RSV_SIZE 0x20600000
|
||||
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
|
||||
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
|
||||
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
|
||||
|
||||
Reference in New Issue
Block a user