From b717a4090fb0fda4814bbc9d9a91396710294cfb Mon Sep 17 00:00:00 2001
From: John Ripple <john.ripple@keysight.com>
Date: Tue, 9 Sep 2025 13:53:22 -0600
Subject: [PATCH 01/15] imx8: Add ahab_commit command

The ahab_commit command allows the user to commit into the SECO fuses
that control the SRK key revocation information. This is used to Revoke
compromised SRK keys.

To use ahab_commit, the boot container must be built with an SRK
revocation bit mask that is not 0x0. For the SPSDK provided by NXP, this
means setting the 'srk_revoke_mask' option in the config file used to
sign the boot container. The 'ahab_commit 0x10' can then be used to commit
the SRK revocation information into the SECO fuses.

Signed-off-by: John Ripple <john.ripple@keysight.com>
---
 arch/arm/mach-imx/imx8/ahab.c  | 29 +++++++++++++++++++++++++++++
 drivers/misc/imx8/scu_api.c    | 31 +++++++++++++++++++++++++++++++
 include/firmware/imx/sci/sci.h |  6 ++++++
 3 files changed, 66 insertions(+)

diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 324e010bb2c..f13baa871cc 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -401,6 +401,29 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 	return 0;
 }
 
+static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	u32 info;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	info = simple_strtoul(argv[1], NULL, 16);
+	printf("Commit index is 0x%x\n", info);
+
+	ret = sc_seco_commit(-1, &info);
+	if (ret) {
+		printf("Error in AHAB commit\n");
+		return ret;
+	}
+
+	printf("AHAB commit succeeded.\n");
+
+	return CMD_RET_SUCCESS;
+}
+
 U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
 	   "autenticate OS container via AHAB",
 	   "addr\n"
@@ -416,3 +439,9 @@ U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
 	   "Change AHAB lifecycle to OEM closed",
 	   ""
 );
+
+U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit,
+	   "commit into the fuses any new SRK revocation information that have been found\n"
+	   "into the NXP (SECO FW) and OEM containers. For SRK revocation use 0x10 for the value.",
+	   ""
+);
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 8985ab6584d..d9cc7acb970 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -1286,3 +1286,34 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data)
 
 	return ret;
 }
+
+int sc_seco_commit(sc_ipc_t ipc, u32 *info)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	/* Fill in header */
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 2U;
+	RPC_SVC(&msg) = (u8)SC_RPC_SVC_SECO;
+	RPC_FUNC(&msg) = (u8)SECO_FUNC_COMMIT;
+
+	/* Fill in send message */
+	RPC_U32(&msg, 0U) = *info;
+
+	/* Call RPC */
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		return ret;
+
+	/* Copy out result */
+	ret = (int)RPC_R8(&msg);
+
+	/* Copy out receive message */
+	if (!ret)
+		*info = RPC_U32(&msg, 0U);
+
+	return ret;
+}
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h
index 588f3671103..876d52cac35 100644
--- a/include/firmware/imx/sci/sci.h
+++ b/include/firmware/imx/sci/sci.h
@@ -144,6 +144,7 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
 int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
 			  u32 *data0, u32 *data1, u32 *data2, u32 *data3,
 			  u32 *data4, u8 size);
+int sc_seco_commit(sc_ipc_t ipc, u32 *info);
 #else
 /* PM API*/
 static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
@@ -383,6 +384,11 @@ static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *dat
 	return -EOPNOTSUPP;
 }
 
+static inline int sc_seco_commit(sc_ipc_t ipc, u32 *info)
+{
+	return -EOPNOTSUPP;
+}
+
 static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
 {
 }

From 00ef795981d0c2df52e7fdd91d57a924b941dbfb Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:04 +0800
Subject: [PATCH 02/15] pci: dw: Fix wrong register used for PCI_COMMAND

Wirting to command register should use PCI_COMMAND not PCI_PRIMARY_BUS

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 drivers/pci/pcie_dw_common.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index c4cad019373..4113a9f03cf 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -7,7 +7,6 @@
  *
  * Copyright (C) 2018 Texas Instruments, Inc
  */
-
 #include <dm.h>
 #include <log.h>
 #include <pci.h>
@@ -385,7 +384,7 @@ void pcie_dw_setup_host(struct pcie_dw *pci)
 			0xffffff, 0x00ff0100);
 
 	/* setup command register */
-	clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
+	clrsetbits_le32(pci->dbi_base + PCI_COMMAND,
 			0xffff,
 			PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 			PCI_COMMAND_MASTER | PCI_COMMAND_SERR);

From f8b188350815df2e0436eb113e7c9300ca9cd02e Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:05 +0800
Subject: [PATCH 03/15] pci: pcie_dw_imx: Add iMX9 support to the driver

Adding iMX95/iMX94 support to the dw driver. Follow kernel driver
stype to use flags to distinguish the characteristic of different
platforms.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 drivers/pci/Kconfig       |   2 +-
 drivers/pci/pcie_dw_imx.c | 420 ++++++++++++++++++++++++++++++++++----
 2 files changed, 377 insertions(+), 45 deletions(-)

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b8568267ff8..6c2cda1a966 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -461,7 +461,7 @@ config PCIE_STARFIVE_JH7110
 
 config PCIE_DW_IMX
 	bool "i.MX DW PCIe controller support"
-	depends on ARCH_IMX8M
+	depends on ARCH_IMX8M || ARCH_IMX9
 	select PCIE_DW_COMMON
 	select DM_REGULATOR
 	select REGMAP
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
index fdb463710ba..f84c7180560 100644
--- a/drivers/pci/pcie_dw_imx.c
+++ b/drivers/pci/pcie_dw_imx.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2024 Linaro Ltd.
+ * Copyright 2025 NXP
  *
  * Author: Sumit Garg <sumit.garg@linaro.org>
  */
@@ -45,6 +46,47 @@
 #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN	BIT(10)
 #define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE		BIT(11)
 
+#define IMX95_PCIE_PHY_GEN_CTRL			0x0
+#define IMX95_PCIE_REF_USE_PAD			BIT(17)
+
+#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
+#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
+
+#define IMX95_PCIE_SS_RW_REG_0			0xf0
+#define IMX95_PCIE_REF_CLKEN			BIT(23)
+#define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
+#define IMX95_PCIE_SS_RW_REG_1			0xf4
+#define IMX95_PCIE_CLKREQ_OVERRIDE_EN		BIT(8)
+#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL		BIT(9)
+#define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)
+
+#define IMX95_PE0_GEN_CTRL_1			0x1050
+#define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
+
+#define IMX95_PE0_GEN_CTRL_3			0x1058
+#define IMX95_PCIE_LTSSM_EN			BIT(0)
+
+#define IMX95_PCIE_RST_CTRL			0x3010
+#define IMX95_PCIE_COLD_RST			BIT(0)
+
+#define GEN3_RELATED_OFF			0x890
+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL	BIT(0)
+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS	BIT(13)
+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE	BIT(16)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT	24
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK	GENMASK(25, 24)
+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT	0x1
+
+#define IMX_PCIE_FLAG_HAS_PHYDRV        BIT(3)
+#define IMX_PCIE_FLAG_HAS_APP_RESET     BIT(4)
+#define IMX_PCIE_FLAG_HAS_SERDES        BIT(6)
+
+#define IMX_PCIE_MAX_INSTANCES	2
+
+/* Parameters for the waiting for PCIe PHY PLL to lock s*/
+#define PHY_PLL_LOCK_WAIT_USLEEP_MAX	200
+#define PHY_PLL_LOCK_WAIT_TIMEOUT	(2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX / 1000)
+
 struct pcie_dw_imx {
 	/* Must be first member of the struct */
 	struct pcie_dw			dw;
@@ -54,20 +96,203 @@ struct pcie_dw_imx {
 	struct reset_ctl		apps_reset;
 	struct phy			phy;
 	struct udevice			*vpcie;
+	void				*info;
+	u32				max_link_speed;
+	bool				enable_ext_refclk;
+	bool				supports_clkreq;
 };
 
 struct pcie_chip_info {
+	u32 flags;
+	const u32 ltssm_off;
+	const u32 ltssm_mask;
+	const u32 mode_off[IMX_PCIE_MAX_INSTANCES];
+	const u32 mode_mask[IMX_PCIE_MAX_INSTANCES];
 	const char *gpr;
+	void (*init_phy)(struct pcie_dw_imx *priv);
+	int (*enable_ref_clk)(struct pcie_dw_imx *priv, bool enable);
+	int (*core_reset)(struct pcie_dw_imx *priv, bool assert);
+	int (*wait_pll_lock)(struct pcie_dw_imx *priv);
+	void (*post_config)(struct pcie_dw_imx *priv);
 };
 
+static void imx95_pcie_init_phy(struct pcie_dw_imx *priv)
+{
+/*
+ * Workaround for ERR051624: The Controller Without Vaux Cannot
+ * Exit L23 Ready Through Beacon or PERST# De-assertion
+ *
+ * When the auxiliary power is not available the controller
+ * cannot exit from L23 Ready with beacon or PERST# de-assertion
+ * when main power is not removed.
+ *
+ * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.
+ */
+	regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,
+		IMX95_PCIE_SYS_AUX_PWR_DET, IMX95_PCIE_SYS_AUX_PWR_DET);
+
+	regmap_update_bits(priv->iomuxc_gpr,
+		IMX95_PCIE_SS_RW_REG_0,
+		IMX95_PCIE_PHY_CR_PARA_SEL,
+		IMX95_PCIE_PHY_CR_PARA_SEL);
+
+	if (priv->enable_ext_refclk) {
+		/* External clock is used as reference clock */
+		regmap_update_bits(priv->iomuxc_gpr,
+			IMX95_PCIE_PHY_GEN_CTRL,
+			IMX95_PCIE_REF_USE_PAD,
+			IMX95_PCIE_REF_USE_PAD);
+		regmap_update_bits(priv->iomuxc_gpr,
+			IMX95_PCIE_SS_RW_REG_0,
+			IMX95_PCIE_REF_CLKEN, 0);
+	} else {
+		regmap_update_bits(priv->iomuxc_gpr,
+			IMX95_PCIE_PHY_GEN_CTRL,
+			IMX95_PCIE_REF_USE_PAD, 0);
+
+		regmap_update_bits(priv->iomuxc_gpr,
+			IMX95_PCIE_SS_RW_REG_0,
+			IMX95_PCIE_REF_CLKEN,
+			IMX95_PCIE_REF_CLKEN);
+	}
+
+	/* Force CLKREQ# low by override */
+	if (!priv->supports_clkreq)
+		regmap_update_bits(priv->iomuxc_gpr,
+				   IMX95_PCIE_SS_RW_REG_1,
+				   IMX95_PCIE_CLKREQ_OVERRIDE_EN |
+				   IMX95_PCIE_CLKREQ_OVERRIDE_VAL,
+				   IMX95_PCIE_CLKREQ_OVERRIDE_EN |
+				   IMX95_PCIE_CLKREQ_OVERRIDE_VAL);
+}
+
+static int imx95_pcie_wait_for_phy_pll_lock(struct pcie_dw_imx *priv)
+{
+	u32 val;
+
+	if (regmap_read_poll_timeout(priv->iomuxc_gpr,
+				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
+				     val & IMX95_PCIE_PHY_MPLL_STATE,
+				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
+				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
+		printf("PCIe PLL lock timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int imx95_pcie_core_reset(struct pcie_dw_imx *priv, bool assert)
+{
+	u32 val;
+
+	if (assert) {
+		/*
+		 * From i.MX95 PCIe PHY perspective, the COLD reset toggle
+		 * should be complete after power-up by the following sequence.
+		 *                 > 10us(at power-up)
+		 *                 > 10ns(warm reset)
+		 *               |<------------>|
+		 *                ______________
+		 * phy_reset ____/              \________________
+		 *                                   ____________
+		 * ref_clk_en_______________________/
+		 * Toggle COLD reset aligned with this sequence for i.MX95 PCIe.
+		 */
+		regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				   IMX95_PCIE_COLD_RST, IMX95_PCIE_COLD_RST);
+		/*
+		 * Make sure the write to IMX95_PCIE_RST_CTRL is flushed to the
+		 * hardware by doing a read. Otherwise, there is no guarantee
+		 * that the write has reached the hardware before udelay().
+		 */
+		regmap_read(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				     &val);
+		udelay(15);
+		regmap_update_bits(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				  IMX95_PCIE_COLD_RST, 0);
+		regmap_read(priv->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
+				     &val);
+		udelay(10);
+	}
+
+	return 0;
+}
+
+static void imx95_pcie_post_config(struct pcie_dw_imx *priv)
+{
+	u32 val;
+
+	/*
+	 * Workaround for ERR051586: Compliance with 8GT/s Receiver
+	 * Impedance ECN
+	 *
+	 * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] is
+	 * 1 which makes receiver non-compliant with the ZRX-DC
+	 * parameter for 2.5 GT/s when operating at 8 GT/s or higher. It
+	 * causes unnecessary timeout in L1.
+	 *
+	 * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] to 0.
+	 */
+	dw_pcie_dbi_write_enable(&priv->dw, true);
+	val = readl(priv->dw.dbi_base + GEN3_RELATED_OFF);
+	val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
+	writel(val, priv->dw.dbi_base + GEN3_RELATED_OFF);
+	dw_pcie_dbi_write_enable(&priv->dw, false);
+}
+
+static int imx8mm_pcie_enable_ref_clk(struct pcie_dw_imx *priv, bool enable)
+{
+	regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+			   IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE,
+			   enable ? 0 : IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE);
+	regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+			   IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+			   enable ? IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0);
+	return 0;
+}
+
 static const struct pcie_chip_info imx8mm_chip_info = {
+	.flags = IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHYDRV,
 	.gpr = "fsl,imx8mm-iomuxc-gpr",
+	.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
 };
 
 static const struct pcie_chip_info imx8mp_chip_info = {
+	.flags = IMX_PCIE_FLAG_HAS_APP_RESET | IMX_PCIE_FLAG_HAS_PHYDRV,
 	.gpr = "fsl,imx8mp-iomuxc-gpr",
+	.enable_ref_clk = imx8mm_pcie_enable_ref_clk,
 };
 
+static const struct pcie_chip_info imx95_chip_info = {
+	.flags = IMX_PCIE_FLAG_HAS_SERDES,
+	.ltssm_off = IMX95_PE0_GEN_CTRL_3,
+	.ltssm_mask = IMX95_PCIE_LTSSM_EN,
+	.mode_off[0]  = IMX95_PE0_GEN_CTRL_1,
+	.mode_mask[0] = IMX95_PCIE_DEVICE_TYPE,
+	.init_phy = imx95_pcie_init_phy,
+	.core_reset = imx95_pcie_core_reset,
+	.wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock,
+	.post_config = imx95_pcie_post_config,
+};
+
+static void imx_pcie_configure_type(struct pcie_dw_imx *priv)
+{
+	struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+	unsigned int mask, val, mode;
+
+	mode = PCI_EXP_TYPE_ROOT_PORT;
+
+	/* If mode_mask is 0, then generic PHY driver is used to set the mode */
+	if (!info->mode_mask[0])
+		return;
+
+	mask = info->mode_mask[0];
+	val = mode << (ffs(mask) - 1);
+
+	regmap_update_bits(priv->iomuxc_gpr, info->mode_off[0], mask, val);
+}
+
 static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
 {
 	dw_pcie_dbi_write_enable(&priv->dw, true);
@@ -75,17 +300,34 @@ static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
 	clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY,
 			TARGET_LINK_SPEED_MASK, cap_speed);
 
+	clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CTL_2,
+			TARGET_LINK_SPEED_MASK, cap_speed);
+
 	dw_pcie_dbi_write_enable(&priv->dw, false);
 }
 
 static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv)
 {
-	reset_deassert(&priv->apps_reset);
+	struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+	if (info->ltssm_mask)
+		regmap_update_bits(priv->iomuxc_gpr, info->ltssm_off, info->ltssm_mask,
+				   info->ltssm_mask);
+
+	if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+		reset_deassert(&priv->apps_reset);
 }
 
 static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv)
 {
-	reset_assert(&priv->apps_reset);
+	struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+	if (info->ltssm_mask)
+		regmap_update_bits(priv->iomuxc_gpr, info->ltssm_off,
+				   info->ltssm_mask, 0);
+
+	if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+		reset_assert(&priv->apps_reset);
 }
 
 static bool is_link_up(u32 val)
@@ -122,6 +364,11 @@ static int pcie_link_up(struct pcie_dw_imx *priv, u32 cap_speed)
 
 static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv)
 {
+	struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+	if (info->core_reset)
+		info->core_reset(priv, true);
+
 	if (dm_gpio_is_valid(&priv->reset_gpio)) {
 		dm_gpio_set_value(&priv->reset_gpio, 1);
 		mdelay(20);
@@ -133,6 +380,7 @@ static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv)
 static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
 {
 	int ret;
+	struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
 
 	ret = clk_enable_bulk(&priv->clks);
 	if (ret)
@@ -142,11 +390,8 @@ static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
 	 * Set the over ride low and enabled make sure that
 	 * REF_CLK is turned on.
 	 */
-	regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
-			   IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, 0);
-	regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
-			   IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
-			   IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
+	if (info->enable_ref_clk)
+		info->enable_ref_clk(priv, true);
 
 	/* allow the clocks to stabilize */
 	udelay(500);
@@ -156,6 +401,11 @@ static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
 
 static void imx_pcie_deassert_core_reset(struct pcie_dw_imx *priv)
 {
+	struct pcie_chip_info *info = (struct pcie_chip_info *)(priv->info);
+
+	if (info->core_reset)
+		info->core_reset(priv, false);
+
 	if (!dm_gpio_is_valid(&priv->reset_gpio))
 		return;
 
@@ -170,10 +420,11 @@ static int pcie_dw_imx_probe(struct udevice *dev)
 	struct pcie_dw_imx *priv = dev_get_priv(dev);
 	struct udevice *ctlr = pci_get_controller(dev);
 	struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+	struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
 	int ret;
 
 	if (priv->vpcie) {
-		ret = regulator_set_enable(priv->vpcie, true);
+		ret = regulator_set_enable_if_allowed(priv->vpcie, true);
 		if (ret) {
 			dev_err(dev, "failed to enable vpcie regulator\n");
 			return ret;
@@ -186,31 +437,49 @@ static int pcie_dw_imx_probe(struct udevice *dev)
 		return ret;
 	}
 
+	if (info->init_phy)
+		info->init_phy(priv);
+
+	imx_pcie_configure_type(priv);
+
 	ret = imx_pcie_clk_enable(priv);
 	if (ret) {
 		dev_err(dev, "failed to enable clocks\n");
 		goto err_clk;
 	}
 
-	ret = generic_phy_init(&priv->phy);
-	if (ret) {
-		dev_err(dev, "failed to initialize PHY\n");
-		goto err_phy_init;
-	}
+	if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) {
+		ret = generic_phy_init(&priv->phy);
+		if (ret) {
+			dev_err(dev, "failed to initialize PHY\n");
+			goto err_phy_init;
+		}
 
-	ret = generic_phy_power_on(&priv->phy);
-	if (ret) {
-		dev_err(dev, "failed to power on PHY\n");
-		goto err_phy_power;
+		ret = generic_phy_power_on(&priv->phy);
+		if (ret) {
+			dev_err(dev, "failed to power on PHY\n");
+			goto err_phy_power;
+		}
 	}
 
 	imx_pcie_deassert_core_reset(priv);
 
+	if (info->wait_pll_lock) {
+		ret = info->wait_pll_lock(priv);
+		if (ret) {
+			dev_err(dev, "failed to wait pll lock\n");
+			goto err_link;
+		}
+	}
+
+	if (info->post_config)
+		info->post_config(priv);
+
 	priv->dw.first_busno = dev_seq(dev);
 	priv->dw.dev = dev;
 	pcie_dw_setup_host(&priv->dw);
 
-	if (pcie_link_up(priv, LINK_SPEED_GEN_1)) {
+	if (pcie_link_up(priv, priv->max_link_speed)) {
 		printf("PCIE-%d: Link down\n", dev_seq(dev));
 		ret = -ENODEV;
 		goto err_link;
@@ -229,26 +498,41 @@ static int pcie_dw_imx_probe(struct udevice *dev)
 	return 0;
 
 err_link:
-	generic_shutdown_phy(&priv->phy);
+	if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV)
+		generic_shutdown_phy(&priv->phy);
 err_phy_power:
-	generic_phy_exit(&priv->phy);
+	if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV)
+		generic_phy_exit(&priv->phy);
 err_phy_init:
-	clk_disable_bulk(&priv->clks);
+	clk_release_bulk(&priv->clks);
 err_clk:
 	imx_pcie_deassert_core_reset(priv);
 
+	dm_gpio_free(dev, &priv->reset_gpio);
+
+	if (priv->vpcie)
+		regulator_set_enable_if_allowed(priv->vpcie, false);
+
 	return ret;
 }
 
 static int pcie_dw_imx_remove(struct udevice *dev)
 {
 	struct pcie_dw_imx *priv = dev_get_priv(dev);
+	struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
+
+	if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV)
+		generic_shutdown_phy(&priv->phy);
 
-	generic_shutdown_phy(&priv->phy);
 	dm_gpio_free(dev, &priv->reset_gpio);
-	reset_free(&priv->apps_reset);
+	if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+		reset_free(&priv->apps_reset);
+
 	clk_release_bulk(&priv->clks);
 
+	if (priv->vpcie)
+		regulator_set_enable_if_allowed(priv->vpcie, false);
+
 	return 0;
 }
 
@@ -257,7 +541,9 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
 	struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
 	struct pcie_dw_imx *priv = dev_get_priv(dev);
 	ofnode gpr;
-	int ret;
+	int ret, index;
+
+	priv->info = info;
 
 	/* Get the controller base address */
 	priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
@@ -274,17 +560,29 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	priv->dw.atu_base = (void *)dev_read_addr_name_ptr(dev, "atu");
+	if (!priv->dw.atu_base)
+		dev_dbg(dev, "failed to get atu address from dtb\n");
+
 	ret = clk_get_bulk(dev, &priv->clks);
 	if (ret) {
 		dev_err(dev, "failed to get PCIe clks\n");
 		return ret;
 	}
 
-	ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
-	if (ret) {
-		dev_err(dev,
-			"Failed to get PCIe apps reset control\n");
-		goto err_reset;
+	index = ofnode_stringlist_search(dev_ofnode(dev), "clock-names", "ext-ref");
+	if (index < 0)
+		priv->enable_ext_refclk = false;
+	else
+		priv->enable_ext_refclk = true;
+
+	if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET) {
+		ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
+		if (ret) {
+			dev_err(dev,
+				"Failed to get PCIe apps reset control\n");
+			goto err_reset;
+		}
 	}
 
 	ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
@@ -294,26 +592,58 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
 		goto err_gpio;
 	}
 
-	ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy);
-	if (ret) {
-		dev_err(dev, "failed to get pcie phy\n");
-		goto err_phy;
+	if (info->flags & IMX_PCIE_FLAG_HAS_PHYDRV) {
+		ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy);
+		if (ret) {
+			dev_err(dev, "failed to get pcie phy\n");
+			goto err_phy;
+		}
 	}
 
-	gpr = ofnode_by_compatible(ofnode_null(), info->gpr);
-	if (ofnode_equal(gpr, ofnode_null())) {
-		dev_err(dev, "unable to find GPR node\n");
-		ret = -ENODEV;
-		goto err_phy;
+	if (info->flags & IMX_PCIE_FLAG_HAS_SERDES) {
+		void __iomem *app_base;
+		fdt_size_t app_size;
+		struct regmap_config config;
+
+		app_base = (void *)dev_read_addr_size_name(dev, "app", &app_size);
+		if ((fdt_addr_t)app_base == FDT_ADDR_T_NONE) {
+			dev_err(dev, "failed to get app_base address\n");
+			return -EINVAL;
+		}
+
+		config.r_start = (ulong)app_base;
+		config.r_size = (ulong)app_size;
+		config.reg_offset_shift = 0;
+		config.width = REGMAP_SIZE_32;
+
+		priv->iomuxc_gpr = devm_regmap_init(dev, NULL, NULL, &config);
+		if (IS_ERR(priv->iomuxc_gpr)) {
+			dev_err(dev, "unable to remap gpr\n");
+			ret = PTR_ERR(priv->iomuxc_gpr);
+			goto err_phy;
+		}
 	}
 
-	priv->iomuxc_gpr = syscon_node_to_regmap(gpr);
-	if (IS_ERR(priv->iomuxc_gpr)) {
-		dev_err(dev, "unable to find iomuxc registers\n");
-		ret = PTR_ERR(priv->iomuxc_gpr);
-		goto err_phy;
+	if (info->gpr) {
+		gpr = ofnode_by_compatible(ofnode_null(), info->gpr);
+		if (ofnode_equal(gpr, ofnode_null())) {
+			dev_err(dev, "unable to find GPR node\n");
+			ret = -ENODEV;
+			goto err_phy;
+		}
+
+		priv->iomuxc_gpr = syscon_node_to_regmap(gpr);
+		if (IS_ERR(priv->iomuxc_gpr)) {
+			dev_err(dev, "unable to find iomuxc registers\n");
+			ret = PTR_ERR(priv->iomuxc_gpr);
+			goto err_phy;
+		}
 	}
 
+	priv->max_link_speed = dev_read_u32_default(dev, "fsl,max-link-speed", LINK_SPEED_GEN_1);
+
+	priv->supports_clkreq = dev_read_bool(dev, "supports-clkreq");
+
 	/* vpcie-supply regulator is optional */
 	device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie);
 
@@ -322,7 +652,8 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
 err_phy:
 	dm_gpio_free(dev, &priv->reset_gpio);
 err_gpio:
-	reset_free(&priv->apps_reset);
+	if (info->flags & IMX_PCIE_FLAG_HAS_APP_RESET)
+		reset_free(&priv->apps_reset);
 err_reset:
 	clk_release_bulk(&priv->clks);
 
@@ -337,6 +668,7 @@ static const struct dm_pci_ops pcie_dw_imx_ops = {
 static const struct udevice_id pcie_dw_imx_ids[] = {
 	{ .compatible = "fsl,imx8mm-pcie", .data = (ulong)&imx8mm_chip_info, },
 	{ .compatible = "fsl,imx8mp-pcie", .data = (ulong)&imx8mp_chip_info, },
+	{ .compatible = "fsl,imx95-pcie", .data = (ulong)&imx95_chip_info, },
 	{ }
 };
 

From d680ac6cfd052ced54f51d7cfe081ad291550e44 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:06 +0800
Subject: [PATCH 04/15] clk: imx: Add imx95 blkctrl clock driver

Add iMX95 blkctrl clock driver which implements clocks for HSIOMIX
blkctrl and LVDS blkctrl.
Since multiple blkctrl device for different blkctrl may be enabled,
and each has dedicated clock id from 0. We must enable CLK_AUTO_ID
to avoid conflict on clock id.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 drivers/clk/imx/Kconfig             |   9 ++
 drivers/clk/imx/Makefile            |   1 +
 drivers/clk/imx/clk-imx95-blkctrl.c | 170 ++++++++++++++++++++++++++++
 3 files changed, 180 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx95-blkctrl.c

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 74d5fe73f94..644ab162af4 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -167,3 +167,12 @@ config CLK_IMXRT1170
 	select CLK_CCF
 	help
 	  This enables support clock driver for i.MXRT1170 platforms.
+
+config CLK_IMX95_BLKCTRL
+	bool "Enable i.MX95 blkctrl clock driver"
+	depends on IMX95 || IMX94
+	select CLK
+	select CLK_CCF
+	select CLK_AUTO_ID
+	help
+	  Enable support for clocks in i.MX95 MIX blkctrl like HSIO and LVDS.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index b10221a195c..f2fd6ff8ca0 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \
 obj-$(CONFIG_$(PHASE_)CLK_IMXRT1020) += clk-imxrt1020.o
 obj-$(CONFIG_$(PHASE_)CLK_IMXRT1050) += clk-imxrt1050.o
 obj-$(CONFIG_$(PHASE_)CLK_IMXRT1170) += clk-imxrt1170.o
+obj-$(CONFIG_CLK_IMX95_BLKCTRL) += clk-imx95-blkctrl.o
diff --git a/drivers/clk/imx/clk-imx95-blkctrl.c b/drivers/clk/imx/clk-imx95-blkctrl.c
new file mode 100644
index 00000000000..3bf6f9415e2
--- /dev/null
+++ b/drivers/clk/imx/clk-imx95-blkctrl.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023-2025 NXP
+ *
+ */
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dt-bindings/clock/nxp,imx95-clock.h>
+#include <linux/clk-provider.h>
+
+#include "clk.h"
+
+enum {
+	CLK_GATE,
+	CLK_DIVIDER,
+	CLK_MUX,
+};
+
+struct imx95_blk_ctl_clk_dev_data {
+	const char *name;
+	const char * const *parent_names;
+	u32 num_parents;
+	u32 reg;
+	u32 bit_idx;
+	u32 clk_type;
+	u32 flags;
+	u32 flags2;
+	u32 type;
+};
+
+struct imx95_blk_ctl_dev_data {
+	const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
+	u32 num_clks;
+	u32 clk_reg_offset;
+};
+
+static const struct imx95_blk_ctl_clk_dev_data hsio_blk_ctl_clk_dev_data[] = {
+	[0] = {
+		.name = "hsio_blk_ctl_clk",
+		.parent_names = (const char *[]){ "hsiopll", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 6,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+	}
+};
+
+static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {
+	.num_clks = 1,
+	.clk_dev_data = hsio_blk_ctl_clk_dev_data,
+	.clk_reg_offset = 0,
+};
+
+static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data[] = {
+	[IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {
+		.name = "ldb_phy_div",
+		.parent_names = (const char *[]){ "ldbpll", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 0,
+		.type = CLK_DIVIDER,
+		.flags2 = CLK_DIVIDER_POWER_OF_TWO,
+	},
+
+    [IMX95_CLK_DISPMIX_LVDS_CH0_GATE] = {
+		.name = "lvds_ch0_gate",
+		.parent_names = (const char *[]){ "ldb_phy_div", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 1,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+		.flags2 = CLK_GATE_SET_TO_DISABLE,
+    },
+    [IMX95_CLK_DISPMIX_LVDS_CH1_GATE] = {
+		.name = "lvds_ch1_gate",
+		.parent_names = (const char *[]){ "ldb_phy_div", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 2,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+		.flags2 = CLK_GATE_SET_TO_DISABLE,
+    },
+    [IMX95_CLK_DISPMIX_PIX_DI0_GATE] = {
+		.name = "lvds_di0_gate",
+		.parent_names = (const char *[]){ "ldb_pll_div7", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 3,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+		.flags2 = CLK_GATE_SET_TO_DISABLE,
+    },
+    [IMX95_CLK_DISPMIX_PIX_DI1_GATE] = {
+		.name = "lvds_di1_gate",
+		.parent_names = (const char *[]){ "ldb_pll_div7", },
+		.num_parents = 1,
+		.reg = 0,
+		.bit_idx = 4,
+		.type = CLK_GATE,
+		.flags = CLK_SET_RATE_PARENT,
+		.flags2 = CLK_GATE_SET_TO_DISABLE,
+    },
+};
+
+static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = {
+	.num_clks = ARRAY_SIZE(imx95_lvds_clk_dev_data),
+	.clk_dev_data = imx95_lvds_clk_dev_data,
+	.clk_reg_offset = 0,
+};
+
+static int imx95_blkctrl_clk_probe(struct udevice *dev)
+{
+	int i;
+	void __iomem *addr;
+	struct imx95_blk_ctl_dev_data *dev_data = (void *)dev_get_driver_data(dev);
+	const struct imx95_blk_ctl_clk_dev_data *clk_dev_data;
+
+	addr = dev_read_addr_ptr(dev);
+	if (addr == (void *)FDT_ADDR_T_NONE) {
+		dev_err(dev, "No blkctrl register base address\n");
+		return -EINVAL;
+	}
+
+	if (!dev_data) {
+		dev_err(dev, "driver data is NULL\n");
+		return -EINVAL;
+	}
+
+	clk_dev_data = dev_data->clk_dev_data;
+	for (i = 0; i < dev_data->num_clks; i++) {
+		if (clk_dev_data[i].clk_type == CLK_GATE) {
+			dev_clk_dm(dev, i, clk_register_gate(dev, clk_dev_data[i].name, clk_dev_data[i].parent_names[0],
+					clk_dev_data[i].flags, addr + dev_data->clk_reg_offset, clk_dev_data[i].bit_idx,
+					clk_dev_data[i].flags2, NULL));
+		} else if (clk_dev_data[i].clk_type == CLK_DIVIDER) {
+			dev_clk_dm(dev, i,
+				clk_register_divider(dev, clk_dev_data[i].name, clk_dev_data[i].parent_names[0],
+					clk_dev_data[i].flags, addr + dev_data->clk_reg_offset, clk_dev_data[i].bit_idx, 1,
+					clk_dev_data[i].flags2));
+		} else if (clk_dev_data[i].clk_type == CLK_MUX) {
+			dev_clk_dm(dev, i,
+				clk_register_mux(dev, clk_dev_data[i].name, clk_dev_data[i].parent_names,
+					clk_dev_data[i].num_parents, clk_dev_data[i].flags, addr + dev_data->clk_reg_offset,
+					clk_dev_data[i].bit_idx, 1, clk_dev_data[i].flags2));
+		}
+	}
+
+	return 0;
+}
+
+static const struct udevice_id imx95_blkctrl_clk_ids[] = {
+	{ .compatible = "nxp,imx95-lvds-csr", .data = (ulong)&imx95_lvds_csr_dev_data, },
+	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = (ulong)&hsio_blk_ctl_dev_data,  },
+	{ },
+};
+
+U_BOOT_DRIVER(imx95_blkctrl_clk) = {
+	.name = "imx95_blkctrl_clk",
+	.id = UCLASS_CLK,
+	.of_match = imx95_blkctrl_clk_ids,
+	.ops = &ccf_clk_ops,
+	.probe = imx95_blkctrl_clk_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};

From f98d812e5353408ef77a46bad1f1cdc793ff8a03 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:07 +0800
Subject: [PATCH 05/15] power: regulator: Add vin-supply for GPIO and Fixed
 regulators

Enable the vin-supply when probing the regulator device.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 drivers/power/regulator/regulator_common.c | 10 ++++++++++
 drivers/power/regulator/regulator_common.h |  1 +
 2 files changed, 11 insertions(+)

diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c
index e3565d32a01..c80f10c3aa3 100644
--- a/drivers/power/regulator/regulator_common.c
+++ b/drivers/power/regulator/regulator_common.c
@@ -45,6 +45,16 @@ int regulator_common_of_to_plat(struct udevice *dev,
 			dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0);
 	}
 
+	ret = device_get_supply_regulator(dev, "vin-supply", &plat->vin_supply);
+	if (ret) {
+		debug("Regulator vin regulator not defined: %d\n", ret);
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	if (plat->vin_supply)
+		regulator_set_enable_if_allowed(plat->vin_supply, true);
+
 	return 0;
 }
 
diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h
index d4962899d83..799c968d0b6 100644
--- a/drivers/power/regulator/regulator_common.h
+++ b/drivers/power/regulator/regulator_common.h
@@ -14,6 +14,7 @@ struct regulator_common_plat {
 	unsigned int startup_delay_us;
 	unsigned int off_on_delay_us;
 	unsigned int enable_count;
+	struct udevice *vin_supply;
 };
 
 int regulator_common_of_to_plat(struct udevice *dev,

From 87119e0f793d55bc540ac98fea9d75c3cb5ac8be Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:08 +0800
Subject: [PATCH 06/15] clk: clk-uclass: Fix clk_set_default_rates issue

clk_set_rate returns the actual clock rate, When assigned clock rate is
higher than 0x7FFFFFFF, the return value will be recognized as error.
Change to IS_ERR_VALUE to check the return value.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 drivers/clk/clk-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 7262e89b512..3dbe1ce9441 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -358,7 +358,7 @@ static int clk_set_default_rates(struct udevice *dev,
 
 		ret = clk_set_rate(c, rates[index]);
 
-		if (ret < 0) {
+		if (IS_ERR_VALUE(ret)) {
 			dev_warn(dev,
 				 "failed to set rate on clock index %d (%ld) (error = %d)\n",
 				 index, clk.id, ret);

From 749f6762b40859c24db6f13ba491300c1d22508c Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:09 +0800
Subject: [PATCH 07/15] arm: dts: imx95: Assign HSIOPLL_VCO as HSIOPLL parent
 clock

We have to explicitly assign HSIOPLL_VCO as HSIOPLL parent. So when
enabling HSIOPLL, its parent HSIOPLL_VCO will be enabled firstly.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx95-u-boot.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
index 9bf8f9834c9..27f8209b19c 100644
--- a/arch/arm/dts/imx95-u-boot.dtsi
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -170,6 +170,22 @@
 	bootph-all;
 };
 
+&pcie0 {
+	assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+					 <&scmi_clk IMX95_CLK_HSIOPLL>,
+					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+	assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+				 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+};
+
+&pcie1 {
+	assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+					 <&scmi_clk IMX95_CLK_HSIOPLL>,
+					 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
+	assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
+				 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
+};
+
 &{/soc} {
 	bootph-all;
 };

From 5c4e28e52f247bfc4fca4e5f61246e510602ad9e Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:10 +0800
Subject: [PATCH 08/15] arm: dts: imx95-evk: set alias for enetc PCI buses

Use fixed seq 0 and 1 for enetc PCI buses, then the seq for PCI controllers
could start after them.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx95-19x19-evk-u-boot.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
index 2d1f02baa5f..8b59831b7ca 100644
--- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
@@ -5,6 +5,13 @@
 
 #include "imx95-u-boot.dtsi"
 
+/ {
+	aliases {
+		pci0 = &netc_bus0;
+		pci1 = &netc_bus1;
+	};
+};
+
 &lpuart1 {
 	bootph-pre-ram;
 };

From 9f90e39d1cc458e2955c1edbe8a018c0c6c08b32 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 11 Sep 2025 18:56:11 +0800
Subject: [PATCH 09/15] imx95_evk: Enable PCI host controller on iMX95 19x19
 EVK

Enable DW IMX PCI driver and iMX95 BLKCTRL clock driver in defconfig,
so PCI controller can work.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 configs/imx95_19x19_evk_defconfig | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig
index 73818a82627..f0a31dbda7b 100644
--- a/configs/imx95_19x19_evk_defconfig
+++ b/configs/imx95_19x19_evk_defconfig
@@ -94,15 +94,12 @@ CONFIG_ETHPRIME="eth0"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_RX_ETH_BUFFER=8
 CONFIG_SPL_DM=y
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
-CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_SPL_CLK_CCF=y
-CONFIG_CLK_CCF=y
 CONFIG_CLK_SCMI=y
 CONFIG_SPL_CLK_SCMI=y
+CONFIG_CLK_IMX95_BLKCTRL=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_SPL_FIRMWARE=y
@@ -130,13 +127,13 @@ CONFIG_DM_MDIO=y
 CONFIG_MII=y
 CONFIG_FSL_ENETC=y
 CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_PCIE_DW_IMX=y
 CONFIG_PHY=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX_SCMI=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_SCMI_POWER_DOMAIN=y
-CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPL_DM_REGULATOR_FIXED=y

From 8918b60e33157dd6abaaf11ea24437da133eed0a Mon Sep 17 00:00:00 2001
From: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
Date: Mon, 15 Sep 2025 14:57:02 +0200
Subject: [PATCH 10/15] imx93_frdm: Add support for flashing board with UUU

Allow to flash a board using NXP UUU utility:
- Enable fastboot support on USB.
- Add fastboot partition aliases with names used by UUU. Also add extra
  environment variables used by UUU.
- Set 'dofastboot' environment variable based on boot device
  configuration, allowing to automatically enter fastboot when booting
  from USB.

Signed-off-by: Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com>
---
 board/freescale/imx93_frdm/imx93_frdm.c   |  6 ++++++
 board/freescale/imx93_frdm/imx93_frdm.env |  8 ++++++++
 configs/imx93_frdm_defconfig              | 14 ++++++++++++++
 doc/board/nxp/imx93_frdm.rst              | 22 ++++++++++++++++++++++
 4 files changed, 50 insertions(+)

diff --git a/board/freescale/imx93_frdm/imx93_frdm.c b/board/freescale/imx93_frdm/imx93_frdm.c
index c74fd85712f..c436ac6aa47 100644
--- a/board/freescale/imx93_frdm/imx93_frdm.c
+++ b/board/freescale/imx93_frdm/imx93_frdm.c
@@ -10,6 +10,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-imx9/imx93_pins.h>
 #include <asm/arch/clock.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <dm/device.h>
 #include <dm/uclass.h>
 
@@ -55,5 +56,10 @@ int board_late_init(void)
 		env_set("board_rev", "iMX93");
 	}
 
+	if (get_boot_device() == USB_BOOT) {
+		printf("USB boot detected. Will enter fasboot mode\n");
+		env_set_ulong("dofastboot", 1);
+	}
+
 	return 0;
 }
diff --git a/board/freescale/imx93_frdm/imx93_frdm.env b/board/freescale/imx93_frdm/imx93_frdm.env
index 528a953c8df..111f38ed72a 100644
--- a/board/freescale/imx93_frdm/imx93_frdm.env
+++ b/board/freescale/imx93_frdm/imx93_frdm.env
@@ -19,8 +19,16 @@ kernel_addr_r=CONFIG_SYS_LOAD_ADDR
 loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
 loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}
 boot_os=booti ${loadaddr} - ${fdt_addr_r}
+fastboot_partition_alias_all=0:0
+fastboot_partition_alias_bootloader=0.1
+emmc_dev=0
+sd_dev=1
+dofastboot=0
 
 bsp_bootcmd=
+	if test ${dofastboot} = 1; then
+		fastboot 0;
+	fi;
 	echo Running BSP bootcmd ...;
 	mmc dev ${mmcdev};
 	run mmcargs;
diff --git a/configs/imx93_frdm_defconfig b/configs/imx93_frdm_defconfig
index 4f837ca9282..eddd36c618d 100644
--- a/configs/imx93_frdm_defconfig
+++ b/configs/imx93_frdm_defconfig
@@ -30,6 +30,7 @@ CONFIG_EFI_VAR_BUF_SIZE=139264
 CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_BOOTCOMMAND="bootflow scan -lb; run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx93-11x11-frdm.dtb"
 CONFIG_SYS_CBSIZE=2048
@@ -58,6 +59,7 @@ CONFIG_CMD_ERASEENV=y
 CONFIG_CMD_NVEDIT_EFI=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_BIND is not set
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
@@ -91,6 +93,11 @@ CONFIG_ADC_IMX93=y
 CONFIG_SPL_CLK_IMX93=y
 CONFIG_CLK_IMX93=y
 CONFIG_DFU_MMC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_IMX_RGPIO2P=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
@@ -116,6 +123,13 @@ CONFIG_SYSRESET=y
 CONFIG_SYSRESET_CMD_POWEROFF=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
 CONFIG_ULP_WATCHDOG=y
 CONFIG_WDT=y
 CONFIG_SHA384=y
diff --git a/doc/board/nxp/imx93_frdm.rst b/doc/board/nxp/imx93_frdm.rst
index a1f526fd4cc..3c3e5f49b04 100644
--- a/doc/board/nxp/imx93_frdm.rst
+++ b/doc/board/nxp/imx93_frdm.rst
@@ -13,6 +13,7 @@ Quick Start
 - Get ahab-container.img
 - Build U-Boot
 - Boot from the SD card
+- Boot using USB serial download (uuu)
 
 Get and Build the ARM Trusted firmware
 --------------------------------------
@@ -73,3 +74,24 @@ Boot from the SD card
   at /dev/ttyACM0.
 - Power on the board by connecting a USB Type-C cable into the P1
   Power USB Port.
+
+Boot using USB serial download (uuu)
+------------------------------------
+
+- Configure SW1 boot switches to serial download boot mode:
+  0001 SW1[3:0] - ("Serial downloader (USB)" Boot Mode)
+- Plug USB Type-C cable into the P2 device port.
+- Connect a USB Type-C cable into the P16 Debug USB Port and connect
+  using a terminal emulator at 115200 bps, 8n1. The console will show up
+  at /dev/ttyACM0.
+- Power on the board by connecting a USB Type-C cable into the P1
+  Power USB Port.
+- Use NXP Universal Update Utility `NXP Universal Update Utility`_ to boot or
+  flash the device. E.g. following command can be used to flash an image onto
+  the eMMC storage:
+
+.. code-block:: bash
+
+   $ uuu -V -b emmc_all <image file>
+
+.. _`NXP Universal Update Utility`: https://github.com/nxp-imx/mfgtools

From 2727de799a644f4db15e8682503f783a62fa4af2 Mon Sep 17 00:00:00 2001
From: Peng Fan <peng.fan@nxp.com>
Date: Tue, 16 Sep 2025 10:57:35 +0800
Subject: [PATCH 11/15] power: regulator: pfuze100: Fix accessing the regulator
 desc

se_desc loop check is wrong, it relies on the desc always has
the expected name to end of the loop. It works because the device tree
has the expected name as of now, but this may not be always true.

Drop se_desc by moving the check into probe and fix the loop check.

Reported-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/power/regulator/pfuze100.c | 44 ++++++++++++------------------
 1 file changed, 17 insertions(+), 27 deletions(-)

diff --git a/drivers/power/regulator/pfuze100.c b/drivers/power/regulator/pfuze100.c
index bf3a7019411..f864b1d8834 100644
--- a/drivers/power/regulator/pfuze100.c
+++ b/drivers/power/regulator/pfuze100.c
@@ -241,56 +241,46 @@ static struct dm_regulator_mode pfuze_ldo_modes[] = {
 	MODE(LDO_MODE_ON, LDO_MODE_ON, "LDO_MODE_ON"),
 };
 
-static struct pfuze100_regulator_desc *se_desc(struct pfuze100_regulator_desc *desc,
-					       int size,
-					       const char *name)
-{
-	int i;
-
-	for (i = 0; i < size; desc++) {
-		if (!strcmp(desc->name, name))
-			return desc;
-		continue;
-	}
-
-	return NULL;
-}
-
 static int pfuze100_regulator_probe(struct udevice *dev)
 {
 	struct dm_regulator_uclass_plat *uc_pdata;
 	struct pfuze100_regulator_plat *plat = dev_get_plat(dev);
 	struct pfuze100_regulator_desc *desc;
+	int i, size;
 
 	switch (dev_get_driver_data(dev_get_parent(dev))) {
 	case PFUZE100:
-		desc = se_desc(pfuze100_regulators,
-			       ARRAY_SIZE(pfuze100_regulators),
-			       dev->name);
+		desc = pfuze100_regulators;
+		size = ARRAY_SIZE(pfuze100_regulators);
 		break;
 	case PFUZE200:
-		desc = se_desc(pfuze200_regulators,
-			       ARRAY_SIZE(pfuze200_regulators),
-			       dev->name);
+		desc = pfuze200_regulators;
+		size = ARRAY_SIZE(pfuze200_regulators);
 		break;
 	case PFUZE3000:
-		desc = se_desc(pfuze3000_regulators,
-			       ARRAY_SIZE(pfuze3000_regulators),
-			       dev->name);
+		desc = pfuze3000_regulators;
+		size = ARRAY_SIZE(pfuze3000_regulators);
 		break;
 	default:
 		debug("Unsupported PFUZE\n");
 		return -EINVAL;
 	}
-	if (!desc) {
+
+	for (i = 0; i < size; i++) {
+		if (strcmp(desc[i].name, dev->name))
+			continue;
+		break;
+	}
+
+	if (i == size) {
 		debug("Do not support regulator %s\n", dev->name);
 		return -EINVAL;
 	}
 
-	plat->desc = desc;
+	plat->desc = &desc[i];
 	uc_pdata = dev_get_uclass_plat(dev);
 
-	uc_pdata->type = desc->type;
+	uc_pdata->type = desc[i].type;
 	if (uc_pdata->type == REGULATOR_TYPE_BUCK) {
 		if (!strcmp(dev->name, "swbst")) {
 			uc_pdata->mode = pfuze_swbst_modes;

From edc666f1cf721c12ebc2fc096d362f8b14004d3a Mon Sep 17 00:00:00 2001
From: Ricardo Simoes <ricardo.simoes@pt.bosch.com>
Date: Wed, 17 Sep 2025 17:59:32 +0200
Subject: [PATCH 12/15] clk: imx6q: Add definition for missing PWM clocks

Following the work done in commit 7f39ad5a ("clk: imx6q: Add definition
for IMX6QDL_CLK_PWM1"), this commit adds definitions for PWM2, PWM3, and
PWM4 clocks. Allowing one to use these PWM modules together with DM_CLK.

Note that the solution was verified only against PWM3.

Signed-off-by: Ricardo Simoes <ricardo.simoes@pt.bosch.com>
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com>
---
 drivers/clk/imx/clk-imx6q.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 13239f2f64d..b69355cefc7 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -156,6 +156,12 @@ static int imx6q_clk_probe(struct udevice *dev)
 	       imx_clk_gate2(dev, "i2c3", "ipg_per", base + 0x70, 10));
 	clk_dm(IMX6QDL_CLK_PWM1,
 	       imx_clk_gate2(dev, "pwm1", "ipg_per", base + 0x78, 16));
+	clk_dm(IMX6QDL_CLK_PWM2,
+	       imx_clk_gate2(dev, "pwm2", "ipg_per", base + 0x78, 18));
+	clk_dm(IMX6QDL_CLK_PWM3,
+	       imx_clk_gate2(dev, "pwm3", "ipg_per", base + 0x78, 20));
+	clk_dm(IMX6QDL_CLK_PWM4,
+	       imx_clk_gate2(dev, "pwm4", "ipg_per", base + 0x78, 22));
 
 	clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10));
 	clk_dm(IMX6QDL_CLK_ENET_REF,

From f7857695c914756f7c62dca23b3a675e779ae0f1 Mon Sep 17 00:00:00 2001
From: Yannic Moog <y.moog@phytec.de>
Date: Thu, 18 Sep 2025 08:13:55 +0200
Subject: [PATCH 13/15] phytec-imx8m boards: enable OP-TEE for KASLR

Enable OP-TEE config and RNG by default.
Set OP-TEE load address to end of 1GiB RAM for phycore-imx8mp and
phycore-imx8mm as the boards support a 1GiB RAM variant (although not
yet upstreamed for phycore-imx8mm).
The imx8mm-phygate-tauri-l board only supports 2GiB, so the default at
the end of 2GiB is sufficient.

Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
---
 configs/imx8mm-phygate-tauri-l_defconfig | 5 ++++-
 configs/phycore-imx8mm_defconfig         | 5 ++++-
 configs/phycore-imx8mp_defconfig         | 4 ++++
 3 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig
index 7369c0a05ac..6dc95d6d3ed 100644
--- a/configs/imx8mm-phygate-tauri-l_defconfig
+++ b/configs/imx8mm-phygate-tauri-l_defconfig
@@ -73,9 +73,9 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMX8MM=y
 CONFIG_CLK_IMX8MM=y
+CONFIG_FSL_CAAM=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
-CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x51
 CONFIG_SUPPORT_EMMC_BOOT=y
@@ -97,11 +97,14 @@ CONFIG_IMX8M_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 4d6bce26f07..4cf4d397256 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -82,9 +82,9 @@ CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_IMX8MM=y
 CONFIG_CLK_IMX8MM=y
+CONFIG_FSL_CAAM=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
-CONFIG_MISC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_SYS_I2C_EEPROM_ADDR=0x51
 CONFIG_SUPPORT_EMMC_BOOT=y
@@ -120,6 +120,7 @@ CONFIG_POWER_DOMAIN=y
 CONFIG_IMX8M_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
@@ -129,5 +130,7 @@ CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
 CONFIG_DM_THERMAL=y
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index 6bd8bcf15da..c497f0bcd91 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -13,6 +13,7 @@ CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mp-phyboard-pollux-rdk"
+CONFIG_IMX8M_OPTEE_LOAD_ADDR=0x7e000000
 CONFIG_TARGET_PHYCORE_IMX8MP=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
@@ -153,6 +154,7 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RNG=y
 CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
@@ -162,6 +164,8 @@ CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
 CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y

From cb1292450d89391b56e83e00e4520935f95d403e Mon Sep 17 00:00:00 2001
From: Yannic Moog <y.moog@phytec.de>
Date: Thu, 18 Sep 2025 08:13:56 +0200
Subject: [PATCH 14/15] doc: phytec: update imx8m docs for optee builds

OP-TEE configs are enabled by default, change the doc to no longer
declare OP-TEE as optional. Also remove CFG_TEE_BENCHMARK as it is no
longer present in optee_os.
Further, phycore-imx8mm and imx8mm-phygate-tauri-l use different build
instructions, so dissolve the common file for building OP-TEE.

Reviewed-by: Teresa Remmet <t.remmet@phytec.de>
Signed-off-by: Yannic Moog <y.moog@phytec.de>
---
 board/phytec/phycore_imx8mm/MAINTAINERS     |  1 -
 doc/board/phytec/imx8mm-optee-build.rsti    | 14 --------------
 doc/board/phytec/imx8mm-phygate-tauri-l.rst | 18 ++++++++++++------
 doc/board/phytec/imx8mp-libra-fpsc.rst      |  1 -
 doc/board/phytec/phycore-imx8mm.rst         | 18 ++++++++++++------
 doc/board/phytec/phycore-imx8mp.rst         | 16 ++++++----------
 6 files changed, 30 insertions(+), 38 deletions(-)
 delete mode 100644 doc/board/phytec/imx8mm-optee-build.rsti

diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS
index 7631e1cb331..58c5e2d0af9 100644
--- a/board/phytec/phycore_imx8mm/MAINTAINERS
+++ b/board/phytec/phycore_imx8mm/MAINTAINERS
@@ -9,6 +9,5 @@ F:	configs/imx8mm-phygate-tauri-l_defconfig
 F:      configs/phycore-imx8mm_defconfig
 F:	doc/board/phytec/imx8mm-phygate-tauri-l.rst
 F:	doc/board/phytec/index.rst
-F:	doc/board/phytec/imx8mm-optee-build.rsti
 F:	doc/board/phytec/phycore_imx8mm.rst
 F:      include/configs/phycore_imx8mm.h
diff --git a/doc/board/phytec/imx8mm-optee-build.rsti b/doc/board/phytec/imx8mm-optee-build.rsti
deleted file mode 100644
index c83de5cc7cf..00000000000
--- a/doc/board/phytec/imx8mm-optee-build.rsti
+++ /dev/null
@@ -1,14 +0,0 @@
-Build the OP-TEE binary (optional)
-----------------------------------
-
-.. code-block:: bash
-
-   $ git clone https://github.com/OP-TEE/optee_os.git
-   $ cd optee_os
-   $ make CFG_TEE_BENCHMARK=n \
-     CROSS_COMPILE=aarch64-linux-gnu- \
-     O=out/arm \
-     PLATFORM=imx-mx8mmevk \
-     CFG_TZDRAM_START=0x56000000 \
-     CFG_DDR_SIZE=0x80000000 \
-     CFG_UART_BASE=UART3_BASE
diff --git a/doc/board/phytec/imx8mm-phygate-tauri-l.rst b/doc/board/phytec/imx8mm-phygate-tauri-l.rst
index 0d9e1024f8c..bc58a141e4f 100644
--- a/doc/board/phytec/imx8mm-phygate-tauri-l.rst
+++ b/doc/board/phytec/imx8mm-phygate-tauri-l.rst
@@ -9,7 +9,7 @@ Quick Start
 -----------
 
 - Build the ARM Trusted firmware binary
-- Build the OP-TEE binary (optional)
+- Build the OP-TEE binary
 - Get ddr firmware
 - Build U-Boot
 - Boot
@@ -23,12 +23,18 @@ Build the ARM Trusted firmware binary
    $ cd trusted-firmware-a
    $ export CROSS_COMPILE=aarch64-linux-gnu-
    $ export IMX_BOOT_UART_BASE=0x30880000
-   $ # with optee
-   $ make PLAT=imx8mm BL32_BASE=0x56000000 SPD=opteed bl31
-   $ # without optee
-   $ make PLAT=imx8mm bl31
+   $ make PLAT=imx8mm BL32_BASE=0xbe000000 SPD=opteed bl31
 
-.. include:: imx8mm-optee-build.rsti
+Build the OP-TEE binary
+-----------------------
+
+.. code-block:: bash
+
+   $ git clone https://github.com/OP-TEE/optee_os.git
+   $ cd optee_os
+   $ make CROSS_COMPILE=aarch64-linux-gnu- \
+          O=out/arm \
+          PLATFORM=imx-mx8mm_phygate_tauri_l
 
 Get the ddr firmware
 --------------------
diff --git a/doc/board/phytec/imx8mp-libra-fpsc.rst b/doc/board/phytec/imx8mp-libra-fpsc.rst
index 26752ac1882..87b7a99ee71 100644
--- a/doc/board/phytec/imx8mp-libra-fpsc.rst
+++ b/doc/board/phytec/imx8mp-libra-fpsc.rst
@@ -40,7 +40,6 @@ Build the OP-TEE binary
    $ cd optee_os
    $ make -j $(nproc) \
           CROSS_COMPILE=aarch64-linux-gnu- \
-          CFG_TEE_BENCHMARK=n \
           O=out/arm \
           PLATFORM=imx-mx8mp_libra_fpsc
 
diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst
index 08f5949e02d..f8fa420019c 100644
--- a/doc/board/phytec/phycore-imx8mm.rst
+++ b/doc/board/phytec/phycore-imx8mm.rst
@@ -9,7 +9,7 @@ Quick Start
 -----------
 
 - Build the ARM Trusted firmware binary
-- Build the OP-TEE binary (optional)
+- Build the OP-TEE binary
 - Get ddr firmware
 - Build U-Boot
 - Boot
@@ -23,12 +23,18 @@ Build the ARM Trusted firmware binary
    $ cd trusted-firmware-a
    $ export CROSS_COMPILE=aarch64-linux-gnu-
    $ export IMX_BOOT_UART_BASE=0x30880000
-   $ # with optee
-   $ make PLAT=imx8mm BL32_BASE=0x56000000 SPD=opteed bl31
-   $ # without optee
-   $ make PLAT=imx8mm bl31
+   $ make PLAT=imx8mm BL32_BASE=0x7e000000 SPD=opteed bl31
 
-.. include:: imx8mm-optee-build.rsti
+Build the OP-TEE binary
+-----------------------
+
+.. code-block:: bash
+
+   $ git clone https://github.com/OP-TEE/optee_os.git
+   $ cd optee_os
+   $ make CROSS_COMPILE=aarch64-linux-gnu- \
+          O=out/arm \
+          PLATFORM=imx-mx8mm_phyboard_polis
 
 Get the ddr firmware
 --------------------
diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst
index 50be9912653..df087072062 100644
--- a/doc/board/phytec/phycore-imx8mp.rst
+++ b/doc/board/phytec/phycore-imx8mp.rst
@@ -9,7 +9,7 @@ Quick Start
 -----------
 
 - Build the ARM Trusted firmware binary
-- Build the OP-TEE binary (optional)
+- Build the OP-TEE binary
 - Get ddr firmware
 - Build U-Boot
 - Boot
@@ -23,23 +23,19 @@ Build the ARM Trusted firmware binary
    $ cd trusted-firmware-a
    $ export CROSS_COMPILE=aarch64-linux-gnu-
    $ export IMX_BOOT_UART_BASE=0x30860000
-   $ # with optee
-   $ make PLAT=imx8mp SPD=opteed bl31
-   $ # without optee
-   $ make PLAT=imx8mp bl31
+   $ make PLAT=imx8mp BL32_BASE=0x7e000000 SPD=opteed bl31
 
-Build the OP-TEE binary (optional)
-----------------------------------
+Build the OP-TEE binary
+-----------------------
 
 .. code-block:: bash
 
    $ git clone https://github.com/OP-TEE/optee_os.git
    $ cd optee_os
-   $ make CFG_TEE_BENCHMARK=n \
-     CROSS_COMPILE=aarch64-linux-gnu- \
+   $ make CROSS_COMPILE=aarch64-linux-gnu- \
      O=out/arm \
      PLATFORM=imx-mx8mp_phyboard_pollux \
-     CFG_TZDRAM_START=0x56000000
+     CFG_TZDRAM_START=0x7e000000
 
 Get the ddr firmware
 --------------------

From db6487861ae87e07db97b6e5ad0de901c483084c Mon Sep 17 00:00:00 2001
From: Yannic Moog <y.moog@phytec.de>
Date: Thu, 18 Sep 2025 08:13:57 +0200
Subject: [PATCH 15/15] doc: phytec: imx8m: Style and firmware update

Use single make command for compiling blobs and U-Boot.
Update the imx firmware version.

Signed-off-by: Yannic Moog <y.moog@phytec.de>
---
 doc/board/phytec/imx8mm-phygate-tauri-l.rst | 27 ++++++++++------
 doc/board/phytec/phycore-imx8mm.rst         | 28 +++++++++++------
 doc/board/phytec/phycore-imx8mp.rst         | 34 ++++++++++++---------
 3 files changed, 55 insertions(+), 34 deletions(-)

diff --git a/doc/board/phytec/imx8mm-phygate-tauri-l.rst b/doc/board/phytec/imx8mm-phygate-tauri-l.rst
index bc58a141e4f..3a09be7075a 100644
--- a/doc/board/phytec/imx8mm-phygate-tauri-l.rst
+++ b/doc/board/phytec/imx8mm-phygate-tauri-l.rst
@@ -21,9 +21,13 @@ Build the ARM Trusted firmware binary
 
    $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
    $ cd trusted-firmware-a
-   $ export CROSS_COMPILE=aarch64-linux-gnu-
-   $ export IMX_BOOT_UART_BASE=0x30880000
-   $ make PLAT=imx8mm BL32_BASE=0xbe000000 SPD=opteed bl31
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          PLAT=imx8mm \
+          IMX_BOOT_UART_BASE=0x30880000 \
+          BL32_BASE=0xbe000000 \
+          SPD=opteed \
+          bl31
 
 Build the OP-TEE binary
 -----------------------
@@ -32,7 +36,8 @@ Build the OP-TEE binary
 
    $ git clone https://github.com/OP-TEE/optee_os.git
    $ cd optee_os
-   $ make CROSS_COMPILE=aarch64-linux-gnu- \
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
           O=out/arm \
           PLATFORM=imx-mx8mm_phygate_tauri_l
 
@@ -41,9 +46,9 @@ Get the ddr firmware
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.23.bin
-   $ chmod +x firmware-imx-8.23.bin
-   $ ./firmware-imx-8.23.bin
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
+   $ chmod +x firmware-imx-8.28-994fa14.bin
+   $ ./firmware-imx-8.28-994fa14.bin
 
 Build U-Boot for SD card
 ------------------------
@@ -55,15 +60,17 @@ Copy binaries
 
    $ cp <TF-A dir>/build/imx8mm/release/bl31.bin .
    $ cp <OP-TEE dir>/out/arm/core/tee-raw.bin tee.bin
-   $ cp firmware-imx-8.23/firmware/ddr/synopsys/lpddr4*.bin .
+   $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin .
 
 Build U-Boot
 ^^^^^^^^^^^^
 
 .. code-block:: bash
 
-   $ make imx8mm-phygate-tauri-l_defconfig
-   $ make flash.bin
+   $ make -j $(nproc)
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          imx8mm-phygate-tauri-l_defconfig \
+          flash.bin
 
 Flash SD card
 ^^^^^^^^^^^^^
diff --git a/doc/board/phytec/phycore-imx8mm.rst b/doc/board/phytec/phycore-imx8mm.rst
index f8fa420019c..0784154e710 100644
--- a/doc/board/phytec/phycore-imx8mm.rst
+++ b/doc/board/phytec/phycore-imx8mm.rst
@@ -21,9 +21,13 @@ Build the ARM Trusted firmware binary
 
    $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
    $ cd trusted-firmware-a
-   $ export CROSS_COMPILE=aarch64-linux-gnu-
-   $ export IMX_BOOT_UART_BASE=0x30880000
-   $ make PLAT=imx8mm BL32_BASE=0x7e000000 SPD=opteed bl31
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          PLAT=imx8mm \
+          IMX_BOOT_UART_BASE=0x30880000 \
+          BL32_BASE=0x7e000000 \
+          SPD=opteed \
+          bl31
 
 Build the OP-TEE binary
 -----------------------
@@ -32,7 +36,8 @@ Build the OP-TEE binary
 
    $ git clone https://github.com/OP-TEE/optee_os.git
    $ cd optee_os
-   $ make CROSS_COMPILE=aarch64-linux-gnu- \
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
           O=out/arm \
           PLATFORM=imx-mx8mm_phyboard_polis
 
@@ -41,9 +46,9 @@ Get the ddr firmware
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin
-   $ chmod +x firmware-imx-8.19.bin
-   $ ./firmware-imx-8.19.bin
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
+   $ chmod +x firmware-imx-8.28-994fa14.bin
+   $ ./firmware-imx-8.28-994fa14.bin
 
 Build U-Boot for SD card
 ------------------------
@@ -54,15 +59,18 @@ Copy binaries
 .. code-block:: bash
 
    $ cp <TF-A dir>/build/imx8mm/release/bl31.bin .
-   $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin .
+   $ cp <OP-TEE dir>/out/arm/core/tee-raw.bin tee.bin
+   $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin .
 
 Build U-Boot
 ^^^^^^^^^^^^
 
 .. code-block:: bash
 
-   $ make phycore-imx8mm_defconfig
-   $ make flash.bin
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          phycore-imx8mm_defconfig \
+          flash.bin
 
 Flash SD card
 ^^^^^^^^^^^^^
diff --git a/doc/board/phytec/phycore-imx8mp.rst b/doc/board/phytec/phycore-imx8mp.rst
index df087072062..0252cbd0824 100644
--- a/doc/board/phytec/phycore-imx8mp.rst
+++ b/doc/board/phytec/phycore-imx8mp.rst
@@ -3,7 +3,7 @@
 phyCORE-i.MX 8M Plus
 ====================
 
-The phyCORE-i.MX 8M Plus with 2GB of main memory is supported.
+The phyCORE-i.MX 8M Plus with 1,2,4GB of main memory is supported.
 
 Quick Start
 -----------
@@ -21,9 +21,13 @@ Build the ARM Trusted firmware binary
 
    $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
    $ cd trusted-firmware-a
-   $ export CROSS_COMPILE=aarch64-linux-gnu-
-   $ export IMX_BOOT_UART_BASE=0x30860000
-   $ make PLAT=imx8mp BL32_BASE=0x7e000000 SPD=opteed bl31
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          PLAT=imx8mp \
+          IMX_BOOT_UART_BASE=0x30860000 \
+          BL32_BASE=0x7e000000 \
+          SPD=opteed \
+          bl31
 
 Build the OP-TEE binary
 -----------------------
@@ -32,19 +36,19 @@ Build the OP-TEE binary
 
    $ git clone https://github.com/OP-TEE/optee_os.git
    $ cd optee_os
-   $ make CROSS_COMPILE=aarch64-linux-gnu- \
-     O=out/arm \
-     PLATFORM=imx-mx8mp_phyboard_pollux \
-     CFG_TZDRAM_START=0x7e000000
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          O=out/arm \
+          PLATFORM=imx-mx8mp_phyboard_pollux
 
 Get the ddr firmware
 --------------------
 
 .. code-block:: bash
 
-   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.19.bin
-   $ chmod +x firmware-imx-8.19.bin
-   $ ./firmware-imx-8.19.bin
+   $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin
+   $ chmod +x firmware-imx-8.28-994fa14.bin
+   $ ./firmware-imx-8.28-994fa14.bin
 
 Build U-Boot for SD card
 ------------------------
@@ -56,15 +60,17 @@ Copy binaries
 
    $ cp <TF-A dir>/build/imx8mp/release/bl31.bin .
    $ cp <OP-TEE dir>/out/arm/core/tee-raw.bin tee.bin
-   $ cp firmware-imx-8.19/firmware/ddr/synopsys/lpddr4*.bin .
+   $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr4*.bin .
 
 Build U-Boot
 ^^^^^^^^^^^^
 
 .. code-block:: bash
 
-   $ make phycore-imx8mp_defconfig
-   $ make flash.bin
+   $ make -j $(nproc) \
+          CROSS_COMPILE=aarch64-linux-gnu- \
+          phycore-imx8mp_defconfig \
+          flash.bin
 
 Flash SD card
 ^^^^^^^^^^^^^