Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

Add support for UEC to 8568

Browse Source 
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming
2007-08-14 00:14:25 -05:00
committed by Andrew Fleming-AFLEMING
parent c59e4091ff
commit da9d4610d7
15 changed files with 313 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
include/asm-ppc/global_data.h
View File

@@ -71,16 +71,16 @@ typedef struct global_data {
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
#if defined (CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;

20
include/asm-ppc/immap_qe.h
View File

@@ -281,6 +281,17 @@ typedef struct ucc_slow {
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
typedef struct ucc_mii_mng {
u32 miimcfg; /* MII management configuration reg */
u32 miimcom; /* MII management command reg */
u32 miimadd; /* MII management address reg */
u32 miimcon; /* MII management control reg */
u32 miimstat; /* MII management status reg */
u32 miimind; /* MII management indication reg */
u32 ifctl; /* interface control reg */
u32 ifstat; /* interface statux reg */
} __attribute__ ((packed))uec_mii_t;
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
@@ -540,14 +551,21 @@ typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
#if defined(CONFIG_MPC8568)
u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_MPC8568)
#define QE_MURAM_SIZE 0x10000UL
#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL

56
include/configs/MPC8568MDS.h
View File

@@ -28,20 +28,21 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -297,6 +298,7 @@ extern unsigned long get_clock_freq(void);
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
@@ -311,7 +313,7 @@ extern unsigned long get_clock_freq(void);
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x52
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */
#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
@@ -340,6 +342,44 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#ifdef CONFIG_QE
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#ifndef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME "Freescale GETH"
#endif
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_eTSEC_MDIO_BUS
#ifdef CONFIG_eTSEC_MDIO_BUS
#define CONFIG_MIIM_ADDRESS 0xE0024520
#endif
#define CONFIG_UEC_ETH1 /* GETH1 */
#ifdef CONFIG_UEC_ETH1
#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
#define CFG_UEC1_RX_CLK QE_CLK_NONE
#define CFG_UEC1_TX_CLK QE_CLK16
#define CFG_UEC1_ETH_TYPE GIGA_ETH
#define CFG_UEC1_PHY_ADDR 7
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
#ifdef CONFIG_UEC_ETH2
#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
#define CFG_UEC2_RX_CLK QE_CLK_NONE
#define CFG_UEC2_TX_CLK QE_CLK16
#define CFG_UEC2_ETH_TYPE GIGA_ETH
#define CFG_UEC2_PHY_ADDR 1
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
#endif
#endif /* CONFIG_QE */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -348,13 +388,12 @@ extern unsigned long get_clock_freq(void);
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
@@ -460,12 +499,15 @@ extern unsigned long get_clock_freq(void);
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253