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Merge tag 'v2024.01-rc3' into next

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Prepare v2024.01-rc3
This commit is contained in:
Tom Rini
2023-11-20 09:19:50 -05:00
parent 9e4b42267e 24ca49b33a
commit dca7a8958f
595 changed files with 4644 additions and 1404 deletions
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2
arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
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@@ -4,7 +4,7 @@
*
* Clock synthesizer header
*
* Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2016, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __CLK_SYNTHESIZER_H

2
arch/arm/include/asm/arch-am33xx/clock.h
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@@ -4,7 +4,7 @@
*
* clock header
*
* Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _CLOCKS_H_

2
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
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@@ -4,7 +4,7 @@
*
* AM33xx clock define
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _CLOCKS_AM33XX_H_

2
arch/arm/include/asm/arch-am33xx/cpu.h
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@@ -4,7 +4,7 @@
*
* AM33xx specific header file
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _AM33XX_CPU_H

2
arch/arm/include/asm/arch-am33xx/ddr_defs.h
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@@ -4,7 +4,7 @@
*
* ddr specific header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _DDR_DEFS_H

2
arch/arm/include/asm/arch-am33xx/hardware.h
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@@ -4,7 +4,7 @@
*
* hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_H

2
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
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@@ -4,7 +4,7 @@
*
* AM33xx hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM33XX_HARDWARE_AM33XX_H

2
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
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@@ -4,7 +4,7 @@
*
* AM43xx hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __AM43XX_HARDWARE_AM43XX_H

2
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
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@@ -1,7 +1,7 @@
/*
* mmc_host_def.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as

2
arch/arm/include/asm/arch-am33xx/mux.h
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@@ -1,7 +1,7 @@
/*
* mux.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as

2
arch/arm/include/asm/arch-am33xx/mux_am33xx.h
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@@ -1,7 +1,7 @@
/*
* mux_am33xx.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as

2
arch/arm/include/asm/arch-am33xx/mux_am43xx.h
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@@ -2,7 +2,7 @@
/*
* mux_am43xx.h
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _MUX_AM43XX_H_

2
arch/arm/include/asm/arch-am33xx/omap.h
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@@ -2,7 +2,7 @@
/*
* omap.h
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*
* Author:
* Chandan Nath <chandan.nath@ti.com>

2
arch/arm/include/asm/arch-am33xx/sys_proto.h
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@@ -4,7 +4,7 @@
*
* System information header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef _SYS_PROTO_H_

2
arch/arm/include/asm/arch-omap3/emif4.h
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@@ -4,7 +4,7 @@
* Vaibhav Hiremath <hvaibhav@ti.com>
*
* Copyright (C) 2010
* Texas Instruments Incorporated - http://www.ti.com/
* Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _EMIF_H_

2
arch/arm/include/asm/arch-omap4/ehci.h
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@@ -4,7 +4,7 @@
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com
* Author: Govindraj R <govindraj.raja@ti.com>
*/

2
arch/arm/include/asm/arch-omap4/hardware.h
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@@ -4,7 +4,7 @@
*
* hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H

2
arch/arm/include/asm/arch-omap5/ehci.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
* Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*/

2
arch/arm/include/asm/arch-omap5/hardware.h
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@@ -4,7 +4,7 @@
*
* hardware specific header
*
* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2013, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_HARDWARE_H

77
arch/arm/include/asm/arch-rk3066/boot0.h
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@@ -3,6 +3,81 @@
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#include <asm/arch-rockchip/boot_mode.h>
/*
* Execution starts on the instruction following this 4-byte header
* (containing the magic 'RK30'). This magic constant will be written into
* the final image by the rkimage tool, but we need to reserve space for it here.
*/
#ifdef CONFIG_SPL_BUILD
b 1f /* if overwritten, entry-address is at the next word */
1:
#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_EARLYRETURN_TO_BROM)
/*
* Keep track of the re-entries with help of the lr register.
* This binary can be re-used and called from various BROM functions.
* Only when it's called from the part that handles SPI, NAND or EMMC
* hardware it needs to early return to BROM ones.
* In download mode when it handles data on USB OTG and UART0
* this section must be skipped.
*/
ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */
bne reset /* goto reset; */
/*
* Unlike newer Rockchip SoC models the rk3066 BROM code does not have built-in
* support to enter download mode on return to BROM. This binary must check
* the boot mode register for the BOOT_BROM_DOWNLOAD flag and reset if it's set.
* It then returns to BROM to the end of the function that reads boot blocks.
* From there the BROM code goes into a download mode and waits for data
* on USB OTG and UART0.
*/
ldr r2, =BOOT_BROM_DOWNLOAD
ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */
cmp r0, r2 /* BOOT_BROM_DOWNLOAD) { */
bne early_return /* goto early_return; */
/* } else { */
mov r0, #0
str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */
ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
/* } */
early_return:
bx lr /* return to LR in BROM */
SAVE_SP_ADDR:
.word 0
.globl save_boot_params
save_boot_params:
push {r1-r12, lr}
ldr r0, =SAVE_SP_ADDR
str sp, [r0]
b save_boot_params_ret
.globl back_to_bootrom
back_to_bootrom:
ldr r0, =SAVE_SP_ADDR
ldr sp, [r0]
mov r0, #0
pop {r1-r12, pc}
#endif
#if (defined(CONFIG_SPL_BUILD))
/* U-Boot proper of armv7 does not need this */
b reset
#endif
/*
* For armv7, the addr '_start' will be used as vector start address
* and is written to the VBAR register, which needs to aligned to 0x20.
*/
.align(5), 0x0
_start:
ARM_VECTORS
#endif

2
arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h
View File

@@ -130,6 +130,7 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
#define MSTR_DEVICETYPE_LPDDR2 BIT(2)
#define MSTR_DEVICETYPE_LPDDR3 BIT(3)
#define MSTR_DEVICETYPE_DDR4 BIT(4)
#define MSTR_DEVICETYPE_LPDDR4 BIT(5)
#define MSTR_DEVICETYPE_MASK GENMASK(5, 0)
#define MSTR_2TMODE BIT(10)
#define MSTR_BUSWIDTH_FULL (0 << 12)
@@ -154,6 +155,7 @@ struct dram_para {
u32 odt_en;
u32 tpr0;
u32 tpr2;
u32 tpr6;
u32 tpr10;
u32 tpr11;
u32 tpr12;

139
arch/arm/include/asm/arch-sunxi/mmc.h
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@@ -1,139 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007-2011
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Aaron <leafy.myeh@allwinnertech.com>
*
* MMC register definition for allwinner sunxi platform.
*/
#ifndef _SUNXI_MMC_H
#define _SUNXI_MMC_H
#include <linux/types.h>
struct sunxi_mmc {
u32 gctrl; /* 0x00 global control */
u32 clkcr; /* 0x04 clock control */
u32 timeout; /* 0x08 time out */
u32 width; /* 0x0c bus width */
u32 blksz; /* 0x10 block size */
u32 bytecnt; /* 0x14 byte count */
u32 cmd; /* 0x18 command */
u32 arg; /* 0x1c argument */
u32 resp0; /* 0x20 response 0 */
u32 resp1; /* 0x24 response 1 */
u32 resp2; /* 0x28 response 2 */
u32 resp3; /* 0x2c response 3 */
u32 imask; /* 0x30 interrupt mask */
u32 mint; /* 0x34 masked interrupt status */
u32 rint; /* 0x38 raw interrupt status */
u32 status; /* 0x3c status */
u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
u32 funcsel; /* 0x44 function select */
u32 cbcr; /* 0x48 CIU byte count */
u32 bbcr; /* 0x4c BIU byte count */
u32 dbgc; /* 0x50 debug enable */
u32 res0; /* 0x54 reserved */
u32 a12a; /* 0x58 Auto command 12 argument */
u32 ntsr; /* 0x5c New timing set register */
u32 res1[8];
u32 dmac; /* 0x80 internal DMA control */
u32 dlba; /* 0x84 internal DMA descr list base address */
u32 idst; /* 0x88 internal DMA status */
u32 idie; /* 0x8c internal DMA interrupt enable */
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res2[26];
#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
u32 res3[17];
u32 samp_dl;
u32 res4[46];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
SUNXI_MMC_GCTRL_FIFO_RESET|\
SUNXI_MMC_GCTRL_DMA_RESET)
#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
#define SUNXI_MMC_CMD_START (0x1 << 31)
#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
(SUNXI_MMC_RINT_RESP_ERROR | \
SUNXI_MMC_RINT_RESP_CRC_ERROR | \
SUNXI_MMC_RINT_DATA_CRC_ERROR | \
SUNXI_MMC_RINT_RESP_TIMEOUT | \
SUNXI_MMC_RINT_DATA_TIMEOUT | \
SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
SUNXI_MMC_RINT_START_BIT_ERROR | \
SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
(SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
SUNXI_MMC_RINT_DATA_OVER | \
SUNXI_MMC_RINT_COMMAND_DONE | \
SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
#define SUNXI_MMC_STATUS_FIFO_LEVEL(reg) (((reg) >> 17) & 0x3fff)
#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
#define SUNXI_MMC_COMMON_RESET (1 << 18)
#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
#ifndef _ASM_ARCH_MMC_H_
#define _ASM_ARCH_MMC_H_
struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */
#endif /* _ASM_ARCH_MMC_H_ */

20
arch/arm/include/asm/armv8/mmu.h
View File

@@ -49,13 +49,10 @@
#define PTE_TYPE_BLOCK (1 << 0)
#define PTE_TYPE_VALID (1 << 0)
#define PTE_RDONLY BIT(7)
#define PTE_DBM BIT(51)
#define PTE_TABLE_PXN BIT(59)
#define PTE_TABLE_XN BIT(60)
#define PTE_TABLE_AP BIT(61)
#define PTE_TABLE_NS BIT(63)
#define PTE_TABLE_PXN (1UL << 59)
#define PTE_TABLE_XN (1UL << 60)
#define PTE_TABLE_AP (1UL << 61)
#define PTE_TABLE_NS (1UL << 63)
/*
* Block
@@ -102,15 +99,6 @@
#define TCR_TG0_16K (2 << 14)
#define TCR_EPD1_DISABLE (1 << 23)
#define TCR_EL1_HA BIT(39)
#define TCR_EL1_HD BIT(40)
#define TCR_EL2_HA BIT(21)
#define TCR_EL2_HD BIT(22)
#define TCR_EL3_HA BIT(21)
#define TCR_EL3_HD BIT(22)
#define TCR_EL1_RSVD (1U << 31)
#define TCR_EL2_RSVD (1U << 31 | 1 << 23)
#define TCR_EL3_RSVD (1U << 31 | 1 << 23)

2
arch/arm/include/asm/ehci-omap.h
View File

@@ -4,7 +4,7 @@
* Based on LINUX KERNEL
* drivers/usb/host/ehci-omap.c and drivers/mfd/omap-usb-host.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com*
* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com*
* Author: Govindraj R <govindraj.raja@ti.com>
*/

2
arch/arm/include/asm/global_data.h
View File

@@ -52,8 +52,6 @@ struct arch_global_data {
#if defined(CONFIG_ARM64)
unsigned long tlb_fillptr;
unsigned long tlb_emerg;
unsigned int first_block_level;
bool has_hafdbs;
#endif
#endif
#ifdef CFG_SYS_MEM_RESERVE_SECURE

2
arch/arm/include/asm/ti-common/omap_wdt.h
View File

@@ -4,7 +4,7 @@
*
* OMAP Watchdog header file
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
*/
#ifndef __OMAP_WDT_H__