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Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire

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This commit is contained in:
Wolfgang Denk
2008-01-23 14:23:13 +01:00
parent 2468592d79 57a127201e
commit e57ed96bac
85 changed files with 14529 additions and 1438 deletions
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386
include/MCD_dma.h Normal file
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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MCD_API_H
#define _MCD_API_H
/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
#undef MCD_INCLUDE_EU
/* Number of DMA channels */
#define NCHANNELS 16
/* Total number of variants */
#ifdef MCD_INCLUDE_EU
#define NUMOFVARIANTS 6
#else
#define NUMOFVARIANTS 4
#endif
/* Define sizes of the various tables */
#define TASK_TABLE_SIZE (NCHANNELS*32)
#define VAR_TAB_SIZE (128)
#define CONTEXT_SAVE_SIZE (128)
#define FUNCDESC_TAB_SIZE (256)
#ifdef MCD_INCLUDE_EU
#define FUNCDESC_TAB_NUM 16
#else
#define FUNCDESC_TAB_NUM 1
#endif
#ifndef DEFINESONLY
/* Portability typedefs */
#if 1
#include "common.h"
#else
#ifndef s32
typedef int s32;
#endif
#ifndef u32
typedef unsigned int u32;
#endif
#ifndef s16
typedef short s16;
#endif
#ifndef u16
typedef unsigned short u16;
#endif
#ifndef s8
typedef char s8;
#endif
#ifndef u8
typedef unsigned char u8;
#endif
#endif
/*
* These structures represent the internal registers of the
* multi-channel DMA
*/
struct dmaRegs_s {
u32 taskbar; /* task table base address */
u32 currPtr;
u32 endPtr;
u32 varTablePtr;
u16 dma_rsvd0;
u16 ptdControl; /* ptd control */
u32 intPending; /* interrupt pending */
u32 intMask; /* interrupt mask */
u16 taskControl[16]; /* task control */
u8 priority[32]; /* priority */
u32 initiatorMux; /* initiator mux control */
u32 taskSize0; /* task size control 0. */
u32 taskSize1; /* task size control 1. */
u32 dma_rsvd1; /* reserved */
u32 dma_rsvd2; /* reserved */
u32 debugComp1; /* debug comparator 1 */
u32 debugComp2; /* debug comparator 2 */
u32 debugControl; /* debug control */
u32 debugStatus; /* debug status */
u32 ptdDebug; /* priority task decode debug */
u32 dma_rsvd3[31]; /* reserved */
};
typedef volatile struct dmaRegs_s dmaRegs;
#endif
/* PTD contrl reg bits */
#define PTD_CTL_TSK_PRI 0x8000
#define PTD_CTL_COMM_PREFETCH 0x0001
/* Task Control reg bits and field masks */
#define TASK_CTL_EN 0x8000
#define TASK_CTL_VALID 0x4000
#define TASK_CTL_ALWAYS 0x2000
#define TASK_CTL_INIT_MASK 0x1f00
#define TASK_CTL_ASTRT 0x0080
#define TASK_CTL_HIPRITSKEN 0x0040
#define TASK_CTL_HLDINITNUM 0x0020
#define TASK_CTL_ASTSKNUM_MASK 0x000f
/* Priority reg bits and field masks */
#define PRIORITY_HLD 0x80
#define PRIORITY_PRI_MASK 0x07
/* Debug Control reg bits and field masks */
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
#define DBG_CTL_AUTO_ARM 0x00008000
#define DBG_CTL_BREAK 0x00004000
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
#define DBG_CTL_EXT_BREAK 0x00000004
#define DBG_CTL_INT_BREAK 0x00000002
/*
* PTD Debug reg selector addresses
* This reg must be written with a value to show the contents of
* one of the desired internal register.
*/
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
have initiators asserted */
/* General return values */
#define MCD_OK 0
#define MCD_ERROR -1
#define MCD_TABLE_UNALIGNED -2
#define MCD_CHANNEL_INVALID -3
/* MCD_initDma input flags */
#define MCD_RELOC_TASKS 0x00000001
#define MCD_NO_RELOC_TASKS 0x00000000
#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */
/*
* MCD_dmaStatus Status Values for each channel:
* MCD_NO_DMA - No DMA has been requested since reset
* MCD_IDLE - DMA active, but the initiator is currently inactive
* MCD_RUNNING - DMA active, and the initiator is currently active
* MCD_PAUSED - DMA active but it is currently paused
* MCD_HALTED - the most recent DMA has been killed with MCD_killTask()
* MCD_DONE - the most recent DMA has completed
*/
#define MCD_NO_DMA 1
#define MCD_IDLE 2
#define MCD_RUNNING 3
#define MCD_PAUSED 4
#define MCD_HALTED 5
#define MCD_DONE 6
/* MCD_startDma parameter defines */
/* Constants for the funcDesc parameter */
/*
* MCD_NO_BYTE_SWAP - to disable byte swapping
* MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data
* MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data
* value being DMAed
* MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of
* each 32-bit data value DMAed
* MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed
* MCD_BIT_REV - reverse the bits of each byte DMAed
* MCD_CRC16 - to perform CRC-16 on DMAed data
* MCD_CRCCCITT - to perform CRC-CCITT on DMAed data
* MCD_CRC32 - to perform CRC-32 on DMAed data
* MCD_CSUMINET - to perform internet checksums on DMAed data
* MCD_NO_CSUM - to perform no checksumming
*/
#define MCD_NO_BYTE_SWAP 0x00045670
#define MCD_BYTE_REVERSE 0x00076540
#define MCD_U16_REVERSE 0x00067450
#define MCD_U16_BYTE_REVERSE 0x00054760
#define MCD_NO_BIT_REV 0x00000000
#define MCD_BIT_REV 0x00088880
/* CRCing: */
#define MCD_CRC16 0xc0100000
#define MCD_CRCCCITT 0xc0200000
#define MCD_CRC32 0xc0300000
#define MCD_CSUMINET 0xc0400000
#define MCD_NO_CSUM 0xa0000000
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
MCD_NO_CSUM)
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
/* Constants for the flags parameter */
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */
#define MCD_TT_FLAGS_MASK 0x000000ff
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
#define MCD_CHAIN_DMA /* TBD */
#define MCD_EU_DMA /* TBD */
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
/*
* MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl
* MCD_WRAP - to tell the FEC Dmas to wrap to the first BD
* MCD_INTERRUPT - to generate an interrupt after completion of the DMA
* MCD_END_FRAME - tell the DMA to end the frame when transferring
* last byte of data in buffer
* MCD_CRC_RESTART - to empty out the accumulated checksum prior to
* performing the DMA
*/
#define MCD_BUF_READY 0x80000000
#define MCD_WRAP 0x20000000
#define MCD_INTERRUPT 0x10000000
#define MCD_END_FRAME 0x08000000
#define MCD_CRC_RESTART 0x40000000
/* Defines for the FEC buffer descriptor control/status word*/
#define MCD_FEC_BUF_READY 0x8000
#define MCD_FEC_WRAP 0x2000
#define MCD_FEC_INTERRUPT 0x1000
#define MCD_FEC_END_FRAME 0x0800
/* Defines for general intuitiveness */
#define MCD_TRUE 1
#define MCD_FALSE 0
/* Three different cases for destination and source. */
#define MINUS1 -1
#define ZERO 0
#define PLUS1 1
#ifndef DEFINESONLY
/* Task Table Entry struct*/
typedef struct {
u32 TDTstart; /* task descriptor table start */
u32 TDTend; /* task descriptor table end */
u32 varTab; /* variable table start */
u32 FDTandFlags; /* function descriptor table start & flags */
volatile u32 descAddrAndStatus;
volatile u32 modifiedVarTab;
u32 contextSaveSpace; /* context save space start */
u32 literalBases;
} TaskTableEntry;
/* Chained buffer descriptor:
* flags - flags describing the DMA
* csumResult - checksum performed since last checksum reset
* srcAddr - the address to move data from
* destAddr - the address to move data to
* lastDestAddr - the last address written to
* dmaSize - the no of bytes to xfer independent of the xfer sz
* next - next buffer descriptor in chain
* info - private info about this descriptor; DMA does not affect it
*/
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
u32 flags;
u32 csumResult;
s8 *srcAddr;
s8 *destAddr;
s8 *lastDestAddr;
u32 dmaSize;
MCD_bufDesc *next;
u32 info;
};
/* Progress Query struct:
* lastSrcAddr - the most-recent or last, post-increment source address
* lastDestAddr - the most-recent or last, post-increment destination address
* dmaSize - the amount of data transferred for the current buffer
* currBufDesc - pointer to the current buffer descriptor being DMAed
*/
typedef volatile struct MCD_XferProg_struct {
s8 *lastSrcAddr;
s8 *lastDestAddr;
u32 dmaSize;
MCD_bufDesc *currBufDesc;
} MCD_XferProg;
/* FEC buffer descriptor */
typedef volatile struct MCD_bufDescFec_struct {
u16 statCtrl;
u16 length;
u32 dataPointer;
} MCD_bufDescFec;
/*************************************************************************/
/* API function Prototypes - see MCD_dmaApi.c for further notes */
/* MCD_startDma starts a particular kind of DMA:
* srcAddr - the channel on which to run the DMA
* srcIncr - the address to move data from, or buffer-descriptor address
* destAddr - the amount to increment the source address per transfer
* destIncr - the address to move data to
* dmaSize - the amount to increment the destination address per transfer
* xferSize - the number bytes in of each data movement (1, 2, or 4)
* initiator - what device initiates the DMA
* priority - priority of the DMA
* flags - flags describing the DMA
* funcDesc - description of byte swapping, bit swapping, and CRC actions
*/
int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
int priority, u32 flags, u32 funcDesc);
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
* setting up some global settings
*/
int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
int MCD_dmaStatus(int channel);
/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
/*
* MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA.
*/
int MCD_killDma(int channel);
/*
* MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor.
*/
int MCD_continDma(int channel);
/*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel).
*/
int MCD_pauseDma(int channel);
/*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel).
*/
int MCD_resumeDma(int channel);
/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
int MCD_csumQuery(int channel, u32 * csum);
/*
* MCD_getCodeSize provides the packed size required by the microcoded task
* and structures.
*/
int MCD_getCodeSize(void);
/*
* MCD_getVersion provides a pointer to a version string and returns a
* version number.
*/
int MCD_getVersion(char **longVersion);
/* macro for setting a location in the variable table */
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
so I'm avoiding surrounding it with "do {} while(0)" */
#endif /* DEFINESONLY */
#endif /* _MCD_API_H */

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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This file is autogenerated. Do not change */
#define CURRBD 4
#define DCOUNT 6
#define DESTPTR 5
#define SRCPTR 7

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include/MCD_tasksInit.h Normal file
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/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MCD_TSK_INIT_H
#define MCD_TSK_INIT_H 1
/*
* Do not edit!
*/
/* Task 0 */
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 1 */
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
short destIncr, int dmaSize, short xferSizeIncr,
int flags, int *currBD, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 2 */
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 3 */
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
short destIncr, int dmaSize, short xferSizeIncr,
int flags, int *currBD, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 4 */
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
volatile TaskTableEntry * taskTable, int channel);
/* Task 5 */
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
volatile TaskTableEntry * taskTable, int channel);
#endif /* MCD_TSK_INIT_H */

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include/asm-m68k/coldfire/crossbar.h Normal file
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/*
* Cross Bar Switch Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CROSSBAR_H__
#define __CROSSBAR_H__
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
typedef struct xbs {
u32 prs1; /* 0x100 Priority Register Slave 1 */
u32 res1[3]; /* 0x104 - 0F */
u32 crs1; /* 0x110 Control Register Slave 1 */
u32 res2[187]; /* 0x114 - 0x3FF */
u32 prs4; /* 0x400 Priority Register Slave 4 */
u32 res3[3]; /* 0x404 - 0F */
u32 crs4; /* 0x410 Control Register Slave 4 */
u32 res4[123]; /* 0x414 - 0x5FF */
u32 prs6; /* 0x600 Priority Register Slave 6 */
u32 res5[3]; /* 0x604 - 0F */
u32 crs6; /* 0x610 Control Register Slave 6 */
u32 res6[59]; /* 0x614 - 0x6FF */
u32 prs7; /* 0x700 Priority Register Slave 7 */
u32 res7[3]; /* 0x704 - 0F */
u32 crs7; /* 0x710 Control Register Slave 7 */
} xbs_t;
/* Bit definitions and macros for PRS group */
#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
/* Bit definitions and macros for CRS group */
#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
#define XBS_CRS_RO (0x80000000) /* Read Only */
#define XBS_CRS_PCTL_PARK_FIELD (0)
#define XBS_CRS_PCTL_PARK_ON_LAST (1)
#define XBS_CRS_PCTL_PARK_NONE (2)
#define XBS_CRS_PCTL_PARK_CORE (0)
#define XBS_CRS_PCTL_PARK_EDMA (1)
#define XBS_CRS_PCTL_PARK_FEC0 (2)
#define XBS_CRS_PCTL_PARK_FEC1 (3)
#define XBS_CRS_PCTL_PARK_PCI (5)
#define XBS_CRS_PCTL_PARK_USB (6)
#define XBS_CRS_PCTL_PARK_SBF (7)
#endif /* __CROSSBAR_H__ */

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include/asm-m68k/coldfire/dspi.h Normal file
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/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __DSPI_H__
#define __DSPI_H__
/*********************************************************************
* DMA Serial Peripheral Interface (DSPI)
*********************************************************************/
typedef struct dspi {
u32 dmcr;
u8 resv0[0x4];
u32 dtcr;
u32 dctar0;
u32 dctar1;
u32 dctar2;
u32 dctar3;
u32 dctar4;
u32 dctar5;
u32 dctar6;
u32 dctar7;
u32 dsr;
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
} dspi_t;
/* Bit definitions and macros for DMCR */
#define DSPI_DMCR_HALT (0x00000001)
#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
#define DSPI_DMCR_CRXF (0x00000400)
#define DSPI_DMCR_CTXF (0x00000800)
#define DSPI_DMCR_DRXF (0x00001000)
#define DSPI_DMCR_DTXF (0x00002000)
#define DSPI_DMCR_CSIS0 (0x00010000)
#define DSPI_DMCR_CSIS2 (0x00040000)
#define DSPI_DMCR_CSIS3 (0x00080000)
#define DSPI_DMCR_CSIS5 (0x00200000)
#define DSPI_DMCR_ROOE (0x01000000)
#define DSPI_DMCR_PCSSE (0x02000000)
#define DSPI_DMCR_MTFE (0x04000000)
#define DSPI_DMCR_FRZ (0x08000000)
#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
#define DSPI_DMCR_CSCK (0x40000000)
#define DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for DTCR */
#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for DCTAR group */
#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
#define DSPI_DCTAR_LSBFE (0x01000000)
#define DSPI_DCTAR_CPHA (0x02000000)
#define DSPI_DCTAR_CPOL (0x04000000)
#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
#define DSPI_DCTAR_PASC_1CLK (0x00000000)
#define DSPI_DCTAR_PASC_3CLK (0x00100000)
#define DSPI_DCTAR_PASC_5CLK (0x00200000)
#define DSPI_DCTAR_PASC_7CLK (0x00300000)
#define DSPI_DCTAR_PDT_1CLK (0x00000000)
#define DSPI_DCTAR_PDT_3CLK (0x00040000)
#define DSPI_DCTAR_PDT_5CLK (0x00080000)
#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
#define DSPI_DCTAR_PBR_1CLK (0x00000000)
#define DSPI_DCTAR_PBR_3CLK (0x00010000)
#define DSPI_DCTAR_PBR_5CLK (0x00020000)
#define DSPI_DCTAR_PBR_7CLK (0x00030000)
/* Bit definitions and macros for DSR */
#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
#define DSPI_DSR_RFDF (0x00020000)
#define DSPI_DSR_RFOF (0x00080000)
#define DSPI_DSR_TFFF (0x02000000)
#define DSPI_DSR_TFUF (0x08000000)
#define DSPI_DSR_EOQF (0x10000000)
#define DSPI_DSR_TXRXS (0x40000000)
#define DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for DIRSR */
#define DSPI_DIRSR_RFDFS (0x00010000)
#define DSPI_DIRSR_RFDFE (0x00020000)
#define DSPI_DIRSR_RFOFE (0x00080000)
#define DSPI_DIRSR_TFFFS (0x01000000)
#define DSPI_DIRSR_TFFFE (0x02000000)
#define DSPI_DIRSR_TFUFE (0x08000000)
#define DSPI_DIRSR_EOQFE (0x10000000)
#define DSPI_DIRSR_TCFE (0x80000000)
/* Bit definitions and macros for DTFR */
#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
#define DSPI_DTFR_CS0 (0x00010000)
#define DSPI_DTFR_CS2 (0x00040000)
#define DSPI_DTFR_CS3 (0x00080000)
#define DSPI_DTFR_CS5 (0x00200000)
#define DSPI_DTFR_CTCNT (0x04000000)
#define DSPI_DTFR_EOQ (0x08000000)
#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
#define DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for DRFR */
#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
/* Bit definitions and macros for DTFDR group */
#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for DRFDR group */
#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
#endif /* __DSPI_H__ */

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/*
* EDMA Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __EDMA_H__
#define __EDMA_H__
/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/
/* eDMA module registers */
typedef struct edma_ctrl {
u32 cr; /* 0x00 Control Register */
u32 es; /* 0x04 Error Status Register */
u16 res1[3]; /* 0x08 - 0x0D */
u16 erq; /* 0x0E Enable Request Register */
u16 res2[3]; /* 0x10 - 0x15 */
u16 eei; /* 0x16 Enable Error Interrupt Request */
u8 serq; /* 0x18 Set Enable Request */
u8 cerq; /* 0x19 Clear Enable Request */
u8 seei; /* 0x1A Set En Error Interrupt Request */
u8 ceei; /* 0x1B Clear En Error Interrupt Request */
u8 cint; /* 0x1C Clear Interrupt Enable */
u8 cerr; /* 0x1D Clear Error */
u8 ssrt; /* 0x1E Set START Bit */
u8 cdne; /* 0x1F Clear DONE Status Bit */
u16 res3[3]; /* 0x20 - 0x25 */
u16 intr; /* 0x26 Interrupt Request */
u16 res4[3]; /* 0x28 - 0x2D */
u16 err; /* 0x2E Error Register */
u32 res5[52]; /* 0x30 - 0xFF */
u8 dchpri0; /* 0x100 Channel 0 Priority */
u8 dchpri1; /* 0x101 Channel 1 Priority */
u8 dchpri2; /* 0x102 Channel 2 Priority */
u8 dchpri3; /* 0x103 Channel 3 Priority */
u8 dchpri4; /* 0x104 Channel 4 Priority */
u8 dchpri5; /* 0x105 Channel 5 Priority */
u8 dchpri6; /* 0x106 Channel 6 Priority */
u8 dchpri7; /* 0x107 Channel 7 Priority */
u8 dchpri8; /* 0x108 Channel 8 Priority */
u8 dchpri9; /* 0x109 Channel 9 Priority */
u8 dchpri10; /* 0x110 Channel 10 Priority */
u8 dchpri11; /* 0x111 Channel 11 Priority */
u8 dchpri12; /* 0x112 Channel 12 Priority */
u8 dchpri13; /* 0x113 Channel 13 Priority */
u8 dchpri14; /* 0x114 Channel 14 Priority */
u8 dchpri15; /* 0x115 Channel 15 Priority */
} edma_t;
/* TCD - eDMA*/
typedef struct tcd_ctrl {
u32 saddr; /* 0x00 Source Address */
u16 attr; /* 0x04 Transfer Attributes */
u16 soff; /* 0x06 Signed Source Address Offset */
u32 nbytes; /* 0x08 Minor Byte Count */
u32 slast; /* 0x0C Last Source Address Adjustment */
u32 daddr; /* 0x10 Destination address */
u16 citer; /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
u16 doff; /* 0x16 Signed Destination Address Offset */
u32 dlast_sga; /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
u16 biter; /* 0x1C Minor Loop Lnk, Major Loop Cnt */
u16 csr; /* 0x1E Control and Status */
} tcd_st;
typedef struct tcd_multiple {
tcd_st tcd[16];
} tcd_t;
/* Bit definitions and macros for EPPAR */
#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
#define EPORT_EPPAR_LEVEL (0)
#define EPORT_EPPAR_RISING (1)
#define EPORT_EPPAR_FALLING (2)
#define EPORT_EPPAR_BOTH (3)
#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA7_RISING (0x4000)
#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA6_RISING (0x1000)
#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA5_RISING (0x0400)
#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA4_RISING (0x0100)
#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA3_RISING (0x0040)
#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA2_RISING (0x0010)
#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
#define EPORT_EPPAR_EPPA1_RISING (0x0004)
#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
/* Bit definitions and macros for EPDDR */
#define EPORT_EPDDR_EPDD1 (0x02)
#define EPORT_EPDDR_EPDD2 (0x04)
#define EPORT_EPDDR_EPDD3 (0x08)
#define EPORT_EPDDR_EPDD4 (0x10)
#define EPORT_EPDDR_EPDD5 (0x20)
#define EPORT_EPDDR_EPDD6 (0x40)
#define EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for EPIER */
#define EPORT_EPIER_EPIE1 (0x02)
#define EPORT_EPIER_EPIE2 (0x04)
#define EPORT_EPIER_EPIE3 (0x08)
#define EPORT_EPIER_EPIE4 (0x10)
#define EPORT_EPIER_EPIE5 (0x20)
#define EPORT_EPIER_EPIE6 (0x40)
#define EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for EPDR */
#define EPORT_EPDR_EPD1 (0x02)
#define EPORT_EPDR_EPD2 (0x04)
#define EPORT_EPDR_EPD3 (0x08)
#define EPORT_EPDR_EPD4 (0x10)
#define EPORT_EPDR_EPD5 (0x20)
#define EPORT_EPDR_EPD6 (0x40)
#define EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for EPPDR */
#define EPORT_EPPDR_EPPD1 (0x02)
#define EPORT_EPPDR_EPPD2 (0x04)
#define EPORT_EPPDR_EPPD3 (0x08)
#define EPORT_EPPDR_EPPD4 (0x10)
#define EPORT_EPPDR_EPPD5 (0x20)
#define EPORT_EPPDR_EPPD6 (0x40)
#define EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for EPFR */
#define EPORT_EPFR_EPF1 (0x02)
#define EPORT_EPFR_EPF2 (0x04)
#define EPORT_EPFR_EPF3 (0x08)
#define EPORT_EPFR_EPF4 (0x10)
#define EPORT_EPFR_EPF5 (0x20)
#define EPORT_EPFR_EPF6 (0x40)
#define EPORT_EPFR_EPF7 (0x80)
#endif /* __EDMA_H__ */

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/*
* FlexBus Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FLEXBUS_H
#define __FLEXBUS_H
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
u32 csar4; /* Chip-select Address Register */
u32 csmr4; /* Chip-select Mask Register */
u32 cscr4; /* Chip-select Control Register */
u32 csar5; /* Chip-select Address Register */
u32 csmr5; /* Chip-select Mask Register */
u32 cscr5; /* Chip-select Control Register */
} fbcs_t;
/* Bit definitions and macros for CSAR group */
#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for CSMR group */
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#define FBCS_CSMR_WP (0x00000100) /* Write protect */
#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for CSCR group */
#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_32 (0x00000000)
#endif /* __FLEXBUS_H */

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/*
* LCD controller Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __LCDC_H__
#define __LCDC_H__
/* LCD module registers */
typedef struct lcd_ctrl {
u32 ssar; /* 0x00 Screen Start Address Register */
u32 sr; /* 0x04 LCD Size Register */
u32 vpw; /* 0x08 Virtual Page Width Register */
u32 cpr; /* 0x0C Cursor Position Register */
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
u32 pcr; /* 0x18 Panel Configuration Register */
u32 hcr; /* 0x1C Horizontal Configuration Register */
u32 vcr; /* 0x20 Vertical Configuration Register */
u32 por; /* 0x24 Panning Offset Register */
u32 scr; /* 0x28 Sharp Configuration Register */
u32 pccr; /* 0x2C PWM Contrast Control Register */
u32 dcr; /* 0x30 DMA Control Register */
u32 rmcr; /* 0x34 Refresh Mode Control Register */
u32 icr; /* 0x38 Refresh Mode Control Register */
u32 ier; /* 0x3C Interrupt Enable Register */
u32 isr; /* 0x40 Interrupt Status Register */
u32 res[4];
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
u32 gwsr; /* 0x54 Graphic Window Size Register */
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
u32 gwpr; /* 0x60 Graphic Window Position Register */
u32 gwcr; /* 0x64 Graphic Window Control Register */
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
} lcd_t;
typedef struct lcdbg_ctrl {
u32 bglut[255];
} lcdbg_t;
typedef struct lcdgw_ctrl {
u32 gwlut[255];
} lcdgw_t;
/* Bit definitions and macros for LCDC_LSSAR */
#define LCDC_SSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LSR */
#define LCDC_SR_XMAX(x) (((x)&0x0000003F)<<20)
#define LCDC_SR_YMAX(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LVPWR */
#define LCDC_VPWR_VPW(x) (((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LCPR */
#define LCDC_CPR_CC(x) (((x)&0x00000003)<<30)
#define LCDC_CPR_CC_AND (0xC0000000)
#define LCDC_CPR_CC_XOR (0x80000000)
#define LCDC_CPR_CC_OR (0x40000000)
#define LCDC_CPR_CC_TRANSPARENT (0x00000000)
#define LCDC_CPR_OP (0x10000000)
#define LCDC_CPR_CXP(x) (((x)&0x000003FF)<<16)
#define LCDC_CPR_CYP(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LCWHBR */
#define LCDC_CWHBR_BK_EN (0x80000000)
#define LCDC_CWHBR_CW(x) (((x)&0x0000001F)<<24)
#define LCDC_CWHBR_CH(x) (((x)&0x0000001F)<<16)
#define LCDC_CWHBR_BD(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_LCCMR */
#define LCDC_CCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
#define LCDC_CCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
#define LCDC_CCMR_CUR_COL_B(x) ((x)&0x0000003F)
/* Bit definitions and macros for LCDC_LPCR */
#define LCDC_PCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
#define LCDC_PCR_MODE_TFT (0xC0000000)
#define LCDC_PCR_MODE_CSTN (0x40000000)
#define LCDC_PCR_MODE_MONOCHROME (0x00000000)
#define LCDC_PCR_TFT (0x80000000)
#define LCDC_PCR_COLOR (0x40000000)
#define LCDC_PCR_PBSIZ(x) (((x)&0x00000003)<<28)
#define LCDC_PCR_PBSIZ_8 (0x30000000)
#define LCDC_PCR_PBSIZ_4 (0x20000000)
#define LCDC_PCR_PBSIZ_2 (0x10000000)
#define LCDC_PCR_PBSIZ_1 (0x00000000)
#define LCDC_PCR_BPIX(x) (((x)&0x00000007)<<25)
#define LCDC_PCR_BPIX_18bpp (0x0C000000)
#define LCDC_PCR_BPIX_16bpp (0x0A000000)
#define LCDC_PCR_BPIX_12bpp (0x08000000)
#define LCDC_PCR_BPIX_8bpp (0x06000000)
#define LCDC_PCR_BPIX_4bpp (0x04000000)
#define LCDC_PCR_BPIX_2bpp (0x02000000)
#define LCDC_PCR_BPIX_1bpp (0x00000000)
#define LCDC_PCR_PIXPOL (0x01000000)
#define LCDC_PCR_FLM (0x00800000)
#define LCDC_PCR_LPPOL (0x00400000)
#define LCDC_PCR_CLKPOL (0x00200000)
#define LCDC_PCR_OEPOL (0x00100000)
#define LCDC_PCR_SCLKIDLE (0x00080000)
#define LCDC_PCR_ENDSEL (0x00040000)
#define LCDC_PCR_SWAP_SEL (0x00020000)
#define LCDC_PCR_REV_VS (0x00010000)
#define LCDC_PCR_ACDSEL (0x00008000)
#define LCDC_PCR_ACD(x) (((x)&0x0000007F)<<8)
#define LCDC_PCR_SCLKSEL (0x00000080)
#define LCDC_PCR_SHARP (0x00000040)
#define LCDC_PCR_PCD(x) ((x)&0x0000003F)
/* Bit definitions and macros for LCDC_LHCR */
#define LCDC_HCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
#define LCDC_HCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_HCR_H_WAIT_2(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_LVCR */
#define LCDC_VCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
#define LCDC_VCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_VCR_V_WAIT_2(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_SCR */
#define LCDC_SCR_PS_R_DELAY(x) (((x)&0x0000003F) << 26)
#define LCDC_SCR_CLS_R_DELAY(x) (((x)&0x000000FF) << 16)
#define LCDC_SCR_RTG_DELAY(x) (((x)&0x0000000F) << 8)
#define LCDC_SCR_GRAY2(x) (((x)&0x0000000F) << 4)
#define LCDC_SCR_GRAY1(x) ((x)&&0x0000000F)
/* Bit definitions and macros for LCDC_LPCCR */
#define LCDC_PCCR_CLS_HI_WID(x) (((x)&0x000001FF)<<16)
#define LCDC_PCCR_LDMSK (0x00008000)
#define LCDC_PCCR_SCR(x) (((x)&0x00000003)<<9)
#define LCDC_PCCR_SCR_LCDCLK (0x00000400)
#define LCDC_PCCR_SCR_PIXCLK (0x00000200)
#define LCDC_PCCR_SCR_LNPULSE (0x00000000)
#define LCDC_PCCR_CC_EN (0x00000100)
#define LCDC_PCCR_PW(x) ((x)&0x000000FF)
/* Bit definitions and macros for LCDC_LDCR */
#define LCDC_DCR_BURST (0x80000000)
#define LCDC_DCR_HM(x) (((x)&0x0000001F)<<16)
#define LCDC_DCR_TM(x) ((x)&0x0000001F)
/* Bit definitions and macros for LCDC_LRMCR */
#define LCDC_RMCR_SEL_REF (0x00000001)
/* Bit definitions and macros for LCDC_LICR */
#define LCDC_ICR_GW_INT_CON (0x00000010)
#define LCDC_ICR_INTSYN (0x00000004)
#define LCDC_ICR_INTCON (0x00000001)
/* Bit definitions and macros for LCDC_LIER */
#define LCDC_IER_GW_UDR (0x00000080)
#define LCDC_IER_GW_ERR (0x00000040)
#define LCDC_IER_GW_EOF (0x00000020)
#define LCDC_IER_GW_BOF (0x00000010)
#define LCDC_IER_UDR (0x00000008)
#define LCDC_IER_ERR (0x00000004)
#define LCDC_IER_EOF (0x00000002)
#define LCDC_IER_BOF (0x00000001)
/* Bit definitions and macros for LCDC_LGWSAR */
#define LCDC_GWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LGWSR */
#define LCDC_GWSR_GWW(x) (((x)&0x0000003F)<<20)
#define LCDC_GWSR_GWH(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LGWVPWR */
#define LCDC_GWVPWR_GWVPW(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LGWPOR */
#define LCDC_GWPOR_GWPO(x) ((x)&0x0000001F)
/* Bit definitions and macros for LCDC_LGWPR */
#define LCDC_GWPR_GWXP(x) (((x)&0x000003FF)<<16)
#define LCDC_GWPR_GWYP(x) ((x)&0x000003FF)
/* Bit definitions and macros for LCDC_LGWCR */
#define LCDC_GWCR_GWAV(x) (((x)&0x000000FF)<<24)
#define LCDC_GWCR_GWCKE (0x00800000)
#define LCDC_LGWCR_GWE (0x00400000)
#define LCDC_LGWCR_GW_RVS (0x00200000)
#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
#define LCDC_LGWCR_GWCKB(x) ((x)&0x0000003F)
/* Bit definitions and macros for LCDC_LGWDCR */
#define LCDC_LGWDCR_GWBT (0x80000000)
#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
#define LCDC_LGWDCR_GWTM(x) ((x)&0x0000001F)
#endif /* __LCDC_H__ */

175
include/asm-m68k/coldfire/ssi.h Normal file
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@@ -0,0 +1,175 @@
/*
* SSI Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SSI_H__
#define __SSI_H__
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
u32 rx0;
u32 rx1;
u32 cr;
u32 isr;
u32 ier;
u32 tcr;
u32 rcr;
u32 ccr;
u8 resv0[0x4];
u32 fcsr;
u8 resv1[0x8];
u32 acr;
u32 acadd;
u32 acdat;
u32 atag;
u32 tmask;
u32 rmask;
} ssi_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
/* Bit definitions and macros for SSI_CR */
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
#define SSI_CR_SYN (0x00000010)
#define SSI_CR_NET (0x00000008)
#define SSI_CR_RE (0x00000004)
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
/* Bit definitions and macros for SSI_ISR */
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
#define SSI_ISR_RDR1 (0x00008000)
#define SSI_ISR_RDR0 (0x00004000)
#define SSI_ISR_TDE1 (0x00002000)
#define SSI_ISR_TDE0 (0x00001000)
#define SSI_ISR_ROE1 (0x00000800)
#define SSI_ISR_ROE0 (0x00000400)
#define SSI_ISR_TUE1 (0x00000200)
#define SSI_ISR_TUE0 (0x00000100)
#define SSI_ISR_TFS (0x00000080)
#define SSI_ISR_RFS (0x00000040)
#define SSI_ISR_TLS (0x00000020)
#define SSI_ISR_RLS (0x00000010)
#define SSI_ISR_RFF1 (0x00000008)
#define SSI_ISR_RFF0 (0x00000004)
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_IER */
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
#define SSI_IER_TIE (0x00080000)
#define SSI_IER_CMDAU (0x00040000)
#define SSI_IER_CMDU (0x00020000)
#define SSI_IER_RXT (0x00010000)
#define SSI_IER_RDR1 (0x00008000)
#define SSI_IER_RDR0 (0x00004000)
#define SSI_IER_TDE1 (0x00002000)
#define SSI_IER_TDE0 (0x00001000)
#define SSI_IER_ROE1 (0x00000800)
#define SSI_IER_ROE0 (0x00000400)
#define SSI_IER_TUE1 (0x00000200)
#define SSI_IER_TUE0 (0x00000100)
#define SSI_IER_TFS (0x00000080)
#define SSI_IER_RFS (0x00000040)
#define SSI_IER_TLS (0x00000020)
#define SSI_IER_RLS (0x00000010)
#define SSI_IER_RFF1 (0x00000008)
#define SSI_IER_RFF0 (0x00000004)
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_TCR */
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
#define SSI_TCR_TFDIR (0x00000040)
#define SSI_TCR_TXDIR (0x00000020)
#define SSI_TCR_TSHFD (0x00000010)
#define SSI_TCR_TSCKP (0x00000008)
#define SSI_TCR_TFSI (0x00000004)
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
/* Bit definitions and macros for SSI_RCR */
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
#define SSI_RCR_RFEN0 (0x00000080)
#define SSI_RCR_RSHFD (0x00000010)
#define SSI_RCR_RSCKP (0x00000008)
#define SSI_RCR_RFSI (0x00000004)
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
/* Bit definitions and macros for SSI_CCR */
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
#define SSI_CCR_PM(x) ((x)&0x000000FF)
/* Bit definitions and macros for SSI_FCSR */
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
/* Bit definitions and macros for SSI_ACR */
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
/* Bit definitions and macros for SSI_ACADD */
#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
/* Bit definitions and macros for SSI_ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
/* Bit definitions and macros for SSI_ATAG */
#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
#endif /* __SSI_H__ */

145
include/asm-m68k/fec.h
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@@ -39,20 +39,20 @@ typedef struct cpm_buf_desc {
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* Buffer descriptor control/status used by Ethernet receive.
*/
@@ -95,11 +95,8 @@ typedef struct cpm_buf_desc {
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
#ifdef CONFIG_MCFFEC
/*********************************************************************
*
* Fast Ethernet Controller (FEC)
*
*********************************************************************/
/* FEC private information */
struct fec_info_s {
@@ -117,8 +114,10 @@ struct fec_info_s {
uint txIdx;
char *txbuf;
int initialized;
struct fec_info_s *next;
};
#ifdef CONFIG_MCFFEC
/* Register read/write struct */
typedef struct fec {
#ifdef CONFIG_M5272
@@ -254,90 +253,91 @@ typedef struct fec {
u32 ieee_r_fdxfc;
u32 ieee_r_octets_ok;
} fec_t;
#endif /* CONFIG_MCFFEC */
/*********************************************************************
* Fast Ethernet Controller (FEC)
*********************************************************************/
/* Bit definitions and macros for FEC_EIR */
#define FEC_EIR_CLEAR_ALL (0xFFF80000)
#define FEC_EIR_HBERR (0x80000000)
#define FEC_EIR_BABR (0x40000000)
#define FEC_EIR_BABT (0x20000000)
#define FEC_EIR_GRA (0x10000000)
#define FEC_EIR_TXF (0x08000000)
#define FEC_EIR_TXB (0x04000000)
#define FEC_EIR_RXF (0x02000000)
#define FEC_EIR_RXB (0x01000000)
#define FEC_EIR_MII (0x00800000)
#define FEC_EIR_EBERR (0x00400000)
#define FEC_EIR_LC (0x00200000)
#define FEC_EIR_RL (0x00100000)
#define FEC_EIR_UN (0x00080000)
#define FEC_EIR_CLEAR_ALL (0xFFF80000)
#define FEC_EIR_HBERR (0x80000000)
#define FEC_EIR_BABR (0x40000000)
#define FEC_EIR_BABT (0x20000000)
#define FEC_EIR_GRA (0x10000000)
#define FEC_EIR_TXF (0x08000000)
#define FEC_EIR_TXB (0x04000000)
#define FEC_EIR_RXF (0x02000000)
#define FEC_EIR_RXB (0x01000000)
#define FEC_EIR_MII (0x00800000)
#define FEC_EIR_EBERR (0x00400000)
#define FEC_EIR_LC (0x00200000)
#define FEC_EIR_RL (0x00100000)
#define FEC_EIR_UN (0x00080000)
/* Bit definitions and macros for FEC_RDAR */
#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_TDAR */
#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
/* Bit definitions and macros for FEC_ECR */
#define FEC_ECR_ETHER_EN (0x00000002)
#define FEC_ECR_RESET (0x00000001)
#define FEC_ECR_ETHER_EN (0x00000002)
#define FEC_ECR_RESET (0x00000001)
/* Bit definitions and macros for FEC_MMFR */
#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
#define FEC_MMFR_ST_01 (0x40000000)
#define FEC_MMFR_OP_RD (0x20000000)
#define FEC_MMFR_OP_WR (0x10000000)
#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
#define FEC_MMFR_TA_10 (0x00020000)
#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
#define FEC_MMFR_ST_01 (0x40000000)
#define FEC_MMFR_OP_RD (0x20000000)
#define FEC_MMFR_OP_WR (0x10000000)
#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
#define FEC_MMFR_TA_10 (0x00020000)
/* Bit definitions and macros for FEC_MSCR */
#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
/* Bit definitions and macros for FEC_MIBC */
#define FEC_MIBC_MIB_DISABLE (0x80000000)
#define FEC_MIBC_MIB_IDLE (0x40000000)
#define FEC_MIBC_MIB_DISABLE (0x80000000)
#define FEC_MIBC_MIB_IDLE (0x40000000)
/* Bit definitions and macros for FEC_RCR */
#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
#define FEC_RCR_FCE (0x00000020)
#define FEC_RCR_BC_REJ (0x00000010)
#define FEC_RCR_PROM (0x00000008)
#define FEC_RCR_MII_MODE (0x00000004)
#define FEC_RCR_DRT (0x00000002)
#define FEC_RCR_LOOP (0x00000001)
#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
#define FEC_RCR_FCE (0x00000020)
#define FEC_RCR_BC_REJ (0x00000010)
#define FEC_RCR_PROM (0x00000008)
#define FEC_RCR_MII_MODE (0x00000004)
#define FEC_RCR_DRT (0x00000002)
#define FEC_RCR_LOOP (0x00000001)
/* Bit definitions and macros for FEC_TCR */
#define FEC_TCR_RFC_PAUSE (0x00000010)
#define FEC_TCR_TFC_PAUSE (0x00000008)
#define FEC_TCR_FDEN (0x00000004)
#define FEC_TCR_HBC (0x00000002)
#define FEC_TCR_GTS (0x00000001)
#define FEC_TCR_RFC_PAUSE (0x00000010)
#define FEC_TCR_TFC_PAUSE (0x00000008)
#define FEC_TCR_FDEN (0x00000004)
#define FEC_TCR_HBC (0x00000002)
#define FEC_TCR_GTS (0x00000001)
/* Bit definitions and macros for FEC_PAUR */
#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
/* Bit definitions and macros for FEC_OPD */
#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for FEC_TFWR */
#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
#define FEC_TFWR_X_WMRK_64 (0x01)
#define FEC_TFWR_X_WMRK_128 (0x02)
#define FEC_TFWR_X_WMRK_192 (0x03)
#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
#define FEC_TFWR_X_WMRK_64 (0x01)
#define FEC_TFWR_X_WMRK_128 (0x02)
#define FEC_TFWR_X_WMRK_192 (0x03)
/* Bit definitions and macros for FEC_FRBR */
#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_FRSR */
#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
/* Bit definitions and macros for FEC_ERDSR */
#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
@@ -348,8 +348,7 @@ typedef struct fec {
/* Bit definitions and macros for FEC_EMRBR */
#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
#define FEC_RESET_DELAY 100
#define FEC_RX_TOUT 100
#endif /* CONFIG_MCFFEC */
#endif /* fec_h */

176
include/asm-m68k/fsl_mcdmafec.h Normal file
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@@ -0,0 +1,176 @@
/*
* fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef fsl_mcdmafec_h
#define fsl_mcdmafec_h
/* Re-use of the definitions */
#include <asm/fec.h>
typedef struct fecdma {
u32 rsvd0; /* 0x000 */
u32 eir; /* 0x004 */
u32 eimr; /* 0x008 */
u32 rsvd1[6]; /* 0x00C - 0x023 */
u32 ecr; /* 0x024 */
u32 rsvd2[6]; /* 0x028 - 0x03F */
u32 mmfr; /* 0x040 */
u32 mscr; /* 0x044 */
u32 rsvd3[7]; /* 0x048 - 0x063 */
u32 mibc; /* 0x064 */
u32 rsvd4[7]; /* 0x068 - 0x083 */
u32 rcr; /* 0x084 */
u32 rhr; /* 0x088 */
u32 rsvd5[14]; /* 0x08C - 0x0C3 */
u32 tcr; /* 0x0C4 */
u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */
u32 palr; /* 0x0E4 */
u32 paur; /* 0x0E8 */
u32 opd; /* 0x0EC */
u32 rsvd7[10]; /* 0x0F0 - 0x117 */
u32 iaur; /* 0x118 */
u32 ialr; /* 0x11C */
u32 gaur; /* 0x120 */
u32 galr; /* 0x124 */
u32 rsvd8[7]; /* 0x128 - 0x143 */
u32 tfwr; /* 0x144 */
u32 rsvd9[14]; /* 0x148 - 0x17F */
u32 fmc; /* 0x180 */
u32 rfdr; /* 0x184 */
u32 rfsr; /* 0x188 */
u32 rfcr; /* 0x18C */
u32 rlrfp; /* 0x190 */
u32 rlwfp; /* 0x194 */
u32 rfar; /* 0x198 */
u32 rfrp; /* 0x19C */
u32 rfwp; /* 0x1A0 */
u32 tfdr; /* 0x1A4 */
u32 tfsr; /* 0x1A8 */
u32 tfcr; /* 0x1AC */
u32 tlrfp; /* 0x1B0 */
u32 tlwfp; /* 0x1B4 */
u32 tfar; /* 0x1B8 */
u32 tfrp; /* 0x1BC */
u32 tfwp; /* 0x1C0 */
u32 frst; /* 0x1C4 */
u32 ctcwr; /* 0x1C8 */
} fecdma_t;
struct fec_info_dma {
int index;
u32 iobase;
u32 pinmux;
u32 miibase;
int phy_addr;
int dup_spd;
char *phy_name;
int phyname_init;
cbd_t *rxbd; /* Rx BD */
cbd_t *txbd; /* Tx BD */
uint rxIdx;
uint txIdx;
char *txbuf;
int initialized;
struct fec_info_dma *next;
u16 rxTask; /* DMA receive Task Number */
u16 txTask; /* DMA Transmit Task Number */
u16 rxPri; /* DMA Receive Priority */
u16 txPri; /* DMA Transmit Priority */
u16 rxInit; /* DMA Receive Initiator */
u16 txInit; /* DMA Transmit Initiator */
u16 usedTbdIdx; /* next transmit BD to clean */
u16 cleanTbdNum; /* the number of available transmit BDs */
};
/* Bit definitions and macros for IEVENT */
#define FEC_EIR_TXERR (0x00040000)
#define FEC_EIR_RXERR (0x00020000)
#undef FEC_EIR_CLEAR_ALL
#define FEC_EIR_CLEAR_ALL (0xFFFE0000)
/* Bit definitions and macros for R_HASH */
#define FEC_RHASH_FCE_DC (0x80000000)
#define FEC_RHASH_MULTCAST (0x40000000)
#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24)
/* Bit definitions and macros for FEC_TFWR */
#undef FEC_TFWR_X_WMRK
#undef FEC_TFWR_X_WMRK_64
#undef FEC_TFWR_X_WMRK_128
#undef FEC_TFWR_X_WMRK_192
#define FEC_TFWR_X_WMRK(x) ((x)&0x0F)
#define FEC_TFWR_X_WMRK_64 (0x00)
#define FEC_TFWR_X_WMRK_128 (0x01)
#define FEC_TFWR_X_WMRK_192 (0x02)
#define FEC_TFWR_X_WMRK_256 (0x03)
#define FEC_TFWR_X_WMRK_320 (0x04)
#define FEC_TFWR_X_WMRK_384 (0x05)
#define FEC_TFWR_X_WMRK_448 (0x06)
#define FEC_TFWR_X_WMRK_512 (0x07)
#define FEC_TFWR_X_WMRK_576 (0x08)
#define FEC_TFWR_X_WMRK_640 (0x09)
#define FEC_TFWR_X_WMRK_704 (0x0A)
#define FEC_TFWR_X_WMRK_768 (0x0B)
#define FEC_TFWR_X_WMRK_832 (0x0C)
#define FEC_TFWR_X_WMRK_896 (0x0D)
#define FEC_TFWR_X_WMRK_960 (0x0E)
#define FEC_TFWR_X_WMRK_1024 (0x0F)
/* FIFO definitions */
/* Bit definitions and macros for FSTAT */
#define FIFO_STAT_IP (0x80000000)
#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24)
#define FIFO_STAT_FAE (0x00800000)
#define FIFO_STAT_RXW (0x00400000)
#define FIFO_STAT_UF (0x00200000)
#define FIFO_STAT_OF (0x00100000)
#define FIFO_STAT_FR (0x00080000)
#define FIFO_STAT_FULL (0x00040000)
#define FIFO_STAT_ALARM (0x00020000)
#define FIFO_STAT_EMPTY (0x00010000)
/* Bit definitions and macros for FCTRL */
#define FIFO_CTRL_WCTL (0x40000000)
#define FIFO_CTRL_WFR (0x20000000)
#define FIFO_CTRL_FRAME (0x08000000)
#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24)
#define FIFO_CTRL_IPMASK (0x00800000)
#define FIFO_CTRL_FAEMASK (0x00400000)
#define FIFO_CTRL_RXWMASK (0x00200000)
#define FIFO_CTRL_UFMASK (0x00100000)
#define FIFO_CTRL_OFMASK (0x00080000)
int fecpin_setclear(struct eth_device *dev, int setclear);
void mii_init(void);
uint mii_send(uint mii_cmd);
int mii_discover_phy(struct eth_device *dev);
int mcffec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int mcffec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
#endif /* fsl_mcdmafec_h */

3
include/asm-m68k/global_data.h
View File

@@ -53,6 +53,9 @@ typedef struct global_data {
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
unsigned long fb_base; /* Base addr of framebuffer memory */
#endif
#ifdef CONFIG_BOARD_TYPES
unsigned long board_type;
#endif

139
include/asm-m68k/immap.h
View File

@@ -26,6 +26,40 @@
#ifndef __IMMAP_H
#define __IMMAP_H
#ifdef CONFIG_M52277
#include <asm/immap_5227x.h>
#include <asm/m5227x.h>
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x4000))
#define CFG_MCFRTC_BASE (MMAP_RTC)
#ifdef CONFIG_LCD
#define CFG_LCD_BASE (MMAP_LCD)
#endif
/* Timer */
#ifdef CONFIG_MCFTMR
#define CFG_UDELAY_BASE (MMAP_DTMR0)
#define CFG_TMR_BASE (MMAP_DTMR1)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_DTMR1)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT33)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (6)
#define CFG_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
#endif
#ifdef CONFIG_MCFPIT
#define CFG_UDELAY_BASE (MMAP_PIT0)
#define CFG_PIT_BASE (MMAP_PIT1)
#define CFG_PIT_PRESCALE (6)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M52277 */
#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>
@@ -169,7 +203,7 @@
#endif
#endif /* CONFIG_M5282 */
#ifdef CONFIG_M5329
#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>
@@ -197,7 +231,7 @@
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#endif /* CONFIG_M5329 */
#endif /* CONFIG_M5329 && CONFIG_M5373 */
#ifdef CONFIG_M54455
#include <asm/immap_5445x.h>
@@ -232,11 +266,104 @@
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_PCI_BAR0 CFG_SDRAM_BASE
#define CFG_PCI_BAR4 CFG_SDRAM_BASE
#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
#define CFG_PCI_BAR0 (CFG_MBAR)
#define CFG_PCI_BAR5 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR0 (CFG_MBAR)
#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M54455 */
#ifdef CONFIG_M547x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CFG_FEC0_IOBASE (MMAP_FEC0)
#define CFG_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6
#define FEC0_TX_PRIORITY 7
#define FEC0_RX_INIT 16
#define FEC0_TX_INIT 17
#define FEC1_RX_TASK 2
#define FEC1_TX_TASK 3
#define FEC1_RX_PRIORITY 6
#define FEC1_TX_PRIORITY 7
#define FEC1_RX_INIT 30
#define FEC1_TX_INIT 31
#endif
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100))
#ifdef CONFIG_SLTTMR
#define CFG_UDELAY_BASE (MMAP_SLT1)
#define CFG_TMR_BASE (MMAP_SLT0)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_SLT0)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT54)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E)
#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_PCI_BAR0 (0x40000000)
#define CFG_PCI_BAR1 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR0 (CFG_MBAR)
#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M547x */
#ifdef CONFIG_M548x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>
#ifdef CONFIG_FSLDMAFEC
#define CFG_FEC0_IOBASE (MMAP_FEC0)
#define CFG_FEC1_IOBASE (MMAP_FEC1)
#define FEC0_RX_TASK 0
#define FEC0_TX_TASK 1
#define FEC0_RX_PRIORITY 6
#define FEC0_TX_PRIORITY 7
#define FEC0_RX_INIT 16
#define FEC0_TX_INIT 17
#define FEC1_RX_TASK 2
#define FEC1_TX_TASK 3
#define FEC1_RX_PRIORITY 6
#define FEC1_TX_PRIORITY 7
#define FEC1_RX_INIT 30
#define FEC1_TX_INIT 31
#endif
#define CFG_UART_BASE (MMAP_UART0 + (CFG_UART_PORT * 0x100))
/* Timer */
#ifdef CONFIG_SLTTMR
#define CFG_UDELAY_BASE (MMAP_SLT1)
#define CFG_TMR_BASE (MMAP_SLT0)
#define CFG_TMRPND_REG (((volatile int0_t *)(CFG_INTR_BASE))->iprh0)
#define CFG_TMRINTR_NO (INT0_HI_SLT0)
#define CFG_TMRINTR_MASK (INTC_IPRH_INT54)
#define CFG_TMRINTR_PEND (CFG_TMRINTR_MASK)
#define CFG_TMRINTR_PRI (0x1E)
#define CFG_TIMER_PRESCALER (gd->bus_clk / 1000000)
#endif
#define CFG_INTR_BASE (MMAP_INTC0)
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
#define CFG_PCI_BAR0 (CFG_MBAR)
#define CFG_PCI_BAR1 (CFG_SDRAM_BASE)
#define CFG_PCI_TBATR0 (CFG_MBAR)
#define CFG_PCI_TBATR1 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M548x */
#endif /* __IMMAP_H */

343
include/asm-m68k/immap_5227x.h Normal file
View File

@@ -0,0 +1,343 @@
/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_5227X__
#define __IMMAP_5227X__
/* Module Base Addresses */
#define MMAP_SCM1 (CFG_MBAR + 0x00000000)
#define MMAP_XBS (CFG_MBAR + 0x00004000)
#define MMAP_FBCS (CFG_MBAR + 0x00008000)
#define MMAP_CAN (CFG_MBAR + 0x00020000)
#define MMAP_RTC (CFG_MBAR + 0x0003C000)
#define MMAP_SCM2 (CFG_MBAR + 0x00040010)
#define MMAP_SCM3 (CFG_MBAR + 0x00040070)
#define MMAP_EDMA (CFG_MBAR + 0x00044000)
#define MMAP_INTC0 (CFG_MBAR + 0x00048000)
#define MMAP_INTC1 (CFG_MBAR + 0x0004C000)
#define MMAP_IACK (CFG_MBAR + 0x00054000)
#define MMAP_I2C (CFG_MBAR + 0x00058000)
#define MMAP_DSPI (CFG_MBAR + 0x0005C000)
#define MMAP_UART0 (CFG_MBAR + 0x00060000)
#define MMAP_UART1 (CFG_MBAR + 0x00064000)
#define MMAP_UART2 (CFG_MBAR + 0x00068000)
#define MMAP_DTMR0 (CFG_MBAR + 0x00070000)
#define MMAP_DTMR1 (CFG_MBAR + 0x00074000)
#define MMAP_DTMR2 (CFG_MBAR + 0x00078000)
#define MMAP_DTMR3 (CFG_MBAR + 0x0007C000)
#define MMAP_PIT0 (CFG_MBAR + 0x00080000)
#define MMAP_PIT1 (CFG_MBAR + 0x00084000)
#define MMAP_PWM (CFG_MBAR + 0x00090000)
#define MMAP_EPORT (CFG_MBAR + 0x00094000)
#define MMAP_RCM (CFG_MBAR + 0x000A0000)
#define MMAP_CCM (CFG_MBAR + 0x000A0004)
#define MMAP_GPIO (CFG_MBAR + 0x000A4000)
#define MMAP_ADC (CFG_MBAR + 0x000A8000)
#define MMAP_LCD (CFG_MBAR + 0x000AC000)
#define MMAP_LCD_BGLUT (CFG_MBAR + 0x000AC800)
#define MMAP_LCD_GWLUT (CFG_MBAR + 0x000ACC00)
#define MMAP_USBHW (CFG_MBAR + 0x000B0000)
#define MMAP_USBCAPS (CFG_MBAR + 0x000B0100)
#define MMAP_USBEHCI (CFG_MBAR + 0x000B0140)
#define MMAP_USBOTG (CFG_MBAR + 0x000B01A0)
#define MMAP_SDRAM (CFG_MBAR + 0x000B8000)
#define MMAP_SSI (CFG_MBAR + 0x000BC000)
#define MMAP_PLL (CFG_MBAR + 0x000C0000)
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/ssi.h>
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
u32 imrh0; /* 0x08 Mask Register High */
u32 imrl0; /* 0x0C Mask Register Low */
u32 frch0; /* 0x10 Force Register High */
u32 frcl0; /* 0x14 Force Register Low */
u16 res1; /* 0x18 - 0x19 */
u16 icfg0; /* 0x1A Configuration Register */
u8 simr0; /* 0x1C Set Interrupt Mask */
u8 cimr0; /* 0x1D Clear Interrupt Mask */
u8 clmask0; /* 0x1E Current Level Mask */
u8 slmask; /* 0x1F Saved Level Mask */
u32 res2[8]; /* 0x20 - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F Control registers */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 Software Interrupt ack */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 Level n interrupt ack */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 Level n interrupt ack */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC Level n interrupt ack */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 Level n interrupt ack */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 Level n interrupt ack */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 Level n interrupt ack */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC Level n interrupt ack */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct int1_ctrl {
/* Interrupt Controller 1 */
u32 iprh1; /* 0x00 Pending Register High */
u32 iprl1; /* 0x04 Pending Register Low */
u32 imrh1; /* 0x08 Mask Register High */
u32 imrl1; /* 0x0C Mask Register Low */
u32 frch1; /* 0x10 Force Register High */
u32 frcl1; /* 0x14 Force Register Low */
u16 res1; /* 0x18 */
u16 icfg1; /* 0x1A Configuration Register */
u8 simr1; /* 0x1C Set Interrupt Mask */
u8 cimr1; /* 0x1D Clear Interrupt Mask */
u16 res2; /* 0x1E - 0x1F */
u32 res3[8]; /* 0x20 - 0x3F */
u8 icr1[64]; /* 0x40 - 0x7F */
u32 res4[24]; /* 0x80 - 0xDF */
u8 swiack1; /* 0xE0 Software Interrupt ack */
u8 res5[3]; /* 0xE1 - 0xE3 */
u8 Lniack1_1; /* 0xE4 Level n interrupt ack */
u8 res6[3]; /* 0xE5 - 0xE7 */
u8 Lniack1_2; /* 0xE8 Level n interrupt ack */
u8 res7[3]; /* 0xE9 - 0xEB */
u8 Lniack1_3; /* 0xEC Level n interrupt ack */
u8 res8[3]; /* 0xED - 0xEF */
u8 Lniack1_4; /* 0xF0 Level n interrupt ack */
u8 res9[3]; /* 0xF1 - 0xF3 */
u8 Lniack1_5; /* 0xF4 Level n interrupt ack */
u8 resa[3]; /* 0xF5 - 0xF7 */
u8 Lniack1_6; /* 0xF8 Level n interrupt ack */
u8 resb[3]; /* 0xF9 - 0xFB */
u8 Lniack1_7; /* 0xFC Level n interrupt ack */
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
u8 resv1[0x3];
u8 gl1iack;
u8 resv2[0x3];
u8 gl2iack;
u8 resv3[0x3];
u8 gl3iack;
u8 resv4[0x3];
u8 gl4iack;
u8 resv5[0x3];
u8 gl5iack;
u8 resv6[0x3];
u8 gl6iack;
u8 resv7[0x3];
u8 gl7iack;
} iack_t;
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
u8 epier;
u8 epdr;
u8 eppdr;
u8 epfr;
} eport_t;
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u16 ccr; /* Chip Configuration (Rd-only) */
u16 resv1;
u16 rcon; /* Reset Configuration (Rd-only) */
u16 cir; /* Chip Identification (Rd-only) */
u32 resv2;
u16 misccr; /* Miscellaneous Control */
u16 cdr; /* Clock Divider */
u16 uocsr; /* USB On-the-Go Controller Status */
u16 resv4;
u16 sbfsr; /* Serial Boot Status */
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_be; /* 0x00 */
u8 podr_cs; /* 0x01 */
u8 podr_fbctl; /* 0x02 */
u8 podr_i2c; /* 0x03 */
u8 rsvd1; /* 0x04 */
u8 podr_uart; /* 0x05 */
u8 podr_dspi; /* 0x06 */
u8 podr_timer; /* 0x07 */
u8 podr_lcdctl; /* 0x08 */
u8 podr_lcddatah; /* 0x09 */
u8 podr_lcddatam; /* 0x0A */
u8 podr_lcddatal; /* 0x0B */
/* Port Data Direction Registers */
u8 pddr_be; /* 0x0C */
u8 pddr_cs; /* 0x0D */
u8 pddr_fbctl; /* 0x0E */
u8 pddr_i2c; /* 0x0F */
u8 rsvd2; /* 0x10 */
u8 pddr_uart; /* 0x11 */
u8 pddr_dspi; /* 0x12 */
u8 pddr_timer; /* 0x13 */
u8 pddr_lcdctl; /* 0x14 */
u8 pddr_lcddatah; /* 0x15 */
u8 pddr_lcddatam; /* 0x16 */
u8 pddr_lcddatal; /* 0x17 */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_be; /* 0x18 */
u8 ppdsdr_cs; /* 0x19 */
u8 ppdsdr_fbctl; /* 0x1A */
u8 ppdsdr_i2c; /* 0x1B */
u8 rsvd3; /* 0x1C */
u8 ppdsdr_uart; /* 0x1D */
u8 ppdsdr_dspi; /* 0x1E */
u8 ppdsdr_timer; /* 0x1F */
u8 ppdsdr_lcdctl; /* 0x20 */
u8 ppdsdr_lcddatah; /* 0x21 */
u8 ppdsdr_lcddatam; /* 0x22 */
u8 ppdsdr_lcddatal; /* 0x23 */
/* Port Clear Output Data Registers */
u8 pclrr_be; /* 0x24 */
u8 pclrr_cs; /* 0x25 */
u8 pclrr_fbctl; /* 0x26 */
u8 pclrr_i2c; /* 0x27 */
u8 rsvd4; /* 0x28 */
u8 pclrr_uart; /* 0x29 */
u8 pclrr_dspi; /* 0x2A */
u8 pclrr_timer; /* 0x2B */
u8 pclrr_lcdctl; /* 0x2C */
u8 pclrr_lcddatah; /* 0x2D */
u8 pclrr_lcddatam; /* 0x2E */
u8 pclrr_lcddatal; /* 0x2F */
/* Pin Assignment Registers */
u8 par_be; /* 0x30 */
u8 par_cs; /* 0x31 */
u8 par_fbctl; /* 0x32 */
u8 par_i2c; /* 0x33 */
u16 par_uart; /* 0x34 */
u8 par_dspi; /* 0x36 */
u8 par_timer; /* 0x37 */
u8 par_lcdctl; /* 0x38 */
u8 par_irq; /* 0x39 */
u16 rsvd6; /* 0x3A - 0x3B */
u32 par_lcdh; /* 0x3C */
u32 par_lcdl; /* 0x40 */
/* Mode select control registers */
u8 mscr_fb; /* 0x44 */
u8 mscr_sdram; /* 0x45 */
u16 rsvd7; /* 0x46 - 0x47 */
u8 dscr_dspi; /* 0x48 */
u8 dscr_timer; /* 0x49 */
u8 dscr_i2c; /* 0x4A */
u8 dscr_lcd; /* 0x4B */
u8 dscr_debug; /* 0x4C */
u8 dscr_clkrst; /* 0x4D */
u8 dscr_irq; /* 0x4E */
u8 dscr_uart; /* 0x4F */
} gpio_t;
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* Mode/Extended Mode */
u32 sdcr; /* Control */
u32 sdcfg1; /* Configuration 1 */
u32 sdcfg2; /* Chip Select */
u8 resv0[0x100];
u32 sdcs0; /* Mode/Extended Mode */
u32 sdcs1; /* Mode/Extended Mode */
} sdramc_t;
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control */
u32 psr; /* PLL Status */
} pll_t;
/* System Control Module register */
typedef struct scm1 {
u32 mpr; /* 0x00 Master Privilege */
u32 rsvd1[7];
u32 pacra; /* 0x20 */
u32 pacrb; /* 0x24 */
u32 pacrc; /* 0x28 */
u32 pacrd; /* 0x2C */
u32 rsvd2[4];
u32 pacre; /* 0x40 */
u32 pacrf; /* 0x44 */
u32 pacrg; /* 0x48 */
u32 rsvd3;
u32 pacri; /* 0x50 */
} scm1_t;
typedef struct scm2_ctrl {
u8 res1[3]; /* 0x00 - 0x02 */
u8 wcr; /* 0x03 wakeup control */
u16 res2; /* 0x04 - 0x05 */
u16 cwcr; /* 0x06 Core Watchdog Control */
u8 res3[3]; /* 0x08 - 0x0A */
u8 cwsr; /* 0x0B Core Watchdog Service */
u8 res4[2]; /* 0x0C - 0x0D */
u8 scmisr; /* 0x0F Interrupt Status */
u32 res5; /* 0x20 */
u32 bcr; /* 0x24 Burst Configuration */
} scm2_t;
typedef struct scm3_ctrl {
u32 cfadr; /* 0x00 Core Fault Address */
u8 res7; /* 0x04 */
u8 cfier; /* 0x05 Core Fault Interrupt Enable */
u8 cfloc; /* 0x06 Core Fault Location */
u8 cfatr; /* 0x07 Core Fault Attributes */
u32 cfdtr; /* 0x08 Core Fault Data */
} scm3_t;
typedef struct rtcex {
u32 rsvd1[3];
u32 gocu;
u32 gocl;
} rtcex_t;
#endif /* __IMMAP_5227X__ */

282
include/asm-m68k/immap_5329.h
View File

@@ -68,6 +68,12 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/ssi.h>
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
@@ -159,61 +165,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* Cross-Bar Switch Module */
typedef struct xbs_ctrl {
u32 prs1; /* 0x100 Priority Register Slave 1 */
u32 res1[3]; /* 0x104 - 0F */
u32 crs1; /* 0x110 Control Register Slave 1 */
u32 res2[187]; /* 0x114 - 0x3FF */
u32 prs4; /* 0x400 Priority Register Slave 4 */
u32 res3[3]; /* 0x404 - 0F */
u32 crs4; /* 0x410 Control Register Slave 4 */
u32 res4[123]; /* 0x414 - 0x5FF */
u32 prs6; /* 0x600 Priority Register Slave 6 */
u32 res5[3]; /* 0x604 - 0F */
u32 crs6; /* 0x610 Control Register Slave 6 */
u32 res6[59]; /* 0x614 - 0x6FF */
u32 prs7; /* 0x700 Priority Register Slave 7 */
u32 res7[3]; /* 0x704 - 0F */
u32 crs7; /* 0x710 Control Register Slave 7 */
} xbs_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res1;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res2;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res3;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res4;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res5;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
} fbcs_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
@@ -255,64 +206,6 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
/* eDMA module registers */
typedef struct edma_ctrl {
u32 cr; /* 0x00 Control Register */
u32 es; /* 0x04 Error Status Register */
u16 res1[3]; /* 0x08 - 0x0D */
u16 erq; /* 0x0E Enable Request Register */
u16 res2[3]; /* 0x10 - 0x15 */
u16 eei; /* 0x16 Enable Error Interrupt Request */
u8 serq; /* 0x18 Set Enable Request */
u8 cerq; /* 0x19 Clear Enable Request */
u8 seei; /* 0x1A Set Enable Error Interrupt Request */
u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */
u8 cint; /* 0x1C Clear Interrupt Enable Register */
u8 cerr; /* 0x1D Clear Error Register */
u8 ssrt; /* 0x1E Set START Bit Register */
u8 cdne; /* 0x1F Clear DONE Status Bit Register */
u16 res3[3]; /* 0x20 - 0x25 */
u16 intr; /* 0x26 Interrupt Request Register */
u16 res4[3]; /* 0x28 - 0x2D */
u16 err; /* 0x2E Error Register */
u32 res5[52]; /* 0x30 - 0xFF */
u8 dchpri0; /* 0x100 Channel 0 Priority Register */
u8 dchpri1; /* 0x101 Channel 1 Priority Register */
u8 dchpri2; /* 0x102 Channel 2 Priority Register */
u8 dchpri3; /* 0x103 Channel 3 Priority Register */
u8 dchpri4; /* 0x104 Channel 4 Priority Register */
u8 dchpri5; /* 0x105 Channel 5 Priority Register */
u8 dchpri6; /* 0x106 Channel 6 Priority Register */
u8 dchpri7; /* 0x107 Channel 7 Priority Register */
u8 dchpri8; /* 0x108 Channel 8 Priority Register */
u8 dchpri9; /* 0x109 Channel 9 Priority Register */
u8 dchpri10; /* 0x110 Channel 10 Priority Register */
u8 dchpri11; /* 0x111 Channel 11 Priority Register */
u8 dchpri12; /* 0x112 Channel 12 Priority Register */
u8 dchpri13; /* 0x113 Channel 13 Priority Register */
u8 dchpri14; /* 0x114 Channel 14 Priority Register */
u8 dchpri15; /* 0x115 Channel 15 Priority Register */
} edma_t;
/* TCD - eDMA*/
typedef struct tcd_ctrl {
u32 saddr; /* 0x00 Source Address */
u16 attr; /* 0x04 Transfer Attributes */
u16 soff; /* 0x06 Signed Source Address Offset */
u32 nbytes; /* 0x08 Minor Byte Count */
u32 slast; /* 0x0C Last Source Address Adjustment */
u32 daddr; /* 0x10 Destination address */
u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */
u16 doff; /* 0x16 Signed Destination Address Offset */
u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */
u16 csr; /* 0x1E Control and Status */
} tcd_st;
typedef struct tcd_multiple {
tcd_st tcd[16];
} tcd_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
@@ -389,20 +282,6 @@ typedef struct intgack_ctrl1 {
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/*I2C module registers */
typedef struct i2c_ctrl {
u8 adr; /* 0x00 address register */
u8 res1[3]; /* 0x01 - 0x03 */
u8 fdr; /* 0x04 frequency divider register */
u8 res2[3]; /* 0x05 - 0x07 */
u8 cr; /* 0x08 control register */
u8 res3[3]; /* 0x09 - 0x0B */
u8 sr; /* 0x0C status register */
u8 res4[3]; /* 0x0D - 0x0F */
u8 dr; /* 0x10 data register */
u8 res5[3]; /* 0x11 - 0x13 */
} i2c_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
@@ -499,91 +378,133 @@ typedef struct rcm {
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */
#ifdef CONFIG_M5329
u8 podr_fech; /* 0x00 */
u8 podr_fecl; /* 0x01 */
#else
u16 res00; /* 0x00 - 0x01 */
#endif
u8 podr_ssi; /* 0x02 */
u8 podr_busctl; /* 0x03 */
u8 podr_be; /* 0x04 */
u8 podr_cs; /* 0x05 */
u8 podr_pwm; /* 0x06 */
u8 podr_feci2c; /* 0x07 */
u8 res1; /* 0x08 */
u8 res08; /* 0x08 */
u8 podr_uart; /* 0x09 */
u8 podr_qspi; /* 0x0A */
u8 podr_timer; /* 0x0B */
u8 res2; /* 0x0C */
#ifdef CONFIG_M5329
u8 res0C; /* 0x0C */
u8 podr_lcddatah; /* 0x0D */
u8 podr_lcddatam; /* 0x0E */
u8 podr_lcddatal; /* 0x0F */
u8 podr_lcdctlh; /* 0x10 */
u8 podr_lcdctll; /* 0x11 */
#else
u16 res0C; /* 0x0C - 0x0D */
u8 podr_fech; /* 0x0E */
u8 podr_fecl; /* 0x0F */
u16 res10[3]; /* 0x10 - 0x15 */
#endif
/* Port Data Direction Registers */
u16 res3; /* 0x12 - 0x13 */
#ifdef CONFIG_M5329
u16 res12; /* 0x12 - 0x13 */
u8 pddr_fech; /* 0x14 */
u8 pddr_fecl; /* 0x15 */
#endif
u8 pddr_ssi; /* 0x16 */
u8 pddr_busctl; /* 0x17 */
u8 pddr_be; /* 0x18 */
u8 pddr_cs; /* 0x19 */
u8 pddr_pwm; /* 0x1A */
u8 pddr_feci2c; /* 0x1B */
u8 res4; /* 0x1C */
u8 res1C; /* 0x1C */
u8 pddr_uart; /* 0x1D */
u8 pddr_qspi; /* 0x1E */
u8 pddr_timer; /* 0x1F */
u8 res5; /* 0x20 */
#ifdef CONFIG_M5329
u8 res20; /* 0x20 */
u8 pddr_lcddatah; /* 0x21 */
u8 pddr_lcddatam; /* 0x22 */
u8 pddr_lcddatal; /* 0x23 */
u8 pddr_lcdctlh; /* 0x24 */
u8 pddr_lcdctll; /* 0x25 */
u16 res6; /* 0x26 - 0x27 */
u16 res26; /* 0x26 - 0x27 */
#else
u16 res20; /* 0x20 - 0x21 */
u8 pddr_fech; /* 0x22 */
u8 pddr_fecl; /* 0x23 */
u16 res24[3]; /* 0x24 - 0x29 */
#endif
/* Port Data Direction Registers */
#ifdef CONFIG_M5329
u8 ppd_fech; /* 0x28 */
u8 ppd_fecl; /* 0x29 */
#endif
u8 ppd_ssi; /* 0x2A */
u8 ppd_busctl; /* 0x2B */
u8 ppd_be; /* 0x2C */
u8 ppd_cs; /* 0x2D */
u8 ppd_pwm; /* 0x2E */
u8 ppd_feci2c; /* 0x2F */
u8 res7; /* 0x30 */
u8 res30; /* 0x30 */
u8 ppd_uart; /* 0x31 */
u8 ppd_qspi; /* 0x32 */
u8 ppd_timer; /* 0x33 */
u8 res8; /* 0x34 */
#ifdef CONFIG_M5329
u8 res34; /* 0x34 */
u8 ppd_lcddatah; /* 0x35 */
u8 ppd_lcddatam; /* 0x36 */
u8 ppd_lcddatal; /* 0x37 */
u8 ppd_lcdctlh; /* 0x38 */
u8 ppd_lcdctll; /* 0x39 */
u16 res9; /* 0x3A - 0x3B */
u16 res3A; /* 0x3A - 0x3B */
#else
u16 res34; /* 0x34 - 0x35 */
u8 ppd_fech; /* 0x36 */
u8 ppd_fecl; /* 0x37 */
u16 res38[3]; /* 0x38 - 0x3D */
#endif
/* Port Clear Output Data Registers */
u8 pclrr_fech; /* 0x3C */
u8 pclrr_fecl; /* 0x3D */
#ifdef CONFIG_M5329
u8 res3C; /* 0x3C */
u8 pclrr_fech; /* 0x3D */
u8 pclrr_fecl; /* 0x3E */
#else
u8 pclrr_ssi; /* 0x3E */
#endif
u8 pclrr_busctl; /* 0x3F */
u8 pclrr_be; /* 0x40 */
u8 pclrr_cs; /* 0x41 */
u8 pclrr_pwm; /* 0x42 */
u8 pclrr_feci2c; /* 0x43 */
u8 res10; /* 0x44 */
u8 res44; /* 0x44 */
u8 pclrr_uart; /* 0x45 */
u8 pclrr_qspi; /* 0x46 */
u8 pclrr_timer; /* 0x47 */
u8 res11; /* 0x48 */
u8 pclrr_lcddatah; /* 0x49 */
u8 pclrr_lcddatam; /* 0x4A */
u8 pclrr_lcddatal; /* 0x4B */
#ifdef CONFIG_M5329
u8 pclrr_lcddatah; /* 0x48 */
u8 pclrr_lcddatam; /* 0x49 */
u8 pclrr_lcddatal; /* 0x4A */
u8 pclrr_ssi; /* 0x4B */
u8 pclrr_lcdctlh; /* 0x4C */
u8 pclrr_lcdctll; /* 0x4D */
u16 res12; /* 0x4E - 0x4F */
u16 res4E; /* 0x4E - 0x4F */
#else
u16 res48; /* 0x48 - 0x49 */
u8 pclrr_fech; /* 0x4A */
u8 pclrr_fecl; /* 0x4B */
u8 res4C[5]; /* 0x4C - 0x50 */
#endif
/* Pin Assignment Registers */
#ifdef CONFIG_M5329
u8 par_fec; /* 0x50 */
#endif
u8 par_pwm; /* 0x51 */
u8 par_busctl; /* 0x52 */
u8 par_feci2c; /* 0x53 */
@@ -593,15 +514,20 @@ typedef struct gpio_ctrl {
u16 par_uart; /* 0x58 */
u16 par_qspi; /* 0x5A */
u8 par_timer; /* 0x5C */
#ifdef CONFIG_M5329
u8 par_lcddata; /* 0x5D */
u16 par_lcdctl; /* 0x5E */
#else
u8 par_fec; /* 0x5D */
u16 res5E; /* 0x5E - 0x5F */
#endif
u16 par_irq; /* 0x60 */
u16 res16; /* 0x62 - 0x63 */
u16 res62; /* 0x62 - 0x63 */
/* Mode Select Control Registers */
u8 mscr_flexbus; /* 0x64 */
u8 mscr_sdram; /* 0x65 */
u16 res17; /* 0x66 - 0x67 */
u16 res66; /* 0x66 - 0x67 */
/* Drive Strength Control Registers */
u8 dscr_i2c; /* 0x68 */
@@ -611,49 +537,16 @@ typedef struct gpio_ctrl {
u8 dscr_qspi; /* 0x6C */
u8 dscr_timer; /* 0x6D */
u8 dscr_ssi; /* 0x6E */
#ifdef CONFIG_M5329
u8 dscr_lcd; /* 0x6F */
#else
u8 res6F; /* 0x6F */
#endif
u8 dscr_debug; /* 0x70 */
u8 dscr_clkrst; /* 0x71 */
u8 dscr_irq; /* 0x72 */
} gpio_t;
/* LCD module registers */
typedef struct lcd_ctrl {
u32 ssar; /* 0x00 Screen Start Address Register */
u32 sr; /* 0x04 LCD Size Register */
u32 vpw; /* 0x08 Virtual Page Width Register */
u32 cpr; /* 0x0C Cursor Position Register */
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
u32 pcr; /* 0x18 Panel Configuration Register */
u32 hcr; /* 0x1C Horizontal Configuration Register */
u32 vcr; /* 0x20 Vertical Configuration Register */
u32 por; /* 0x24 Panning Offset Register */
u32 scr; /* 0x28 Sharp Configuration Register */
u32 pccr; /* 0x2C PWM Contrast Control Register */
u32 dcr; /* 0x30 DMA Control Register */
u32 rmcr; /* 0x34 Refresh Mode Control Register */
u32 icr; /* 0x38 Refresh Mode Control Register */
u32 ier; /* 0x3C Interrupt Enable Register */
u32 isr; /* 0x40 Interrupt Status Register */
u32 res[4];
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
u32 gwsr; /* 0x54 Graphic Window Size Register */
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
u32 gwpr; /* 0x60 Graphic Window Position Register */
u32 gwcr; /* 0x64 Graphic Window Control Register */
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
} lcd_t;
typedef struct lcdbg_ctrl {
u32 bglut[255];
} lcdbg_t;
typedef struct lcdgw_ctrl {
u32 gwlut[255];
} lcdgw_t;
/* USB OTG module registers */
typedef struct usb_otg {
u32 id; /* 0x000 Identification Register */
@@ -758,29 +651,6 @@ typedef struct sdram_ctrl {
u32 cs1; /* 0x114 Chip Select 1 Configuration */
} sdram_t;
/* Synchronous serial interface */
typedef struct ssi_ctrl {
u32 tx0; /* 0x00 Transmit Data Register 0 */
u32 tx1; /* 0x04 Transmit Data Register 1 */
u32 rx0; /* 0x08 Receive Data Register 0 */
u32 rx1; /* 0x0C Receive Data Register 1 */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 tcr; /* 0x1C Transmit Configuration Register */
u32 rcr; /* 0x20 Receive Configuration Register */
u32 ccr; /* 0x24 Clock Control Register */
u32 res1; /* 0x28 */
u32 fcsr; /* 0x2C FIFO Control/Status Register */
u32 res2[2]; /* 0x30 - 0x37 */
u32 acr; /* 0x38 AC97 Control Register */
u32 acadd; /* 0x3C AC97 Command Address Register */
u32 acdat; /* 0x40 AC97 Command Data Register */
u32 atag; /* 0x44 AC97 Tag Register */
u32 tmask; /* 0x48 Transmit Time Slot Mask Register */
u32 rmask; /* 0x4C Receive Time Slot Mask Register */
} ssi_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u8 podr; /* 0x00 Output Divider Register */

517
include/asm-m68k/immap_5445x.h
View File

@@ -33,6 +33,7 @@
#define MMAP_FEC0 0xFC030000
#define MMAP_FEC1 0xFC034000
#define MMAP_RTC 0xFC03C000
#define MMAP_SCM2 0xFC040000
#define MMAP_EDMA 0xFC044000
#define MMAP_INTC0 0xFC048000
#define MMAP_INTC1 0xFC04C000
@@ -63,11 +64,18 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C4000
#define MMAP_ATA 0x90000000
#define MMAP_USBHW 0xFC0B0000
#define MMAP_USBCAPS 0xFC0B0100
#define MMAP_USBEHCI 0xFC0B0140
#define MMAP_USBOTG 0xFC0B01A0
/*********************************************************************
* ATA
*********************************************************************/
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/ssi.h>
/* ATA */
typedef struct atac {
/* PIO */
u8 toff; /* 0x00 */
@@ -117,379 +125,7 @@ typedef struct atac {
u8 rsvd6[106];
} atac_t;
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
typedef struct xbs {
u8 resv0[0x100];
u32 prs1; /* XBS Priority Register */
u8 resv1[0xC];
u32 crs1; /* XBS Control Register */
u8 resv2[0xEC];
u32 prs2; /* XBS Priority Register */
u8 resv3[0xC];
u32 crs2; /* XBS Control Register */
u8 resv4[0xEC];
u32 prs3; /* XBS Priority Register */
u8 resv5[0xC];
u32 crs3; /* XBS Control Register */
u8 resv6[0xEC];
u32 prs4; /* XBS Priority Register */
u8 resv7[0xC];
u32 crs4; /* XBS Control Register */
u8 resv8[0xEC];
u32 prs5; /* XBS Priority Register */
u8 resv9[0xC];
u32 crs5; /* XBS Control Register */
u8 resv10[0xEC];
u32 prs6; /* XBS Priority Register */
u8 resv11[0xC];
u32 crs6; /* XBS Control Register */
u8 resv12[0xEC];
u32 prs7; /* XBS Priority Register */
u8 resv13[0xC];
u32 crs7; /* XBS Control Register */
} xbs_t;
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
typedef struct fbcs {
u32 csar0; /* Chip-select Address Register */
u32 csmr0; /* Chip-select Mask Register */
u32 cscr0; /* Chip-select Control Register */
u32 csar1; /* Chip-select Address Register */
u32 csmr1; /* Chip-select Mask Register */
u32 cscr1; /* Chip-select Control Register */
u32 csar2; /* Chip-select Address Register */
u32 csmr2; /* Chip-select Mask Register */
u32 cscr2; /* Chip-select Control Register */
u32 csar3; /* Chip-select Address Register */
u32 csmr3; /* Chip-select Mask Register */
u32 cscr3; /* Chip-select Control Register */
} fbcs_t;
/*********************************************************************
* Enhanced DMA (EDMA)
*********************************************************************/
typedef struct edma {
u32 cr;
u32 es;
u8 resv0[0x6];
u16 erq;
u8 resv1[0x6];
u16 eei;
u8 serq;
u8 cerq;
u8 seei;
u8 ceei;
u8 cint;
u8 cerr;
u8 ssrt;
u8 cdne;
u8 resv2[0x6];
u16 intr;
u8 resv3[0x6];
u16 err;
u8 resv4[0xD0];
u8 dchpri0;
u8 dchpri1;
u8 dchpri2;
u8 dchpri3;
u8 dchpri4;
u8 dchpri5;
u8 dchpri6;
u8 dchpri7;
u8 dchpri8;
u8 dchpri9;
u8 dchpri10;
u8 dchpri11;
u8 dchpri12;
u8 dchpri13;
u8 dchpri14;
u8 dchpri15;
u8 resv5[0xEF0];
u32 tcd0_saddr;
u16 tcd0_attr;
u16 tcd0_soff;
u32 tcd0_nbytes;
u32 tcd0_slast;
u32 tcd0_daddr;
union {
u16 tcd0_citer_elink;
u16 tcd0_citer;
};
u16 tcd0_doff;
u32 tcd0_dlast_sga;
union {
u16 tcd0_biter_elink;
u16 tcd0_biter;
};
u16 tcd0_csr;
u32 tcd1_saddr;
u16 tcd1_attr;
u16 tcd1_soff;
u32 tcd1_nbytes;
u32 tcd1_slast;
u32 tcd1_daddr;
union {
u16 tcd1_citer_elink;
u16 tcd1_citer;
};
u16 tcd1_doff;
u32 tcd1_dlast_sga;
union {
u16 tcd1_biter;
u16 tcd1_biter_elink;
};
u16 tcd1_csr;
u32 tcd2_saddr;
u16 tcd2_attr;
u16 tcd2_soff;
u32 tcd2_nbytes;
u32 tcd2_slast;
u32 tcd2_daddr;
union {
u16 tcd2_citer;
u16 tcd2_citer_elink;
};
u16 tcd2_doff;
u32 tcd2_dlast_sga;
union {
u16 tcd2_biter_elink;
u16 tcd2_biter;
};
u16 tcd2_csr;
u32 tcd3_saddr;
u16 tcd3_attr;
u16 tcd3_soff;
u32 tcd3_nbytes;
u32 tcd3_slast;
u32 tcd3_daddr;
union {
u16 tcd3_citer;
u16 tcd3_citer_elink;
};
u16 tcd3_doff;
u32 tcd3_dlast_sga;
union {
u16 tcd3_biter_elink;
u16 tcd3_biter;
};
u16 tcd3_csr;
u32 tcd4_saddr;
u16 tcd4_attr;
u16 tcd4_soff;
u32 tcd4_nbytes;
u32 tcd4_slast;
u32 tcd4_daddr;
union {
u16 tcd4_citer;
u16 tcd4_citer_elink;
};
u16 tcd4_doff;
u32 tcd4_dlast_sga;
union {
u16 tcd4_biter;
u16 tcd4_biter_elink;
};
u16 tcd4_csr;
u32 tcd5_saddr;
u16 tcd5_attr;
u16 tcd5_soff;
u32 tcd5_nbytes;
u32 tcd5_slast;
u32 tcd5_daddr;
union {
u16 tcd5_citer;
u16 tcd5_citer_elink;
};
u16 tcd5_doff;
u32 tcd5_dlast_sga;
union {
u16 tcd5_biter_elink;
u16 tcd5_biter;
};
u16 tcd5_csr;
u32 tcd6_saddr;
u16 tcd6_attr;
u16 tcd6_soff;
u32 tcd6_nbytes;
u32 tcd6_slast;
u32 tcd6_daddr;
union {
u16 tcd6_citer;
u16 tcd6_citer_elink;
};
u16 tcd6_doff;
u32 tcd6_dlast_sga;
union {
u16 tcd6_biter_elink;
u16 tcd6_biter;
};
u16 tcd6_csr;
u32 tcd7_saddr;
u16 tcd7_attr;
u16 tcd7_soff;
u32 tcd7_nbytes;
u32 tcd7_slast;
u32 tcd7_daddr;
union {
u16 tcd7_citer;
u16 tcd7_citer_elink;
};
u16 tcd7_doff;
u32 tcd7_dlast_sga;
union {
u16 tcd7_biter_elink;
u16 tcd7_biter;
};
u16 tcd7_csr;
u32 tcd8_saddr;
u16 tcd8_attr;
u16 tcd8_soff;
u32 tcd8_nbytes;
u32 tcd8_slast;
u32 tcd8_daddr;
union {
u16 tcd8_citer;
u16 tcd8_citer_elink;
};
u16 tcd8_doff;
u32 tcd8_dlast_sga;
union {
u16 tcd8_biter_elink;
u16 tcd8_biter;
};
u16 tcd8_csr;
u32 tcd9_saddr;
u16 tcd9_attr;
u16 tcd9_soff;
u32 tcd9_nbytes;
u32 tcd9_slast;
u32 tcd9_daddr;
union {
u16 tcd9_citer_elink;
u16 tcd9_citer;
};
u16 tcd9_doff;
u32 tcd9_dlast_sga;
union {
u16 tcd9_biter_elink;
u16 tcd9_biter;
};
u16 tcd9_csr;
u32 tcd10_saddr;
u16 tcd10_attr;
u16 tcd10_soff;
u32 tcd10_nbytes;
u32 tcd10_slast;
u32 tcd10_daddr;
union {
u16 tcd10_citer_elink;
u16 tcd10_citer;
};
u16 tcd10_doff;
u32 tcd10_dlast_sga;
union {
u16 tcd10_biter;
u16 tcd10_biter_elink;
};
u16 tcd10_csr;
u32 tcd11_saddr;
u16 tcd11_attr;
u16 tcd11_soff;
u32 tcd11_nbytes;
u32 tcd11_slast;
u32 tcd11_daddr;
union {
u16 tcd11_citer;
u16 tcd11_citer_elink;
};
u16 tcd11_doff;
u32 tcd11_dlast_sga;
union {
u16 tcd11_biter;
u16 tcd11_biter_elink;
};
u16 tcd11_csr;
u32 tcd12_saddr;
u16 tcd12_attr;
u16 tcd12_soff;
u32 tcd12_nbytes;
u32 tcd12_slast;
u32 tcd12_daddr;
union {
u16 tcd12_citer;
u16 tcd12_citer_elink;
};
u16 tcd12_doff;
u32 tcd12_dlast_sga;
union {
u16 tcd12_biter;
u16 tcd12_biter_elink;
};
u16 tcd12_csr;
u32 tcd13_saddr;
u16 tcd13_attr;
u16 tcd13_soff;
u32 tcd13_nbytes;
u32 tcd13_slast;
u32 tcd13_daddr;
union {
u16 tcd13_citer_elink;
u16 tcd13_citer;
};
u16 tcd13_doff;
u32 tcd13_dlast_sga;
union {
u16 tcd13_biter_elink;
u16 tcd13_biter;
};
u16 tcd13_csr;
u32 tcd14_saddr;
u16 tcd14_attr;
u16 tcd14_soff;
u32 tcd14_nbytes;
u32 tcd14_slast;
u32 tcd14_daddr;
union {
u16 tcd14_citer;
u16 tcd14_citer_elink;
};
u16 tcd14_doff;
u32 tcd14_dlast_sga;
union {
u16 tcd14_biter_elink;
u16 tcd14_biter;
};
u16 tcd14_csr;
u32 tcd15_saddr;
u16 tcd15_attr;
u16 tcd15_soff;
u32 tcd15_nbytes;
u32 tcd15_slast;
u32 tcd15_daddr;
union {
u16 tcd15_citer_elink;
u16 tcd15_citer;
};
u16 tcd15_doff;
u32 tcd15_dlast_sga;
union {
u16 tcd15_biter;
u16 tcd15_biter_elink;
};
u16 tcd15_csr;
} edma_t;
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
/* Interrupt Controller (INTC) */
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 Pending Register High */
u32 iprl0; /* 0x04 Pending Register Low */
@@ -558,10 +194,7 @@ typedef struct int1_ctrl {
u8 resc[3]; /* 0xFD - 0xFF */
} int1_t;
/*********************************************************************
* Global Interrupt Acknowledge (IACK)
*********************************************************************/
/* Global Interrupt Acknowledge (IACK) */
typedef struct iack {
u8 resv0[0xE0];
u8 gswiack;
@@ -581,41 +214,7 @@ typedef struct iack {
u8 gl7iack;
} iack_t;
/*********************************************************************
* DMA Serial Peripheral Interface (DSPI)
*********************************************************************/
typedef struct dspi {
u32 dmcr;
u8 resv0[0x4];
u32 dtcr;
u32 dctar0;
u32 dctar1;
u32 dctar2;
u32 dctar3;
u32 dctar4;
u32 dctar5;
u32 dctar6;
u32 dctar7;
u32 dsr;
u32 dirsr;
u32 dtfr;
u32 drfr;
u32 dtfdr0;
u32 dtfdr1;
u32 dtfdr2;
u32 dtfdr3;
u8 resv1[0x30];
u32 drfdr0;
u32 drfdr1;
u32 drfdr2;
u32 drfdr3;
} dspi_t;
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
/* Edge Port Module (EPORT) */
typedef struct eport {
u16 eppar;
u8 epddr;
@@ -625,10 +224,7 @@ typedef struct eport {
u8 epfr;
} eport_t;
/*********************************************************************
* Watchdog Timer Modules (WTM)
*********************************************************************/
/* Watchdog Timer Modules (WTM) */
typedef struct wtm {
u16 wcr;
u16 wmr;
@@ -636,10 +232,7 @@ typedef struct wtm {
u16 wsr;
} wtm_t;
/*********************************************************************
* Serial Boot Facility (SBF)
*********************************************************************/
/* Serial Boot Facility (SBF) */
typedef struct sbf {
u8 resv0[0x18];
u16 sbfsr; /* Serial Boot Facility Status Register */
@@ -647,19 +240,13 @@ typedef struct sbf {
u16 sbfcr; /* Serial Boot Facility Control Register */
} sbf_t;
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Chip Configuration Module (CCM) */
typedef struct ccm {
u8 ccm_resv0[0x4];
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
@@ -672,10 +259,7 @@ typedef struct ccm {
u16 uocsr; /* USB On-the-Go Controller Status Register */
} ccm_t;
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
@@ -803,10 +387,7 @@ typedef struct gpio {
u8 dscr_ata; /* ATA Drive Strength Control Register */
} gpio_t;
/*********************************************************************
* Random Number Generator (RNG)
*********************************************************************/
/* Random Number Generator (RNG) */
typedef struct rng {
u32 rngcr;
u32 rngsr;
@@ -814,10 +395,7 @@ typedef struct rng {
u32 rngout;
} rng_t;
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* SDRAM Controller (SDRAMC) */
typedef struct sdramc {
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
u32 sdcr; /* SDRAM Control Register */
@@ -828,36 +406,7 @@ typedef struct sdramc {
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
} sdramc_t;
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
typedef struct ssi {
u32 tx0;
u32 tx1;
u32 rx0;
u32 rx1;
u32 cr;
u32 isr;
u32 ier;
u32 tcr;
u32 rcr;
u32 ccr;
u8 resv0[0x4];
u32 fcsr;
u8 resv1[0x8];
u32 acr;
u32 acadd;
u32 acdat;
u32 atag;
u32 tmask;
u32 rmask;
} ssi_t;
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
/* Phase Locked Loop (PLL) */
typedef struct pll {
u32 pcr; /* PLL Control Register */
u32 psr; /* PLL Status Register */
@@ -927,7 +476,27 @@ typedef struct scm1 {
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
} scm1_t;
/********************************************************************/
typedef struct scm2 {
u8 rsvd1[19]; /* 0x00 - 0x12 */
u8 wcr; /* 0x13 */
u16 rsvd2; /* 0x14 - 0x15 */
u16 cwcr; /* 0x16 */
u8 rsvd3[3]; /* 0x18 - 0x1A */
u8 cwsr; /* 0x1B */
u8 rsvd4[3]; /* 0x1C - 0x1E */
u8 scmisr; /* 0x1F */
u32 rsvd5; /* 0x20 - 0x23 */
u8 bcr; /* 0x24 */
u8 rsvd6[74]; /* 0x25 - 0x6F */
u32 cfadr; /* 0x70 */
u8 rsvd7; /* 0x74 */
u8 cfier; /* 0x75 */
u8 cfloc; /* 0x76 */
u8 cfatr; /* 0x77 */
u32 rsvd8; /* 0x78 - 0x7B */
u32 cfdtr; /* 0x7C */
} scm2_t;
typedef struct rtcex {
u32 rsvd1[3];

297
include/asm-m68k/immap_547x_8x.h Normal file
View File

@@ -0,0 +1,297 @@
/*
* MCF547x_8x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IMMAP_547x_8x__
#define __IMMAP_547x_8x__
#define MMAP_SIU (CFG_MBAR + 0x00000000)
#define MMAP_SDRAM (CFG_MBAR + 0x00000100)
#define MMAP_XARB (CFG_MBAR + 0x00000240)
#define MMAP_FBCS (CFG_MBAR + 0x00000500)
#define MMAP_INTC0 (CFG_MBAR + 0x00000700)
#define MMAP_GPTMR (CFG_MBAR + 0x00000800)
#define MMAP_SLT0 (CFG_MBAR + 0x00000900)
#define MMAP_SLT1 (CFG_MBAR + 0x00000910)
#define MMAP_GPIO (CFG_MBAR + 0x00000A00)
#define MMAP_PCI (CFG_MBAR + 0x00000B00)
#define MMAP_PCIARB (CFG_MBAR + 0x00000C00)
#define MMAP_EXTDMA (CFG_MBAR + 0x00000D00)
#define MMAP_EPORT (CFG_MBAR + 0x00000F00)
#define MMAP_CTM (CFG_MBAR + 0x00007F00)
#define MMAP_MCDMA (CFG_MBAR + 0x00008000)
#define MMAP_SCPCI (CFG_MBAR + 0x00008400)
#define MMAP_UART0 (CFG_MBAR + 0x00008600)
#define MMAP_UART1 (CFG_MBAR + 0x00008700)
#define MMAP_UART2 (CFG_MBAR + 0x00008800)
#define MMAP_UART3 (CFG_MBAR + 0x00008900)
#define MMAP_DSPI (CFG_MBAR + 0x00008A00)
#define MMAP_I2C (CFG_MBAR + 0x00008F00)
#define MMAP_FEC0 (CFG_MBAR + 0x00009000)
#define MMAP_FEC1 (CFG_MBAR + 0x00009800)
#define MMAP_CAN0 (CFG_MBAR + 0x0000A000)
#define MMAP_CAN1 (CFG_MBAR + 0x0000A800)
#define MMAP_USBD (CFG_MBAR + 0x0000B000)
#define MMAP_SRAM (CFG_MBAR + 0x00010000)
#define MMAP_SRAMCFG (CFG_MBAR + 0x0001FF00)
#define MMAP_SEC (CFG_MBAR + 0x00020000)
#include <asm/coldfire/flexbus.h>
typedef struct siu {
u32 mbar; /* 0x00 */
u32 drv; /* 0x04 */
u32 rsvd1[2]; /* 0x08 - 0x1F */
u32 sbcr; /* 0x10 */
u32 rsvd2[3]; /* 0x14 - 0x1F */
u32 cs0cfg; /* 0x20 */
u32 cs1cfg; /* 0x24 */
u32 cs2cfg; /* 0x28 */
u32 cs3cfg; /* 0x2C */
u32 rsvd3[2]; /* 0x30 - 0x37 */
u32 secsacr; /* 0x38 */
u32 rsvd4[2]; /* 0x3C - 0x43 */
u32 rsr; /* 0x44 */
u32 rsvd5[2]; /* 0x48 - 0x4F */
u32 jtagid; /* 0x50 */
} siu_t;
typedef struct sdram {
u32 mode; /* 0x00 */
u32 ctrl; /* 0x04 */
u32 cfg1; /* 0x08 */
u32 cfg2; /* 0x0c */
} sdram_t;
typedef struct xlb_arb {
u32 cfg; /* 0x240 */
u32 ver; /* 0x244 */
u32 sr; /* 0x248 */
u32 imr; /* 0x24c */
u32 adrcap; /* 0x250 */
u32 sigcap; /* 0x254 */
u32 adrto; /* 0x258 */
u32 datto; /* 0x25c */
u32 busto; /* 0x260 */
u32 prien; /* 0x264 */
u32 pri; /* 0x268 */
} xlbarb_t;
typedef struct int0_ctrl {
u32 iprh0; /* 0x00 */
u32 iprl0; /* 0x04 */
u32 imrh0; /* 0x08 */
u32 imrl0; /* 0x0C */
u32 frch0; /* 0x10 */
u32 frcl0; /* 0x14 */
u8 irlr; /* 0x18 */
u8 iacklpr; /* 0x19 */
u16 res1; /* 0x1A - 0x1B */
u32 res2[9]; /* 0x1C - 0x3F */
u8 icr0[64]; /* 0x40 - 0x7F */
u32 res3[24]; /* 0x80 - 0xDF */
u8 swiack0; /* 0xE0 */
u8 res4[3]; /* 0xE1 - 0xE3 */
u8 Lniack0_1; /* 0xE4 */
u8 res5[3]; /* 0xE5 - 0xE7 */
u8 Lniack0_2; /* 0xE8 */
u8 res6[3]; /* 0xE9 - 0xEB */
u8 Lniack0_3; /* 0xEC */
u8 res7[3]; /* 0xED - 0xEF */
u8 Lniack0_4; /* 0xF0 */
u8 res8[3]; /* 0xF1 - 0xF3 */
u8 Lniack0_5; /* 0xF4 */
u8 res9[3]; /* 0xF5 - 0xF7 */
u8 Lniack0_6; /* 0xF8 */
u8 resa[3]; /* 0xF9 - 0xFB */
u8 Lniack0_7; /* 0xFC */
u8 resb[3]; /* 0xFD - 0xFF */
} int0_t;
typedef struct gptmr {
u8 ocpw;
u8 octict;
u8 ctrl;
u8 mode;
u16 pre; /* Prescale */
u16 cnt;
u16 pwmwidth;
u8 pwmop; /* Output Polarity */
u8 pwmld; /* Immediate Update */
u16 cap; /* Capture internal counter */
u8 ovfpin; /* Ovf and Pin */
u8 intr; /* Interrupts */
} gptmr_t;
typedef struct slt {
u32 tcnt; /* 0x00 */
u32 cr; /* 0x04 */
u32 cnt; /* 0x08 */
u32 sr; /* 0x0C */
} slt_t;
typedef struct gpio {
/* Port Output Data Registers */
u8 podr_fbctl; /*0x00 */
u8 podr_fbcs; /*0x01 */
u8 podr_dma; /*0x02 */
u8 rsvd1; /*0x03 */
u8 podr_fec0h; /*0x04 */
u8 podr_fec0l; /*0x05 */
u8 podr_fec1h; /*0x06 */
u8 podr_fec1l; /*0x07 */
u8 podr_feci2c; /*0x08 */
u8 podr_pcibg; /*0x09 */
u8 podr_pcibr; /*0x0A */
u8 rsvd2; /*0x0B */
u8 podr_psc3psc2; /*0x0C */
u8 podr_psc1psc0; /*0x0D */
u8 podr_dspi; /*0x0E */
u8 rsvd3; /*0x0F */
/* Port Data Direction Registers */
u8 pddr_fbctl; /*0x10 */
u8 pddr_fbcs; /*0x11 */
u8 pddr_dma; /*0x12 */
u8 rsvd4; /*0x13 */
u8 pddr_fec0h; /*0x14 */
u8 pddr_fec0l; /*0x15 */
u8 pddr_fec1h; /*0x16 */
u8 pddr_fec1l; /*0x17 */
u8 pddr_feci2c; /*0x18 */
u8 pddr_pcibg; /*0x19 */
u8 pddr_pcibr; /*0x1A */
u8 rsvd5; /*0x1B */
u8 pddr_psc3psc2; /*0x1C */
u8 pddr_psc1psc0; /*0x1D */
u8 pddr_dspi; /*0x1E */
u8 rsvd6; /*0x1F */
/* Port Pin Data/Set Data Registers */
u8 ppdsdr_fbctl; /*0x20 */
u8 ppdsdr_fbcs; /*0x21 */
u8 ppdsdr_dma; /*0x22 */
u8 rsvd7; /*0x23 */
u8 ppdsdr_fec0h; /*0x24 */
u8 ppdsdr_fec0l; /*0x25 */
u8 ppdsdr_fec1h; /*0x26 */
u8 ppdsdr_fec1l; /*0x27 */
u8 ppdsdr_feci2c; /*0x28 */
u8 ppdsdr_pcibg; /*0x29 */
u8 ppdsdr_pcibr; /*0x2A */
u8 rsvd8; /*0x2B */
u8 ppdsdr_psc3psc2; /*0x2C */
u8 ppdsdr_psc1psc0; /*0x2D */
u8 ppdsdr_dspi; /*0x2E */
u8 rsvd9; /*0x2F */
/* Port Clear Output Data Registers */
u8 pclrr_fbctl; /*0x30 */
u8 pclrr_fbcs; /*0x31 */
u8 pclrr_dma; /*0x32 */
u8 rsvd10; /*0x33 */
u8 pclrr_fec0h; /*0x34 */
u8 pclrr_fec0l; /*0x35 */
u8 pclrr_fec1h; /*0x36 */
u8 pclrr_fec1l; /*0x37 */
u8 pclrr_feci2c; /*0x38 */
u8 pclrr_pcibg; /*0x39 */
u8 pclrr_pcibr; /*0x3A */
u8 rsvd11; /*0x3B */
u8 pclrr_psc3psc2; /*0x3C */
u8 pclrr_psc1psc0; /*0x3D */
u8 pclrr_dspi; /*0x3E */
u8 rsvd12; /*0x3F */
/* Pin Assignment Registers */
u16 par_fbctl; /*0x40 */
u8 par_fbcs; /*0x42 */
u8 par_dma; /*0x43 */
u16 par_feci2cirq; /*0x44 */
u16 rsvd13; /*0x46 */
u16 par_pcibg; /*0x48 */
u16 par_pcibr; /*0x4A */
u8 par_psc3; /*0x4C */
u8 par_psc2; /*0x4D */
u8 par_psc1; /*0x4E */
u8 par_psc0; /*0x4F */
u16 par_dspi; /*0x50 */
u8 par_timer; /*0x52 */
u8 rsvd14; /*0x53 */
} gpio_t;
typedef struct pci {
u32 idr; /* 0x00 Device Id / Vendor Id */
u32 scr; /* 0x04 Status / command */
u32 ccrir; /* 0x08 Class Code / Revision Id */
u32 cr1; /* 0x0c Configuration 1 */
u32 bar0; /* 0x10 Base address register 0 */
u32 bar1; /* 0x14 Base address register 1 */
u32 bar2; /* 0x18 NA */
u32 bar3; /* 0x1c NA */
u32 bar4; /* 0x20 NA */
u32 bar5; /* 0x24 NA */
u32 ccpr; /* 0x28 Cardbus CIS Pointer */
u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */
u32 erbar; /* 0x30 Expansion ROM Base Address */
u32 cpr; /* 0x34 Capabilities Pointer */
u32 rsvd1; /* 0x38 */
u32 cr2; /* 0x3c Configuration 2 */
u32 rsvd2[8]; /* 0x40 - 0x5f */
/* General control / status registers */
u32 gscr; /* 0x60 Global Status / Control */
u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */
u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */
u32 tcr1; /* 0x6c Target Control 1 Register */
u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */
u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */
u32 iw2btar; /* 0x78 NA */
u32 rsvd3; /* 0x7c */
u32 iwcr; /* 0x80 Initiator Window Configuration */
u32 icr; /* 0x84 Initiator Control */
u32 isr; /* 0x88 Initiator Status */
u32 tcr2; /* 0x8c NA */
u32 tbatr0; /* 0x90 NA */
u32 tbatr1; /* 0x94 NA */
u32 tbatr2; /* 0x98 NA */
u32 tbatr3; /* 0x9c NA */
u32 tbatr4; /* 0xa0 NA */
u32 tbatr5; /* 0xa4 NA */
u32 intr; /* 0xa8 NA */
u32 rsvd4[19]; /* 0xac - 0xf7 */
u32 car; /* 0xf8 Configuration Address */
} pci_t;
typedef struct pci_arbiter {
/* Pci Arbiter Registers */
union {
u32 acr; /* Arbiter Control */
u32 asr; /* Arbiter Status */
};
} pciarb_t;
#endif /* __IMMAP_547x_8x__ */

22
include/asm-m68k/io.h
View File

@@ -28,19 +28,13 @@
#include <asm/byteorder.h>
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesirable for some devices.
*/
#define __raw_readb(addr) \
({ u8 __v = (*(volatile u8 *) (addr)); __v; })
#define __raw_readw(addr) \
({ u16 __v = (*(volatile u16 *) (addr)); __v; })
#define __raw_readl(addr) \
({ u32 __v = (*(volatile u32 *) (addr)); __v; })
#define __raw_readb(addr) (*(volatile u8 *)(addr))
#define __raw_readw(addr) (*(volatile u16 *)(addr))
#define __raw_readl(addr) (*(volatile u32 *)(addr))
#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b))
#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w))
#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l))
#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
@@ -245,8 +239,8 @@ typedef unsigned long phys_addr_t;
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
unsigned long flags)
{
return (void *)paddr;
}

796
include/asm-m68k/m5227x.h Normal file
View File

@@ -0,0 +1,796 @@
/*
* MCF5227x Internal Memory Map
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MCF5227X__
#define __MCF5227X__
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EDMA_00 (8)
#define INT0_LO_EDMA_01 (9)
#define INT0_LO_EDMA_02 (10)
#define INT0_LO_EDMA_03 (11)
#define INT0_LO_EDMA_04 (12)
#define INT0_LO_EDMA_05 (13)
#define INT0_LO_EDMA_06 (14)
#define INT0_LO_EDMA_07 (15)
#define INT0_LO_EDMA_08 (16)
#define INT0_LO_EDMA_09 (17)
#define INT0_LO_EDMA_10 (18)
#define INT0_LO_EDMA_11 (19)
#define INT0_LO_EDMA_12 (20)
#define INT0_LO_EDMA_13 (21)
#define INT0_LO_EDMA_14 (22)
#define INT0_LO_EDMA_15 (23)
#define INT0_LO_EDMA_ERR (24)
#define INT0_LO_SCM_CWIC (25)
#define INT0_LO_UART0 (26)
#define INT0_LO_UART1 (27)
#define INT0_LO_UART2 (28)
#define INT0_LO_I2C (30)
#define INT0_LO_DSPI (31)
#define INT0_HI_DTMR0 (32)
#define INT0_HI_DTMR1 (33)
#define INT0_HI_DTMR2 (34)
#define INT0_HI_DTMR3 (35)
#define INT0_HI_SCMIR (62)
#define INT0_HI_RTC_ISR (63)
#define INT1_HI_CAN_BOFFINT (1)
#define INT1_HI_CAN_ERRINT (3)
#define INT1_HI_CAN_BUF0I (4)
#define INT1_HI_CAN_BUF1I (5)
#define INT1_HI_CAN_BUF2I (6)
#define INT1_HI_CAN_BUF3I (7)
#define INT1_HI_CAN_BUF4I (8)
#define INT1_HI_CAN_BUF5I (9)
#define INT1_HI_CAN_BUF6I (10)
#define INT1_HI_CAN_BUF7I (11)
#define INT1_HI_CAN_BUF8I (12)
#define INT1_HI_CAN_BUF9I (13)
#define INT1_HI_CAN_BUF10I (14)
#define INT1_HI_CAN_BUF11I (15)
#define INT1_HI_CAN_BUF12I (16)
#define INT1_HI_CAN_BUF13I (17)
#define INT1_HI_CAN_BUF14I (18)
#define INT1_HI_CAN_BUF15I (19)
#define INT1_HI_PIT0_PIF (43)
#define INT1_HI_PIT1_PIF (44)
#define INT1_HI_USBOTG_STS (47)
#define INT1_HI_SSI_ISR (49)
#define INT1_HI_PWM_INT (50)
#define INT1_HI_LCDC_ISR (51)
#define INT1_HI_CCM_UOCSR (53)
#define INT1_HI_DSPI_EOQF (54)
#define INT1_HI_DSPI_TFFF (55)
#define INT1_HI_DSPI_TCF (56)
#define INT1_HI_DSPI_TFUF (57)
#define INT1_HI_DSPI_RFDF (58)
#define INT1_HI_DSPI_RFOF (59)
#define INT1_HI_DSPI_RFOF_TFUF (60)
#define INT1_HI_TOUCH_ADC (61)
#define INT1_HI_PLL_LOCKS (62)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for IMRH */
#define INTC_IMRH_INT_MASK32 (0x00000001)
#define INTC_IMRH_INT_MASK33 (0x00000002)
#define INTC_IMRH_INT_MASK34 (0x00000004)
#define INTC_IMRH_INT_MASK35 (0x00000008)
#define INTC_IMRH_INT_MASK36 (0x00000010)
#define INTC_IMRH_INT_MASK37 (0x00000020)
#define INTC_IMRH_INT_MASK38 (0x00000040)
#define INTC_IMRH_INT_MASK39 (0x00000080)
#define INTC_IMRH_INT_MASK40 (0x00000100)
#define INTC_IMRH_INT_MASK41 (0x00000200)
#define INTC_IMRH_INT_MASK42 (0x00000400)
#define INTC_IMRH_INT_MASK43 (0x00000800)
#define INTC_IMRH_INT_MASK44 (0x00001000)
#define INTC_IMRH_INT_MASK45 (0x00002000)
#define INTC_IMRH_INT_MASK46 (0x00004000)
#define INTC_IMRH_INT_MASK47 (0x00008000)
#define INTC_IMRH_INT_MASK48 (0x00010000)
#define INTC_IMRH_INT_MASK49 (0x00020000)
#define INTC_IMRH_INT_MASK50 (0x00040000)
#define INTC_IMRH_INT_MASK51 (0x00080000)
#define INTC_IMRH_INT_MASK52 (0x00100000)
#define INTC_IMRH_INT_MASK53 (0x00200000)
#define INTC_IMRH_INT_MASK54 (0x00400000)
#define INTC_IMRH_INT_MASK55 (0x00800000)
#define INTC_IMRH_INT_MASK56 (0x01000000)
#define INTC_IMRH_INT_MASK57 (0x02000000)
#define INTC_IMRH_INT_MASK58 (0x04000000)
#define INTC_IMRH_INT_MASK59 (0x08000000)
#define INTC_IMRH_INT_MASK60 (0x10000000)
#define INTC_IMRH_INT_MASK61 (0x20000000)
#define INTC_IMRH_INT_MASK62 (0x40000000)
#define INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for IMRL */
#define INTC_IMRL_INT_MASK0 (0x00000001)
#define INTC_IMRL_INT_MASK1 (0x00000002)
#define INTC_IMRL_INT_MASK2 (0x00000004)
#define INTC_IMRL_INT_MASK3 (0x00000008)
#define INTC_IMRL_INT_MASK4 (0x00000010)
#define INTC_IMRL_INT_MASK5 (0x00000020)
#define INTC_IMRL_INT_MASK6 (0x00000040)
#define INTC_IMRL_INT_MASK7 (0x00000080)
#define INTC_IMRL_INT_MASK8 (0x00000100)
#define INTC_IMRL_INT_MASK9 (0x00000200)
#define INTC_IMRL_INT_MASK10 (0x00000400)
#define INTC_IMRL_INT_MASK11 (0x00000800)
#define INTC_IMRL_INT_MASK12 (0x00001000)
#define INTC_IMRL_INT_MASK13 (0x00002000)
#define INTC_IMRL_INT_MASK14 (0x00004000)
#define INTC_IMRL_INT_MASK15 (0x00008000)
#define INTC_IMRL_INT_MASK16 (0x00010000)
#define INTC_IMRL_INT_MASK17 (0x00020000)
#define INTC_IMRL_INT_MASK18 (0x00040000)
#define INTC_IMRL_INT_MASK19 (0x00080000)
#define INTC_IMRL_INT_MASK20 (0x00100000)
#define INTC_IMRL_INT_MASK21 (0x00200000)
#define INTC_IMRL_INT_MASK22 (0x00400000)
#define INTC_IMRL_INT_MASK23 (0x00800000)
#define INTC_IMRL_INT_MASK24 (0x01000000)
#define INTC_IMRL_INT_MASK25 (0x02000000)
#define INTC_IMRL_INT_MASK26 (0x04000000)
#define INTC_IMRL_INT_MASK27 (0x08000000)
#define INTC_IMRL_INT_MASK28 (0x10000000)
#define INTC_IMRL_INT_MASK29 (0x20000000)
#define INTC_IMRL_INT_MASK30 (0x40000000)
#define INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for INTFRCH */
#define INTC_INTFRCH_INTFRC32 (0x00000001)
#define INTC_INTFRCH_INTFRC33 (0x00000002)
#define INTC_INTFRCH_INTFRC34 (0x00000004)
#define INTC_INTFRCH_INTFRC35 (0x00000008)
#define INTC_INTFRCH_INTFRC36 (0x00000010)
#define INTC_INTFRCH_INTFRC37 (0x00000020)
#define INTC_INTFRCH_INTFRC38 (0x00000040)
#define INTC_INTFRCH_INTFRC39 (0x00000080)
#define INTC_INTFRCH_INTFRC40 (0x00000100)
#define INTC_INTFRCH_INTFRC41 (0x00000200)
#define INTC_INTFRCH_INTFRC42 (0x00000400)
#define INTC_INTFRCH_INTFRC43 (0x00000800)
#define INTC_INTFRCH_INTFRC44 (0x00001000)
#define INTC_INTFRCH_INTFRC45 (0x00002000)
#define INTC_INTFRCH_INTFRC46 (0x00004000)
#define INTC_INTFRCH_INTFRC47 (0x00008000)
#define INTC_INTFRCH_INTFRC48 (0x00010000)
#define INTC_INTFRCH_INTFRC49 (0x00020000)
#define INTC_INTFRCH_INTFRC50 (0x00040000)
#define INTC_INTFRCH_INTFRC51 (0x00080000)
#define INTC_INTFRCH_INTFRC52 (0x00100000)
#define INTC_INTFRCH_INTFRC53 (0x00200000)
#define INTC_INTFRCH_INTFRC54 (0x00400000)
#define INTC_INTFRCH_INTFRC55 (0x00800000)
#define INTC_INTFRCH_INTFRC56 (0x01000000)
#define INTC_INTFRCH_INTFRC57 (0x02000000)
#define INTC_INTFRCH_INTFRC58 (0x04000000)
#define INTC_INTFRCH_INTFRC59 (0x08000000)
#define INTC_INTFRCH_INTFRC60 (0x10000000)
#define INTC_INTFRCH_INTFRC61 (0x20000000)
#define INTC_INTFRCH_INTFRC62 (0x40000000)
#define INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for INTFRCL */
#define INTC_INTFRCL_INTFRC0 (0x00000001)
#define INTC_INTFRCL_INTFRC1 (0x00000002)
#define INTC_INTFRCL_INTFRC2 (0x00000004)
#define INTC_INTFRCL_INTFRC3 (0x00000008)
#define INTC_INTFRCL_INTFRC4 (0x00000010)
#define INTC_INTFRCL_INTFRC5 (0x00000020)
#define INTC_INTFRCL_INTFRC6 (0x00000040)
#define INTC_INTFRCL_INTFRC7 (0x00000080)
#define INTC_INTFRCL_INTFRC8 (0x00000100)
#define INTC_INTFRCL_INTFRC9 (0x00000200)
#define INTC_INTFRCL_INTFRC10 (0x00000400)
#define INTC_INTFRCL_INTFRC11 (0x00000800)
#define INTC_INTFRCL_INTFRC12 (0x00001000)
#define INTC_INTFRCL_INTFRC13 (0x00002000)
#define INTC_INTFRCL_INTFRC14 (0x00004000)
#define INTC_INTFRCL_INTFRC15 (0x00008000)
#define INTC_INTFRCL_INTFRC16 (0x00010000)
#define INTC_INTFRCL_INTFRC17 (0x00020000)
#define INTC_INTFRCL_INTFRC18 (0x00040000)
#define INTC_INTFRCL_INTFRC19 (0x00080000)
#define INTC_INTFRCL_INTFRC20 (0x00100000)
#define INTC_INTFRCL_INTFRC21 (0x00200000)
#define INTC_INTFRCL_INTFRC22 (0x00400000)
#define INTC_INTFRCL_INTFRC23 (0x00800000)
#define INTC_INTFRCL_INTFRC24 (0x01000000)
#define INTC_INTFRCL_INTFRC25 (0x02000000)
#define INTC_INTFRCL_INTFRC26 (0x04000000)
#define INTC_INTFRCL_INTFRC27 (0x08000000)
#define INTC_INTFRCL_INTFRC28 (0x10000000)
#define INTC_INTFRCL_INTFRC29 (0x20000000)
#define INTC_INTFRCL_INTFRC30 (0x40000000)
#define INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for ICONFIG */
#define INTC_ICONFIG_EMASK (0x0020)
#define INTC_ICONFIG_ELVLPRI1 (0x0200)
#define INTC_ICONFIG_ELVLPRI2 (0x0400)
#define INTC_ICONFIG_ELVLPRI3 (0x0800)
#define INTC_ICONFIG_ELVLPRI4 (0x1000)
#define INTC_ICONFIG_ELVLPRI5 (0x2000)
#define INTC_ICONFIG_ELVLPRI6 (0x4000)
#define INTC_ICONFIG_ELVLPRI7 (0x8000)
/* Bit definitions and macros for SIMR */
#define INTC_SIMR_SIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CIMR */
#define INTC_CIMR_CIMR(x) (((x)&0x7F))
/* Bit definitions and macros for CLMASK */
#define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for SLMASK */
#define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for RSR */
#define RCM_RSR_LOL (0x01)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* Chip Configuration Module (CCM)
*********************************************************************/
/* Bit definitions and macros for CCR */
#define CCM_CCR_DRAMSEL (0x0100)
#define CCM_CCR_CSC_MASK (0xFF3F)
#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
#define CCM_CCR_LIMP (0x0020)
#define CCM_CCR_LOAD (0x0010)
#define CCM_CCR_BOOTPS_MASK (0xFFF3)
#define CCM_CCR_BOOTPS_PS16 (0x0008)
#define CCM_CCR_BOOTPS_PS8 (0x0004)
#define CCM_CCR_BOOTPS_PS32 (0x0000)
#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
/* Bit definitions and macros for RCON */
#define CCM_RCON_CSC_MASK (0xFF3F)
#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
#define CCM_RCON_LIMP (0x0020)
#define CCM_RCON_LOAD (0x0010)
#define CCM_RCON_BOOTPS_MASK (0xFFF3)
#define CCM_RCON_BOOTPS_PS16 (0x0008)
#define CCM_RCON_BOOTPS_PS8 (0x0004)
#define CCM_RCON_BOOTPS_PS32 (0x0000)
#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
/* Bit definitions and macros for CIR */
#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
#define CCM_CIR_PIN_MASK (0xFFC0)
#define CCM_CIR_PRN_MASK (0x003F)
#define CCM_CIR_PIN_MCF52277 (0x0000)
/* Bit definitions and macros for MISCCR */
#define CCM_MISCCR_RTCSRC (0x4000)
#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
#define CCM_MISCCR_BMT_65536 (0)
#define CCM_MISCCR_BMT_32768 (1)
#define CCM_MISCCR_BMT_16384 (2)
#define CCM_MISCCR_BMT_8192 (3)
#define CCM_MISCCR_BMT_4096 (4)
#define CCM_MISCCR_BMT_2048 (5)
#define CCM_MISCCR_BMT_1024 (6)
#define CCM_MISCCR_BMT_512 (7)
#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
/* Bit definitions and macros for CDR */
#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
/* Bit definitions and macros for UOCSR */
#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
#define CCM_UOCSR_SEND (0x0010) /* Session end */
#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
/*********************************************************************
* General Purpose I/O Module (GPIO)
*********************************************************************/
/* Bit definitions and macros for PAR_BE */
#define GPIO_PAR_BE_MASK (0x0F)
#define GPIO_PAR_BE_BE3_BE3 (0x08)
#define GPIO_PAR_BE_BE3_GPIO (0x00)
#define GPIO_PAR_BE_BE2_BE2 (0x04)
#define GPIO_PAR_BE_BE2_GPIO (0x00)
#define GPIO_PAR_BE_BE1_BE1 (0x02)
#define GPIO_PAR_BE_BE1_GPIO (0x00)
#define GPIO_PAR_BE_BE0_BE0 (0x01)
#define GPIO_PAR_BE_BE0_GPIO (0x00)
/* Bit definitions and macros for PAR_CS */
#define GPIO_PAR_CS_CS3 (0x10)
#define GPIO_PAR_CS_CS2 (0x08)
#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
#define GPIO_PAR_CS_CS1_GPIO (0x00)
#define GPIO_PAR_CS_CS0 (0x01)
/* Bit definitions and macros for PAR_FBCTL */
#define GPIO_PAR_FBCTL_OE (0x80)
#define GPIO_PAR_FBCTL_TA (0x40)
#define GPIO_PAR_FBCTL_RW (0x20)
#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
/* Bit definitions and macros for PAR_FECI2C */
#define GPIO_PAR_I2C_SCL_MASK (0xF3)
#define GPIO_PAR_I2C_SCL_SCL (0x0C)
#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
#define GPIO_PAR_I2C_SCL_GPIO (0x00)
#define GPIO_PAR_I2C_SDA_MASK (0xFC)
#define GPIO_PAR_I2C_SDA_SDA (0x03)
#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
#define GPIO_PAR_I2C_SDA_GPIO (0x00)
/* Bit definitions and macros for PAR_UART */
#define GPIO_PAR_UART_U1CTS_MASK (0x3FFF)
#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
#define GPIO_PAR_UART_U1RTS_MASK (0xCFFF)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
#define GPIO_PAR_UART_U1RXD_MASK (0xF3FF)
#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
#define GPIO_PAR_UART_U1TXD_MASK (0xFCFF)
#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
#define GPIO_PAR_UART_U0CTS_MASK (0xFF3F)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
#define GPIO_PAR_UART_U0RTS_MASK (0xFFCF)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
#define GPIO_PAR_UART_U0RXD_MASK (0xFFF3)
#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
#define GPIO_PAR_UART_U0TXD_MASK (0xFFFC)
#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
/* Bit definitions and macros for PAR_DSPI */
#define GPIO_PAR_DSPI_PCS0_MASK (0x3F)
#define GPIO_PAR_DSPI_PCS0_PCS0 (0x80)
#define GPIO_PAR_DSPI_PCS0_U2RTS (0x40)
#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
#define GPIO_PAR_DSPI_SIN_MASK (0xCF)
#define GPIO_PAR_DSPI_SIN_SIN (0x30)
#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
#define GPIO_PAR_DSPI_SOUT_MASK (0xF3)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
#define GPIO_PAR_DSPI_SCK_MASK (0xFC)
#define GPIO_PAR_DSPI_SCK_SCK (0x03)
#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
/* Bit definitions and macros for PAR_TIMER */
#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
/* Bit definitions and macros for GPIO_PAR_LCDCTL */
#define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7)
#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
#define GPIO_PAR_LCDCTL_LSCLK (0x01)
/* Bit definitions and macros for PAR_IRQ */
#define GPIO_PAR_IRQ_IRQ4_MASK (0xF3)
#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
#define GPIO_PAR_IRQ_IRQ1_MASK (0xFC)
#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
/* Bit definitions and macros for GPIO_PAR_LCDH */
#define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF)
#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF)
#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F)
#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF)
#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3)
#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
#define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC)
#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
/* Bit definitions and macros for GPIO_PAR_LCDL */
#define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF)
#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF)
#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF)
#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF)
#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF)
#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF)
#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF)
#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF)
#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF)
#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF)
#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF)
#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
#define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF)
#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
/* Bit definitions and macros for MSCR_FB */
#define GPIO_MSCR_FB_DUPPER_MASK (0xCF)
#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
#define GPIO_MSCR_FB_DUPPER_OD (0x10)
#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
#define GPIO_MSCR_FB_DLOWER_MASK (0xF3)
#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
#define GPIO_MSCR_FB_DLOWER_OD (0x04)
#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
#define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC)
#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
/* Bit definitions and macros for MSCR_SDRAM */
#define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF)
#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
/* Bit definitions and macros for Drive Strength Control */
#define DSCR_LOAD_50PF (0x03)
#define DSCR_LOAD_30PF (0x02)
#define DSCR_LOAD_20PF (0x01)
#define DSCR_LOAD_10PF (0x00)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
/* Bit definitions and macros for SDMR */
#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
#define SDRAMC_SDMR_BK_LMR (0x00000000)
#define SDRAMC_SDMR_BK_LEMR (0x40000000)
/* Bit definitions and macros for SDCR */
#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
/* Bit definitions and macros for SDCFG1 */
#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
/* Bit definitions and macros for SDCFG2 */
#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
/* Bit definitions and macros for SDCS group */
#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
/* Bit definitions and macros for PCR */
#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
#define PLL_PCR_PFDR_MASK (0x000F0000)
#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
/* Bit definitions and macros for PSR */
#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
/********************************************************************/
#endif /* __MCF5227X__ */

286
include/asm-m68k/m5329.h
View File

@@ -1118,6 +1118,7 @@
#define GPIO_PCLRR_LCDCTLL7 (0x80)
/* Bit definitions and macros for GPIO_PAR_FEC */
#ifdef CONFIG_M5329
#define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0)
#define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2)
#define GPIO_PAR_FEC_7W_GPIO (0x00)
@@ -1126,6 +1127,10 @@
#define GPIO_PAR_FEC_MII_GPIO (0x00)
#define GPIO_PAR_FEC_MII_UART (0x01)
#define GPIO_PAR_FEC_MII_FEC (0x03)
#else
#define GPIO_PAR_FEC_7W_FEC (0x08)
#define GPIO_PAR_FEC_MII_FEC (0x02)
#endif
/* Bit definitions and macros for GPIO_PAR_PWM */
#define GPIO_PAR_PWM1(x) (((x)&0x03)<<0)
@@ -1315,168 +1320,6 @@
/* Bit definitions and macros for GPIO_DSCR_IRQ */
#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)
/* not done yet */
/*********************************************************************
* LCD Controller (LCDC)
*********************************************************************/
/* Bit definitions and macros for LCDC_LSSAR */
#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LSR */
#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
/* Bit definitions and macros for LCDC_LVPWR */
#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
/* Bit definitions and macros for LCDC_LCPR */
#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
#define LCDC_LCPR_OP (0x10000000)
#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
#define LCDC_LCPR_CC_TRANSPARENT (0x00000000)
#define LCDC_LCPR_CC_OR (0x40000000)
#define LCDC_LCPR_CC_XOR (0x80000000)
#define LCDC_LCPR_CC_AND (0xC0000000)
#define LCDC_LCPR_OP_ON (0x10000000)
#define LCDC_LCPR_OP_OFF (0x00000000)
/* Bit definitions and macros for LCDC_LCWHBR */
#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
#define LCDC_LCWHBR_BK_EN (0x80000000)
#define LCDC_LCWHBR_BK_EN_ON (0x80000000)
#define LCDC_LCWHBR_BK_EN_OFF (0x00000000)
/* Bit definitions and macros for LCDC_LCCMR */
#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
/* Bit definitions and macros for LCDC_LPCR */
#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
#define LCDC_LPCR_SHARP (0x00000040)
#define LCDC_LPCR_SCLKSEL (0x00000080)
#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
#define LCDC_LPCR_ACDSEL (0x00008000)
#define LCDC_LPCR_REV_VS (0x00010000)
#define LCDC_LPCR_SWAP_SEL (0x00020000)
#define LCDC_LPCR_ENDSEL (0x00040000)
#define LCDC_LPCR_SCLKIDLE (0x00080000)
#define LCDC_LPCR_OEPOL (0x00100000)
#define LCDC_LPCR_CLKPOL (0x00200000)
#define LCDC_LPCR_LPPOL (0x00400000)
#define LCDC_LPCR_FLM (0x00800000)
#define LCDC_LPCR_PIXPOL (0x01000000)
#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
#define LCDC_LPCR_COLOR (0x40000000)
#define LCDC_LPCR_TFT (0x80000000)
#define LCDC_LPCR_MODE_MONOCHROME (0x00000000)
#define LCDC_LPCR_MODE_CSTN (0x40000000)
#define LCDC_LPCR_MODE_TFT (0xC0000000)
#define LCDC_LPCR_PBSIZ_1 (0x00000000)
#define LCDC_LPCR_PBSIZ_2 (0x10000000)
#define LCDC_LPCR_PBSIZ_4 (0x20000000)
#define LCDC_LPCR_PBSIZ_8 (0x30000000)
#define LCDC_LPCR_BPIX_1bpp (0x00000000)
#define LCDC_LPCR_BPIX_2bpp (0x02000000)
#define LCDC_LPCR_BPIX_4bpp (0x04000000)
#define LCDC_LPCR_BPIX_8bpp (0x06000000)
#define LCDC_LPCR_BPIX_12bpp (0x08000000)
#define LCDC_LPCR_BPIX_16bpp (0x0A000000)
#define LCDC_LPCR_BPIX_18bpp (0x0C000000)
#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for LCDC_LHCR */
#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
/* Bit definitions and macros for LCDC_LVCR */
#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
/* Bit definitions and macros for LCDC_LPOR */
#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
/* Bit definitions and macros for LCDC_LPCCR */
#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
#define LCDC_LPCCR_CC_EN (0x00000100)
#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
#define LCDC_LPCCR_LDMSK (0x00008000)
#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
/* Bit definitions and macros for LCDC_LDCR */
#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
#define LCDC_LDCR_BURST (0x80000000)
/* Bit definitions and macros for LCDC_LRMCR */
#define LCDC_LRMCR_SEL_REF (0x00000001)
/* Bit definitions and macros for LCDC_LICR */
#define LCDC_LICR_INTCON (0x00000001)
#define LCDC_LICR_INTSYN (0x00000004)
#define LCDC_LICR_GW_INT_CON (0x00000010)
/* Bit definitions and macros for LCDC_LIER */
#define LCDC_LIER_BOF_EN (0x00000001)
#define LCDC_LIER_EOF_EN (0x00000002)
#define LCDC_LIER_ERR_RES_EN (0x00000004)
#define LCDC_LIER_UDR_ERR_EN (0x00000008)
#define LCDC_LIER_GW_BOF_EN (0x00000010)
#define LCDC_LIER_GW_EOF_EN (0x00000020)
#define LCDC_LIER_GW_ERR_RES_EN (0x00000040)
#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
/* Bit definitions and macros for LCDC_LISR */
#define LCDC_LISR_BOF (0x00000001)
#define LCDC_LISR_EOF (0x00000002)
#define LCDC_LISR_ERR_RES (0x00000004)
#define LCDC_LISR_UDR_ERR (0x00000008)
#define LCDC_LISR_GW_BOF (0x00000010)
#define LCDC_LISR_GW_EOF (0x00000020)
#define LCDC_LISR_GW_ERR_RES (0x00000040)
#define LCDC_LISR_GW_UDR_ERR (0x00000080)
/* Bit definitions and macros for LCDC_LGWSAR */
#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LGWSR */
#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
/* Bit definitions and macros for LCDC_LGWVPWR */
#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
/* Bit definitions and macros for LCDC_LGWPOR */
#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
/* Bit definitions and macros for LCDC_LGWPR */
#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
/* Bit definitions and macros for LCDC_LGWCR */
#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
#define LCDC_LGWCR_GW_RVS (0x00200000)
#define LCDC_LGWCR_GWE (0x00400000)
#define LCDC_LGWCR_GWCKE (0x00800000)
#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for LCDC_LGWDCR */
#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
#define LCDC_LGWDCR_GWBT (0x80000000)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
@@ -1540,125 +1383,6 @@
#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
/* Bit definitions and macros for SSI_CR */
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
#define SSI_CR_SYN (0x00000010)
#define SSI_CR_NET (0x00000008)
#define SSI_CR_RE (0x00000004)
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
/* Bit definitions and macros for SSI_ISR */
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
#define SSI_ISR_RDR1 (0x00008000)
#define SSI_ISR_RDR0 (0x00004000)
#define SSI_ISR_TDE1 (0x00002000)
#define SSI_ISR_TDE0 (0x00001000)
#define SSI_ISR_ROE1 (0x00000800)
#define SSI_ISR_ROE0 (0x00000400)
#define SSI_ISR_TUE1 (0x00000200)
#define SSI_ISR_TUE0 (0x00000100)
#define SSI_ISR_TFS (0x00000080)
#define SSI_ISR_RFS (0x00000040)
#define SSI_ISR_TLS (0x00000020)
#define SSI_ISR_RLS (0x00000010)
#define SSI_ISR_RFF1 (0x00000008)
#define SSI_ISR_RFF0 (0x00000004)
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_IER */
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
#define SSI_IER_TIE (0x00080000)
#define SSI_IER_CMDAU (0x00040000)
#define SSI_IER_CMDU (0x00020000)
#define SSI_IER_RXT (0x00010000)
#define SSI_IER_RDR1 (0x00008000)
#define SSI_IER_RDR0 (0x00004000)
#define SSI_IER_TDE1 (0x00002000)
#define SSI_IER_TDE0 (0x00001000)
#define SSI_IER_ROE1 (0x00000800)
#define SSI_IER_ROE0 (0x00000400)
#define SSI_IER_TUE1 (0x00000200)
#define SSI_IER_TUE0 (0x00000100)
#define SSI_IER_TFS (0x00000080)
#define SSI_IER_RFS (0x00000040)
#define SSI_IER_TLS (0x00000020)
#define SSI_IER_RLS (0x00000010)
#define SSI_IER_RFF1 (0x00000008)
#define SSI_IER_RFF0 (0x00000004)
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_TCR */
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
#define SSI_TCR_TFDIR (0x00000040)
#define SSI_TCR_TXDIR (0x00000020)
#define SSI_TCR_TSHFD (0x00000010)
#define SSI_TCR_TSCKP (0x00000008)
#define SSI_TCR_TFSI (0x00000004)
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
/* Bit definitions and macros for SSI_RCR */
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
#define SSI_RCR_RFEN0 (0x00000080)
#define SSI_RCR_RSHFD (0x00000010)
#define SSI_RCR_RSCKP (0x00000008)
#define SSI_RCR_RFSI (0x00000004)
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
/* Bit definitions and macros for SSI_CCR */
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
#define SSI_CCR_PM(x) ((x)&0x000000FF)
/* Bit definitions and macros for SSI_FCSR */
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
/* Bit definitions and macros for SSI_ACR */
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
/* Bit definitions and macros for SSI_ACADD */
#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
/* Bit definitions and macros for SSI_ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
/* Bit definitions and macros for SSI_ATAG */
#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/

316
include/asm-m68k/m5445x.h
View File

@@ -26,84 +26,6 @@
#ifndef __MCF5445X__
#define __MCF5445X__
/*********************************************************************
* Cross-bar switch (XBS)
*********************************************************************/
/* Bit definitions and macros for PRS group */
#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
/* Bit definitions and macros for CRS group */
#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
#define XBS_CRS_RO (0x80000000) /* Read Only */
#define XBS_CRS_PCTL_PARK_FIELD (0)
#define XBS_CRS_PCTL_PARK_ON_LAST (1)
#define XBS_CRS_PCTL_PARK_NONE (2)
#define XBS_CRS_PCTL_PARK_CORE (0)
#define XBS_CRS_PCTL_PARK_EDMA (1)
#define XBS_CRS_PCTL_PARK_FEC0 (2)
#define XBS_CRS_PCTL_PARK_FEC1 (3)
#define XBS_CRS_PCTL_PARK_PCI (5)
#define XBS_CRS_PCTL_PARK_USB (6)
#define XBS_CRS_PCTL_PARK_SBF (7)
/*********************************************************************
* FlexBus Chip Selects (FBCS)
*********************************************************************/
/* Bit definitions and macros for CSAR group */
#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for CSMR group */
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
#define FBCS_CSMR_WP (0x00000100) /* Write protect */
#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
#define FBCS_CSMR_BAM_128M (0x07FF0000)
#define FBCS_CSMR_BAM_64M (0x03FF0000)
#define FBCS_CSMR_BAM_32M (0x01FF0000)
#define FBCS_CSMR_BAM_16M (0x00FF0000)
#define FBCS_CSMR_BAM_8M (0x007F0000)
#define FBCS_CSMR_BAM_4M (0x003F0000)
#define FBCS_CSMR_BAM_2M (0x001F0000)
#define FBCS_CSMR_BAM_1M (0x000F0000)
#define FBCS_CSMR_BAM_1024K (0x000F0000)
#define FBCS_CSMR_BAM_512K (0x00070000)
#define FBCS_CSMR_BAM_256K (0x00030000)
#define FBCS_CSMR_BAM_128K (0x00010000)
#define FBCS_CSMR_BAM_64K (0x00000000)
/* Bit definitions and macros for CSCR group */
#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
#define FBCS_CSCR_PS_8 (0x00000040)
#define FBCS_CSCR_PS_16 (0x00000080)
#define FBCS_CSCR_PS_32 (0x00000000)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
@@ -421,106 +343,6 @@
/* Bit definitions and macros for ICR group */
#define INTC_ICR_IL(x) (((x)&0x07))
/*********************************************************************
* DMA Serial Peripheral Interface (DSPI)
*********************************************************************/
/* Bit definitions and macros for DMCR */
#define DSPI_DMCR_HALT (0x00000001)
#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
#define DSPI_DMCR_CRXF (0x00000400)
#define DSPI_DMCR_CTXF (0x00000800)
#define DSPI_DMCR_DRXF (0x00001000)
#define DSPI_DMCR_DTXF (0x00002000)
#define DSPI_DMCR_CSIS0 (0x00010000)
#define DSPI_DMCR_CSIS2 (0x00040000)
#define DSPI_DMCR_CSIS3 (0x00080000)
#define DSPI_DMCR_CSIS5 (0x00200000)
#define DSPI_DMCR_ROOE (0x01000000)
#define DSPI_DMCR_PCSSE (0x02000000)
#define DSPI_DMCR_MTFE (0x04000000)
#define DSPI_DMCR_FRZ (0x08000000)
#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
#define DSPI_DMCR_CSCK (0x40000000)
#define DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for DTCR */
#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for DCTAR group */
#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
#define DSPI_DCTAR_LSBFE (0x01000000)
#define DSPI_DCTAR_CPHA (0x02000000)
#define DSPI_DCTAR_CPOL (0x04000000)
#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
#define DSPI_DCTAR_PASC_1CLK (0x00000000)
#define DSPI_DCTAR_PASC_3CLK (0x00100000)
#define DSPI_DCTAR_PASC_5CLK (0x00200000)
#define DSPI_DCTAR_PASC_7CLK (0x00300000)
#define DSPI_DCTAR_PDT_1CLK (0x00000000)
#define DSPI_DCTAR_PDT_3CLK (0x00040000)
#define DSPI_DCTAR_PDT_5CLK (0x00080000)
#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
#define DSPI_DCTAR_PBR_1CLK (0x00000000)
#define DSPI_DCTAR_PBR_3CLK (0x00010000)
#define DSPI_DCTAR_PBR_5CLK (0x00020000)
#define DSPI_DCTAR_PBR_7CLK (0x00030000)
/* Bit definitions and macros for DSR */
#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
#define DSPI_DSR_RFDF (0x00020000)
#define DSPI_DSR_RFOF (0x00080000)
#define DSPI_DSR_TFFF (0x02000000)
#define DSPI_DSR_TFUF (0x08000000)
#define DSPI_DSR_EOQF (0x10000000)
#define DSPI_DSR_TXRXS (0x40000000)
#define DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for DIRSR */
#define DSPI_DIRSR_RFDFS (0x00010000)
#define DSPI_DIRSR_RFDFE (0x00020000)
#define DSPI_DIRSR_RFOFE (0x00080000)
#define DSPI_DIRSR_TFFFS (0x01000000)
#define DSPI_DIRSR_TFFFE (0x02000000)
#define DSPI_DIRSR_TFUFE (0x08000000)
#define DSPI_DIRSR_EOQFE (0x10000000)
#define DSPI_DIRSR_TCFE (0x80000000)
/* Bit definitions and macros for DTFR */
#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
#define DSPI_DTFR_CS0 (0x00010000)
#define DSPI_DTFR_CS2 (0x00040000)
#define DSPI_DTFR_CS3 (0x00080000)
#define DSPI_DTFR_CS5 (0x00200000)
#define DSPI_DTFR_CTCNT (0x04000000)
#define DSPI_DTFR_EOQ (0x08000000)
#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
#define DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for DRFR */
#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
/* Bit definitions and macros for DTFDR group */
#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
/* Bit definitions and macros for DRFDR group */
#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
/*********************************************************************
* Edge Port Module (EPORT)
*********************************************************************/
@@ -1297,127 +1119,6 @@
#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
/* Bit definitions and macros for CR */
#define SSI_CR_SSI_EN (0x00000001)
#define SSI_CR_TE (0x00000002)
#define SSI_CR_RE (0x00000004)
#define SSI_CR_NET (0x00000008)
#define SSI_CR_SYN (0x00000010)
#define SSI_CR_I2S(x) (((x)&0x00000003)<<5)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_I2S_NORMAL (0x00000000)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_SLAVE (0x00000040)
/* Bit definitions and macros for ISR */
#define SSI_ISR_TFE0 (0x00000001)
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_RFF0 (0x00000004)
#define SSI_ISR_RFF1 (0x00000008)
#define SSI_ISR_RLS (0x00000010)
#define SSI_ISR_TLS (0x00000020)
#define SSI_ISR_RFS (0x00000040)
#define SSI_ISR_TFS (0x00000080)
#define SSI_ISR_TUE0 (0x00000100)
#define SSI_ISR_TUE1 (0x00000200)
#define SSI_ISR_ROE0 (0x00000400)
#define SSI_ISR_ROE1 (0x00000800)
#define SSI_ISR_TDE0 (0x00001000)
#define SSI_ISR_TDE1 (0x00002000)
#define SSI_ISR_RDR0 (0x00004000)
#define SSI_ISR_RDR1 (0x00008000)
#define SSI_ISR_RXT (0x00010000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_CMDAU (0x00040000)
/* Bit definitions and macros for IER */
#define SSI_IER_TFE0 (0x00000001)
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_RFF0 (0x00000004)
#define SSI_IER_RFF1 (0x00000008)
#define SSI_IER_RLS (0x00000010)
#define SSI_IER_TLS (0x00000020)
#define SSI_IER_RFS (0x00000040)
#define SSI_IER_TFS (0x00000080)
#define SSI_IER_TUE0 (0x00000100)
#define SSI_IER_TUE1 (0x00000200)
#define SSI_IER_ROE0 (0x00000400)
#define SSI_IER_ROE1 (0x00000800)
#define SSI_IER_TDE0 (0x00001000)
#define SSI_IER_TDE1 (0x00002000)
#define SSI_IER_RDR0 (0x00004000)
#define SSI_IER_RDR1 (0x00008000)
#define SSI_IER_RXT (0x00010000)
#define SSI_IER_CMDU (0x00020000)
#define SSI_IER_CMDAU (0x00040000)
#define SSI_IER_TIE (0x00080000)
#define SSI_IER_TDMAE (0x00100000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_RDMAE (0x00400000)
/* Bit definitions and macros for TCR */
#define SSI_TCR_TEFS (0x00000001)
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TFSI (0x00000004)
#define SSI_TCR_TSCKP (0x00000008)
#define SSI_TCR_TSHFD (0x00000010)
#define SSI_TCR_TXDIR (0x00000020)
#define SSI_TCR_TFDIR (0x00000040)
#define SSI_TCR_TFEN0 (0x00000080)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TXBIT0 (0x00000200)
/* Bit definitions and macros for RCR */
#define SSI_RCR_REFS (0x00000001)
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_RFSI (0x00000004)
#define SSI_RCR_RSCKP (0x00000008)
#define SSI_RCR_RSHFD (0x00000010)
#define SSI_RCR_RFEN0 (0x00000080)
#define SSI_RCR_RFEN1 (0x00000100)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RXEXT (0x00000400)
/* Bit definitions and macros for CCR */
#define SSI_CCR_PM(x) (((x)&0x000000FF))
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_DIV2 (0x00040000)
/* Bit definitions and macros for FCSR */
#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
/* Bit definitions and macros for ACR */
#define SSI_ACR_AC97EN (0x00000001)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
/* Bit definitions and macros for ACADD */
#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
/* Bit definitions and macros for ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
/* Bit definitions and macros for ATAG */
#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
@@ -1503,13 +1204,13 @@
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
#define PCI_TCR1_B5E (0x00002000) /* */
#define PCI_TCR1_B4E (0x00001000) /* */
#define PCI_TCR1_B3E (0x00000800) /* */
#define PCI_TCR1_B2E (0x00000400) /* */
#define PCI_TCR1_B1E (0x00000200) /* */
#define PCI_TCR1_B0E (0x00000100) /* */
#define PCI_TCR1_CR (0x00000001) /* */
#define PCI_TCR2_B5E (0x00002000) /* */
#define PCI_TCR2_B4E (0x00001000) /* */
#define PCI_TCR2_B3E (0x00000800) /* */
#define PCI_TCR2_B2E (0x00000400) /* */
#define PCI_TCR2_B1E (0x00000200) /* */
#define PCI_TCR2_B0E (0x00000100) /* */
#define PCI_TCR2_CR (0x00000001) /* */
#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
#define PCI_TBATR_EN (0x00000001) /* Enable */
@@ -1533,8 +1234,7 @@
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
#define PCI_IDR_DEVID (
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
/********************************************************************/

502
include/asm-m68k/m547x_8x.h Normal file
View File

@@ -0,0 +1,502 @@
/*
* mcf547x_8x.h -- Definitions for Freescale Coldfire 547x_8x
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef mcf547x_8x_h
#define mcf547x_8x_h
/*********************************************************************
* XLB Arbiter (XLB)
*********************************************************************/
/* Bit definitions and macros for XARB_CFG */
#define XARB_CFG_AT (0x00000002)
#define XARB_CFG_DT (0x00000004)
#define XARB_CFG_BA (0x00000008)
#define XARB_CFG_PM(x) (((x)&0x00000003)<<5)
#define XARB_CFG_SP(x) (((x)&0x00000007)<<8)
#define XARB_CFG_PLDIS (0x80000000)
/* Bit definitions and macros for XARB_SR */
#define XARB_SR_AT (0x00000001)
#define XARB_SR_DT (0x00000002)
#define XARB_SR_BA (0x00000004)
#define XARB_SR_TTM (0x00000008)
#define XARB_SR_ECW (0x00000010)
#define XARB_SR_TTR (0x00000020)
#define XARB_SR_TTA (0x00000040)
#define XARB_SR_MM (0x00000080)
#define XARB_SR_SEA (0x00000100)
/* Bit definitions and macros for XARB_IMR */
#define XARB_IMR_ATE (0x00000001)
#define XARB_IMR_DTE (0x00000002)
#define XARB_IMR_BAE (0x00000004)
#define XARB_IMR_TTME (0x00000008)
#define XARB_IMR_ECWE (0x00000010)
#define XARB_IMR_TTRE (0x00000020)
#define XARB_IMR_TTAE (0x00000040)
#define XARB_IMR_MME (0x00000080)
#define XARB_IMR_SEAE (0x00000100)
/* Bit definitions and macros for XARB_SIGCAP */
#define XARB_SIGCAP_TT(x) ((x)&0x0000001F)
#define XARB_SIGCAP_TBST (0x00000020)
#define XARB_SIGCAP_TSIZ(x) (((x)&0x00000007)<<7)
/* Bit definitions and macros for XARB_PRIEN */
#define XARB_PRIEN_M0 (0x00000001)
#define XARB_PRIEN_M2 (0x00000004)
#define XARB_PRIEN_M3 (0x00000008)
/* Bit definitions and macros for XARB_PRI */
#define XARB_PRI_M0P(x) (((x)&0x00000007)<<0)
#define XARB_PRI_M2P(x) (((x)&0x00000007)<<8)
#define XARB_PRI_M3P(x) (((x)&0x00000007)<<12)
/*********************************************************************
* General Purpose I/O (GPIO)
*********************************************************************/
/* Bit definitions and macros for GPIO_PAR_FBCTL */
#define GPIO_PAR_FBCTL_TS(x) (((x)&0x0003)<<0)
#define GPIO_PAR_FBCTL_TA (0x0004)
#define GPIO_PAR_FBCTL_RWB(x) (((x)&0x0003)<<4)
#define GPIO_PAR_FBCTL_OE (0x0040)
#define GPIO_PAR_FBCTL_BWE0 (0x0100)
#define GPIO_PAR_FBCTL_BWE1 (0x0400)
#define GPIO_PAR_FBCTL_BWE2 (0x1000)
#define GPIO_PAR_FBCTL_BWE3 (0x4000)
#define GPIO_PAR_FBCTL_TS_GPIO (0)
#define GPIO_PAR_FBCTL_TS_TBST (2)
#define GPIO_PAR_FBCTL_TS_TS (3)
#define GPIO_PAR_FBCTL_RWB_GPIO (0x0000)
#define GPIO_PAR_FBCTL_RWB_TBST (0x0020)
#define GPIO_PAR_FBCTL_RWB_RWB (0x0030)
/* Bit definitions and macros for GPIO_PAR_FBCS */
#define GPIO_PAR_FBCS_CS1 (0x02)
#define GPIO_PAR_FBCS_CS2 (0x04)
#define GPIO_PAR_FBCS_CS3 (0x08)
#define GPIO_PAR_FBCS_CS4 (0x10)
#define GPIO_PAR_FBCS_CS5 (0x20)
/* Bit definitions and macros for GPIO_PAR_DMA */
#define GPIO_PAR_DMA_DREQ0(x) (((x)&0x03)<<0)
#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<2)
#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<4)
#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
#define GPIO_PAR_DMA_DACKx_GPIO (0)
#define GPIO_PAR_DMA_DACKx_TOUT (2)
#define GPIO_PAR_DMA_DACKx_DACK (3)
#define GPIO_PAR_DMA_DREQx_GPIO (0)
#define GPIO_PAR_DMA_DREQx_TIN (2)
#define GPIO_PAR_DMA_DREQx_DREQ (3)
/* Bit definitions and macros for GPIO_PAR_FECI2CIRQ */
#define GPIO_PAR_FECI2CIRQ_IRQ5 (0x0001)
#define GPIO_PAR_FECI2CIRQ_IRQ6 (0x0002)
#define GPIO_PAR_FECI2CIRQ_SCL (0x0004)
#define GPIO_PAR_FECI2CIRQ_SDA (0x0008)
#define GPIO_PAR_FECI2CIRQ_E1MDC(x) (((x)&0x0003)<<6)
#define GPIO_PAR_FECI2CIRQ_E1MDIO(x) (((x)&0x0003)<<8)
#define GPIO_PAR_FECI2CIRQ_E1MII (0x0400)
#define GPIO_PAR_FECI2CIRQ_E17 (0x0800)
#define GPIO_PAR_FECI2CIRQ_E0MDC (0x1000)
#define GPIO_PAR_FECI2CIRQ_E0MDIO (0x2000)
#define GPIO_PAR_FECI2CIRQ_E0MII (0x4000)
#define GPIO_PAR_FECI2CIRQ_E07 (0x8000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_CANRX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_SDA (0x0200)
#define GPIO_PAR_FECI2CIRQ_E1MDIO_EMDIO (0x0300)
#define GPIO_PAR_FECI2CIRQ_E1MDC_CANTX (0x0000)
#define GPIO_PAR_FECI2CIRQ_E1MDC_SCL (0x0080)
#define GPIO_PAR_FECI2CIRQ_E1MDC_EMDC (0x00C0)
/* Bit definitions and macros for GPIO_PAR_PCIBG */
#define GPIO_PAR_PCIBG_PCIBG0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBG_PCIBG1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBG_PCIBG2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBG_PCIBG3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBG_PCIBG4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PCIBR */
#define GPIO_PAR_PCIBR_PCIBR0(x) (((x)&0x0003)<<0)
#define GPIO_PAR_PCIBR_PCIBR1(x) (((x)&0x0003)<<2)
#define GPIO_PAR_PCIBR_PCIBR2(x) (((x)&0x0003)<<4)
#define GPIO_PAR_PCIBR_PCIBR3(x) (((x)&0x0003)<<6)
#define GPIO_PAR_PCIBR_PCIBR4(x) (((x)&0x0003)<<8)
/* Bit definitions and macros for GPIO_PAR_PSC3 */
#define GPIO_PAR_PSC3_TXD3 (0x04)
#define GPIO_PAR_PSC3_RXD3 (0x08)
#define GPIO_PAR_PSC3_RTS3(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC3_CTS3(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC3_CTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_CTS3_BCLK (0x80)
#define GPIO_PAR_PSC3_CTS3_CTS (0xC0)
#define GPIO_PAR_PSC3_RTS3_GPIO (0x00)
#define GPIO_PAR_PSC3_RTS3_FSYNC (0x20)
#define GPIO_PAR_PSC3_RTS3_RTS (0x30)
#define GPIO_PAR_PSC3_CTS2_CANRX (0x40)
/* Bit definitions and macros for GPIO_PAR_PSC2 */
#define GPIO_PAR_PSC2_TXD2 (0x04)
#define GPIO_PAR_PSC2_RXD2 (0x08)
#define GPIO_PAR_PSC2_RTS2(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC2_CTS2(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC2_CTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_CTS2_BCLK (0x80)
#define GPIO_PAR_PSC2_CTS2_CTS (0xC0)
#define GPIO_PAR_PSC2_RTS2_GPIO (0x00)
#define GPIO_PAR_PSC2_RTS2_CANTX (0x10)
#define GPIO_PAR_PSC2_RTS2_FSYNC (0x20)
#define GPIO_PAR_PSC2_RTS2_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC1 */
#define GPIO_PAR_PSC1_TXD1 (0x04)
#define GPIO_PAR_PSC1_RXD1 (0x08)
#define GPIO_PAR_PSC1_RTS1(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC1_CTS1(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC1_CTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_CTS1_BCLK (0x80)
#define GPIO_PAR_PSC1_CTS1_CTS (0xC0)
#define GPIO_PAR_PSC1_RTS1_GPIO (0x00)
#define GPIO_PAR_PSC1_RTS1_FSYNC (0x20)
#define GPIO_PAR_PSC1_RTS1_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_PSC0 */
#define GPIO_PAR_PSC0_TXD0 (0x04)
#define GPIO_PAR_PSC0_RXD0 (0x08)
#define GPIO_PAR_PSC0_RTS0(x) (((x)&0x03)<<4)
#define GPIO_PAR_PSC0_CTS0(x) (((x)&0x03)<<6)
#define GPIO_PAR_PSC0_CTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_CTS0_BCLK (0x80)
#define GPIO_PAR_PSC0_CTS0_CTS (0xC0)
#define GPIO_PAR_PSC0_RTS0_GPIO (0x00)
#define GPIO_PAR_PSC0_RTS0_FSYNC (0x20)
#define GPIO_PAR_PSC0_RTS0_RTS (0x30)
/* Bit definitions and macros for GPIO_PAR_DSPI */
#define GPIO_PAR_DSPI_SOUT(x) (((x)&0x0003)<<0)
#define GPIO_PAR_DSPI_SIN(x) (((x)&0x0003)<<2)
#define GPIO_PAR_DSPI_SCK(x) (((x)&0x0003)<<4)
#define GPIO_PAR_DSPI_CS0(x) (((x)&0x0003)<<6)
#define GPIO_PAR_DSPI_CS2(x) (((x)&0x0003)<<8)
#define GPIO_PAR_DSPI_CS3(x) (((x)&0x0003)<<10)
#define GPIO_PAR_DSPI_CS5 (0x1000)
#define GPIO_PAR_DSPI_CS3_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS3_CANTX (0x0400)
#define GPIO_PAR_DSPI_CS3_TOUT (0x0800)
#define GPIO_PAR_DSPI_CS3_DSPICS (0x0C00)
#define GPIO_PAR_DSPI_CS2_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS2_CANTX (0x0100)
#define GPIO_PAR_DSPI_CS2_TOUT (0x0200)
#define GPIO_PAR_DSPI_CS2_DSPICS (0x0300)
#define GPIO_PAR_DSPI_CS0_GPIO (0x0000)
#define GPIO_PAR_DSPI_CS0_FSYNC (0x0040)
#define GPIO_PAR_DSPI_CS0_RTS (0x0080)
#define GPIO_PAR_DSPI_CS0_DSPICS (0x00C0)
#define GPIO_PAR_DSPI_SCK_GPIO (0x0000)
#define GPIO_PAR_DSPI_SCK_BCLK (0x0010)
#define GPIO_PAR_DSPI_SCK_CTS (0x0020)
#define GPIO_PAR_DSPI_SCK_SCK (0x0030)
#define GPIO_PAR_DSPI_SIN_GPIO (0x0000)
#define GPIO_PAR_DSPI_SIN_RXD (0x0008)
#define GPIO_PAR_DSPI_SIN_SIN (0x000C)
#define GPIO_PAR_DSPI_SOUT_GPIO (0x0000)
#define GPIO_PAR_DSPI_SOUT_TXD (0x0002)
#define GPIO_PAR_DSPI_SOUT_SOUT (0x0003)
/* Bit definitions and macros for GPIO_PAR_TIMER */
#define GPIO_PAR_TIMER_TOUT2 (0x01)
#define GPIO_PAR_TIMER_TIN2(x) (((x)&0x03)<<1)
#define GPIO_PAR_TIMER_TOUT3 (0x08)
#define GPIO_PAR_TIMER_TIN3(x) (((x)&0x03)<<4)
#define GPIO_PAR_TIMER_TIN3_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN3_IRQ (0x20)
#define GPIO_PAR_TIMER_TIN3_TIN (0x30)
#define GPIO_PAR_TIMER_TIN2_CANRX (0x00)
#define GPIO_PAR_TIMER_TIN2_IRQ (0x04)
#define GPIO_PAR_TIMER_TIN2_TIN (0x06)
/*********************************************************************
* Slice Timer (SLT)
*********************************************************************/
#define SLT_CR_RUN (0x04000000)
#define SLT_CR_IEN (0x02000000)
#define SLT_CR_TEN (0x01000000)
#define SLT_SR_BE (0x02000000)
#define SLT_SR_ST (0x01000000)
/*********************************************************************
* Interrupt Controller (INTC)
*********************************************************************/
#define INT0_LO_RSVD0 (0)
#define INT0_LO_EPORT1 (1)
#define INT0_LO_EPORT2 (2)
#define INT0_LO_EPORT3 (3)
#define INT0_LO_EPORT4 (4)
#define INT0_LO_EPORT5 (5)
#define INT0_LO_EPORT6 (6)
#define INT0_LO_EPORT7 (7)
#define INT0_LO_EP0ISR (15)
#define INT0_LO_EP1ISR (16)
#define INT0_LO_EP2ISR (17)
#define INT0_LO_EP3ISR (18)
#define INT0_LO_EP4ISR (19)
#define INT0_LO_EP5ISR (20)
#define INT0_LO_EP6ISR (21)
#define INT0_LO_USBISR (22)
#define INT0_LO_USBAISR (23)
#define INT0_LO_USB (24)
#define INT1_LO_DSPI_RFOF_TFUF (25)
#define INT1_LO_DSPI_RFOF (26)
#define INT1_LO_DSPI_RFDF (27)
#define INT1_LO_DSPI_TFUF (28)
#define INT1_LO_DSPI_TCF (29)
#define INT1_LO_DSPI_TFFF (30)
#define INT1_LO_DSPI_EOQF (31)
#define INT0_HI_UART3 (32)
#define INT0_HI_UART2 (33)
#define INT0_HI_UART1 (34)
#define INT0_HI_UART0 (35)
#define INT0_HI_COMMTIM_TC (36)
#define INT0_HI_SEC (37)
#define INT0_HI_FEC1 (38)
#define INT0_HI_FEC0 (39)
#define INT0_HI_I2C (40)
#define INT0_HI_PCIARB (41)
#define INT0_HI_CBPCI (42)
#define INT0_HI_XLBPCI (43)
#define INT0_HI_XLBARB (47)
#define INT0_HI_DMA (48)
#define INT0_HI_CAN0_ERROR (49)
#define INT0_HI_CAN0_BUSOFF (50)
#define INT0_HI_CAN0_MBOR (51)
#define INT0_HI_SLT1 (53)
#define INT0_HI_SLT0 (54)
#define INT0_HI_CAN1_ERROR (55)
#define INT0_HI_CAN1_BUSOFF (56)
#define INT0_HI_CAN1_MBOR (57)
#define INT0_HI_GPT3 (59)
#define INT0_HI_GPT2 (60)
#define INT0_HI_GPT1 (61)
#define INT0_HI_GPT0 (62)
/* Bit definitions and macros for IPRH */
#define INTC_IPRH_INT32 (0x00000001)
#define INTC_IPRH_INT33 (0x00000002)
#define INTC_IPRH_INT34 (0x00000004)
#define INTC_IPRH_INT35 (0x00000008)
#define INTC_IPRH_INT36 (0x00000010)
#define INTC_IPRH_INT37 (0x00000020)
#define INTC_IPRH_INT38 (0x00000040)
#define INTC_IPRH_INT39 (0x00000080)
#define INTC_IPRH_INT40 (0x00000100)
#define INTC_IPRH_INT41 (0x00000200)
#define INTC_IPRH_INT42 (0x00000400)
#define INTC_IPRH_INT43 (0x00000800)
#define INTC_IPRH_INT44 (0x00001000)
#define INTC_IPRH_INT45 (0x00002000)
#define INTC_IPRH_INT46 (0x00004000)
#define INTC_IPRH_INT47 (0x00008000)
#define INTC_IPRH_INT48 (0x00010000)
#define INTC_IPRH_INT49 (0x00020000)
#define INTC_IPRH_INT50 (0x00040000)
#define INTC_IPRH_INT51 (0x00080000)
#define INTC_IPRH_INT52 (0x00100000)
#define INTC_IPRH_INT53 (0x00200000)
#define INTC_IPRH_INT54 (0x00400000)
#define INTC_IPRH_INT55 (0x00800000)
#define INTC_IPRH_INT56 (0x01000000)
#define INTC_IPRH_INT57 (0x02000000)
#define INTC_IPRH_INT58 (0x04000000)
#define INTC_IPRH_INT59 (0x08000000)
#define INTC_IPRH_INT60 (0x10000000)
#define INTC_IPRH_INT61 (0x20000000)
#define INTC_IPRH_INT62 (0x40000000)
#define INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for IPRL */
#define INTC_IPRL_INT0 (0x00000001)
#define INTC_IPRL_INT1 (0x00000002)
#define INTC_IPRL_INT2 (0x00000004)
#define INTC_IPRL_INT3 (0x00000008)
#define INTC_IPRL_INT4 (0x00000010)
#define INTC_IPRL_INT5 (0x00000020)
#define INTC_IPRL_INT6 (0x00000040)
#define INTC_IPRL_INT7 (0x00000080)
#define INTC_IPRL_INT8 (0x00000100)
#define INTC_IPRL_INT9 (0x00000200)
#define INTC_IPRL_INT10 (0x00000400)
#define INTC_IPRL_INT11 (0x00000800)
#define INTC_IPRL_INT12 (0x00001000)
#define INTC_IPRL_INT13 (0x00002000)
#define INTC_IPRL_INT14 (0x00004000)
#define INTC_IPRL_INT15 (0x00008000)
#define INTC_IPRL_INT16 (0x00010000)
#define INTC_IPRL_INT17 (0x00020000)
#define INTC_IPRL_INT18 (0x00040000)
#define INTC_IPRL_INT19 (0x00080000)
#define INTC_IPRL_INT20 (0x00100000)
#define INTC_IPRL_INT21 (0x00200000)
#define INTC_IPRL_INT22 (0x00400000)
#define INTC_IPRL_INT23 (0x00800000)
#define INTC_IPRL_INT24 (0x01000000)
#define INTC_IPRL_INT25 (0x02000000)
#define INTC_IPRL_INT26 (0x04000000)
#define INTC_IPRL_INT27 (0x08000000)
#define INTC_IPRL_INT28 (0x10000000)
#define INTC_IPRL_INT29 (0x20000000)
#define INTC_IPRL_INT30 (0x40000000)
#define INTC_IPRL_INT31 (0x80000000)
/*********************************************************************
* General Purpose Timers (GPTMR)
*********************************************************************/
/* Enable and Mode Select */
#define GPT_OCT(x) (x & 0x3)<<4 /* Output Compare Type */
#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
#define GPT_CTRL_CE 0x10 /* Counter Enable */
#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
#define GPT_MODE_GPIO(x) (x & 0x3)<<4 /* Gpio Mode Type */
#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
#define GPT_PWM_WIDTH(x) (x & 0xffff)
/* Status */
#define GPT_STA_CAPTURE(x) (x & 0xffff)
#define GPT_OVFPIN_OVF(x) (x & 0x70)
#define GPT_OVFPIN_PIN 0x01
#define GPT_INT_TEXP 0x08
#define GPT_INT_PWMP 0x04
#define GPT_INT_COMP 0x02
#define GPT_INT_CAPT 0x01
/*********************************************************************
* PCI
*********************************************************************/
/* Bit definitions and macros for SCR */
#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
#define PCI_SCR_SE (0x40000000) /* System error signalled */
#define PCI_SCR_MA (0x20000000) /* Master aboart received */
#define PCI_SCR_TR (0x10000000) /* Target abort received */
#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
#define PCI_SCR_DP (0x01000000) /* Master data parity err */
#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
#define PCI_SCR_R (0x00400000) /* Reserved */
#define PCI_SCR_66M (0x00200000) /* 66Mhz */
#define PCI_SCR_C (0x00100000) /* Capabilities list */
#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
#define PCI_SCR_S (0x00000100) /* SERR enable */
#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
#define PCI_SCR_PER (0x00000040) /* Parity error response */
#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
#define PCI_SCR_B (0x00000004) /* Bus master enable */
#define PCI_SCR_M (0x00000002) /* Memory access control */
#define PCI_SCR_IO (0x00000001) /* I/O access control */
#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
#define PCI_BAR_BAR1(x) (x & 0xC0000000)
#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
#define PCI_GSCR_SE (0x10000000) /* SERR detected */
#define PCI_GSCR_ER (0x08000000) /* Error response detected */
#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
#define PCI_GSCR_PR (0x00000001) /* PCI reset */
#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
#define PCI_TCR1_B5E (0x00002000) /* */
#define PCI_TCR1_B4E (0x00001000) /* */
#define PCI_TCR1_B3E (0x00000800) /* */
#define PCI_TCR1_B2E (0x00000400) /* */
#define PCI_TCR1_B1E (0x00000200) /* */
#define PCI_TCR1_B0E (0x00000100) /* */
#define PCI_TCR1_CR (0x00000001) /* */
#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
#define PCI_TBATR_EN (0x00000001) /* Enable */
#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
#define PCIARB_ACR_DS (0x80000000)
#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
#define PCIARB_ARC_INTMINTEN (0x00010000)
#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
#define PCIARB_ARC_INTMPRI (0x00000001)
#endif /* mcf547x_8x_h */

251
include/configs/M52277EVB.h Normal file
View File

@@ -0,0 +1,251 @@
/*
* Configuation settings for the Freescale MCF52277 EVB board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M52277EVB_H
#define _M52277EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF5227x /* define processor family */
#define CONFIG_M52277 /* define processor type */
#define CONFIG_M52277EVB /* M52277EVB board */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_BMP
#define CONFIG_HOSTNAME M52277EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 0x3ffff;" \
"era 0 3ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#define CFG_USB_EHCI_REGS_BASE 0xFC0B0000
#define CFG_USB_EHCI_CPU_INIT
#endif
/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK
#define CFG_INPUT_CLKSRC 16000000
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
#define CFG_HZ 1000
#define CFG_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x80000000
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x21
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 16)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
#define CFG_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x43711630
#define CFG_SDRAM_CFG2 0x56670000
#define CFG_SDRAM_CTRL 0xE1092000
#define CFG_SDRAM_EMOD 0x81810000
#define CFG_SDRAM_MODE 0x00CD0000
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OVERWRITE 1
#undef CFG_ENV_IS_EMBEDDED
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_BASE CFG_CS0_BASE
#define CFG_FLASH0_BASE CFG_CS0_BASE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000)
#define CFG_ENV_SECT_SIZE 0x8000
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_CHECKSUM
#endif
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
*/
#ifdef CONFIG_CMD_JFFS2
# define CONFIG_JFFS2_DEV "nor0"
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x40000)
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/*
* CS0 - NOR Flash
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CFG_CS0_BASE 0x00000000
#define CFG_CS0_MASK 0x00FF0001
#define CFG_CS0_CTRL 0x00001FA0
#endif /* _M52277EVB_H */

8
include/configs/M5329EVB.h
View File

@@ -213,7 +213,7 @@
#ifdef NANDFLASH_SIZE
# define CFG_MAX_NAND_DEVICE 1
# define CFG_NAND_BASE (CFG_CS2_BASE << 16)
# define CFG_NAND_BASE CFG_CS2_BASE
# define CFG_NAND_SIZE 1
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
# define NAND_MAX_CHIPS 1
@@ -224,7 +224,7 @@
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CFG_FLASH_BASE (CFG_CS0_BASE << 16)
#define CFG_FLASH_BASE CFG_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
@@ -254,12 +254,12 @@
#define CFG_CS0_MASK 0x007f0001
#define CFG_CS0_CTRL 0x00001fa0
#define CFG_CS1_BASE 0x1000
#define CFG_CS1_BASE 0x10000000
#define CFG_CS1_MASK 0x001f0001
#define CFG_CS1_CTRL 0x002A3780
#ifdef NANDFLASH_SIZE
#define CFG_CS2_BASE 0x2000
#define CFG_CS2_BASE 0x20000000
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
#define CFG_CS2_CTRL 0x00001f60
#endif

267
include/configs/M5373EVB.h Normal file
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@@ -0,0 +1,267 @@
/*
* Configuation settings for the Freescale MCF5373 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5373EVB_H
#define _M5373EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5373 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#ifdef NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
#define CFG_UNIFY_CACHE
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
#endif
#define CONFIG_MCFRTC
#undef RTC_DEBUG
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x58000
#define CFG_IMMR CFG_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 2ffff;" \
"era 0 2ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x40010000
#define CFG_HZ 1000
#define CFG_CLK 80000000
#define CFG_CPU_CLK CFG_CLK * 3
#define CFG_MBAR 0xFC000000
#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x80000000
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x221
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x40000000
#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CFG_SDRAM_CFG1 0x53722730
#define CFG_SDRAM_CFG2 0x56670000
#define CFG_SDRAM_CTRL 0xE1092000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#ifdef NANDFLASH_SIZE
# define CFG_MAX_NAND_DEVICE 1
# define CFG_NAND_BASE CFG_CS2_BASE
# define CFG_NAND_SIZE 1
# define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
# define NAND_MAX_CHIPS 1
# define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0"
# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CFG_FLASH_BASE CFG_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_OFFSET 0x4000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - CompactFlash and registers
* CS2 - NAND Flash 16, 32, or 64MB
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CFG_CS0_BASE 0
#define CFG_CS0_MASK 0x007f0001
#define CFG_CS0_CTRL 0x00001fa0
#define CFG_CS1_BASE 0x10000000
#define CFG_CS1_MASK 0x001f0001
#define CFG_CS1_CTRL 0x002A3780
#ifdef NANDFLASH_SIZE
#define CFG_CS2_BASE 0x20000000
#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
#define CFG_CS2_CTRL 0x00001f60
#endif
#endif /* _M5373EVB_H */

14
include/configs/M54455EVB.h
View File

@@ -176,6 +176,10 @@
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_SKIPPCI_HOSTBRIDGE
#define CFG_PCI_CACHE_LINE_SIZE 4
#define CFG_PCI_MEM_BUS 0xA0000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
@@ -192,9 +196,7 @@
/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA CFG_SPARTAN3
#define CONFIG_FPGA_COUNT 1
#define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC
@@ -286,9 +288,9 @@
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
# define CFG_ENV_SECT_SIZE 0x2000
#else
# define CFG_FLASH_BASE CFG_FLASH0_BASE
# define CFG_FLASH0_BASE CFG_CS1_BASE
# define CFG_FLASH1_BASE CFG_CS0_BASE
# define CFG_FLASH_BASE CFG_CS0_BASE
# define CFG_FLASH0_BASE CFG_CS0_BASE
# define CFG_FLASH1_BASE CFG_CS1_BASE
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
# define CFG_ENV_SECT_SIZE 0x20000
#endif

311
include/configs/M5475EVB.h Normal file
View File

@@ -0,0 +1,311 @@
/*
* Configuation settings for the Freescale MCF5475 board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5475EVB_H
#define _M5475EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF547x_8x /* define processor family */
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_SLTTMR
#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CONFIG_HAS_ETH1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 32
# define CFG_TX_ETH_BUFFER 48
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define CFG_FEC1_PINMUX 0
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif
#ifdef CONFIG_CMD_USB
# define CONFIG_USB_OHCI_NEW
# define CONFIG_USB_STORAGE
# ifndef CONFIG_CMD_PCI
# define CONFIG_CMD_PCI
# endif
# define CONFIG_PCI_OHCI
# define CONFIG_DOS_PARTITION
# undef CFG_USB_OHCI_BOARD_INIT
# undef CFG_USB_OHCI_CPU_INIT
# define CFG_USB_OHCI_MAX_ROOT_PORTS 15
# define CFG_USB_OHCI_SLOT_NAME "isp1561"
# define CFG_OHCI_SWAP_REG_ACCESS
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00008F00
#define CFG_IMMR CFG_MBAR
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_SKIPPCI_HOSTBRIDGE
#define CFG_PCI_CACHE_LINE_SIZE 8
#define CFG_PCI_MEM_BUS 0x80000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
#define CFG_PCI_MEM_SIZE 0x10000000
#define CFG_PCI_IO_BUS 0x71000000
#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
#define CFG_PCI_IO_SIZE 0x01000000
#define CFG_PCI_CFG_BUS 0x70000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000
#endif
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M547xEVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off bank 1;" \
"era ff800000 ff82ffff;" \
"cp.b ${loadaddr} ff800000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00010000
#define CFG_HZ 1000
#define CFG_CLK CFG_BUSCLK
#define CFG_CPU_CLK CFG_CLK * 2
#define CFG_MBAR 0xF0000000
#define CFG_INTSRAM (CFG_MBAR + 0x10000)
#define CFG_INTSRAMSZ 0x8000
/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0xF2000000
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x21
#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM1_CTRL 0x21
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_CFG1 0x73711630
#define CFG_SDRAM_CFG2 0x46370000
#define CFG_SDRAM_CTRL 0xE10B0000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
#define CFG_SDRAM_DRVSTRENGTH 0x000002AA
#ifdef CFG_DRAMSZ1
# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
#else
# define CFG_SDRAM_SIZE CFG_DRAMSZ
#endif
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_BASE (CFG_CS0_BASE)
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_USE_BUFFER_WRITE
#ifdef CFG_NOR1SZ
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
#else
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
#endif
#endif
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_OFFSET 0x2000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - NOR Flash
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CFG_CS0_BASE 0xFF800000
#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
#define CFG_CS1_BASE 0xF8000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CFG_CS1_CTRL 0x00000D80
#endif
#endif /* _M5475EVB_H */

296
include/configs/M5485EVB.h Normal file
View File

@@ -0,0 +1,296 @@
/*
* Configuation settings for the Freescale MCF5485 FireEngine board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5485EVB_H
#define _M5485EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF547x_8x /* define processor family */
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_SLTTMR
#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
# define CONFIG_HAS_ETH1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 32
# define CFG_TX_ETH_BUFFER 48
# define CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FEC0_PINMUX 0
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
# define CFG_FEC1_PINMUX 0
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CFG_FAULT_ECHO_LINK_DOWN
# define CFG_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CFG_DISCOVER_PHY */
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif
#ifdef CONFIG_CMD_USB
# define CONFIG_USB_STORAGE
# define CONFIG_DOS_PARTITION
# define CONFIG_USB_OHCI_NEW
# ifndef CONFIG_CMD_PCI
# define CONFIG_CMD_PCI
# endif
/*# define CONFIG_PCI_OHCI*/
# define CFG_USB_OHCI_REGS_BASE 0x80041000
# define CFG_USB_OHCI_MAX_ROOT_PORTS 15
# define CFG_USB_OHCI_SLOT_NAME "isp1561"
# define CFG_OHCI_SWAP_REG_ACCESS
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00008F00
#define CFG_IMMR CFG_MBAR
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CFG_PCI_MEM_BUS 0x80000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
#define CFG_PCI_MEM_SIZE 0x10000000
#define CFG_PCI_IO_BUS 0x71000000
#define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
#define CFG_PCI_IO_SIZE 0x01000000
#define CFG_PCI_CFG_BUS 0x70000000
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
#define CFG_PCI_CFG_SIZE 0x01000000
#endif
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#define CONFIG_HOSTNAME M548xEVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off bank 1;" \
"era ff800000 ff82ffff;" \
"cp.b ${loadaddr} ff800000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CFG_PROMPT "-> "
#define CFG_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00010000
#define CFG_HZ 1000
#define CFG_CLK CFG_BUSCLK
#define CFG_CPU_CLK CFG_CLK * 2
#define CFG_MBAR 0xF0000000
#define CFG_INTSRAM (CFG_MBAR + 0x10000)
#define CFG_INTSRAMSZ 0x8000
/*#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)*/
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0xF2000000
#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM_CTRL 0x21
#define CFG_INIT_RAM1_ADDR (CFG_INIT_RAM_ADDR + CFG_INIT_RAM_END)
#define CFG_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CFG_INIT_RAM1_CTRL 0x21
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_CFG1 0x73711630
#define CFG_SDRAM_CFG2 0x46370000
#define CFG_SDRAM_CTRL 0xE10B0000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
#define CFG_SDRAM_DRVSTRENGTH 0x000002AA
#ifdef CFG_DRAMSZ1
# define CFG_SDRAM_SIZE (CFG_DRAMSZ + CFG_DRAMSZ1)
#else
# define CFG_SDRAM_SIZE CFG_DRAMSZ
#endif
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_BOOTPARAMS_LEN 64*1024
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_BASE (CFG_CS0_BASE)
# define CFG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CFG_FLASH_USE_BUFFER_WRITE
#ifdef CFG_NOR1SZ
# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CFG_FLASH_SIZE ((CFG_NOR1SZ + CFG_BOOTSZ) << 20)
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
#else
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CFG_FLASH_SIZE (CFG_BOOTSZ << 20)
#endif
#endif
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_ENV_OFFSET 0x2000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_IS_EMBEDDED 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - NOR Flash
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CFG_CS0_BASE 0xFF800000
#define CFG_CS0_MASK (((CFG_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
#define CFG_CS1_BASE 0xF8000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CFG_CS1_CTRL 0x00000D80
#endif
#endif /* _M5485EVB_H */