From 71914337ef579bb22705d4b88fee6b1448f7a9b1 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 11 Aug 2023 16:12:25 +0900 Subject: [PATCH 01/12] eeprom: starfive: set eth0 mac address properly fdt_fixup_ethernet() sets eth0 mac address from ethaddr. Set ethaddr to environment instead of eth0addr. Signed-off-by: Seung-Woo Kim Reviewed-by: Leo Yu-Chi Liang --- board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c index befe7888c40..c334d98cf6e 100644 --- a/board/starfive/visionfive2/visionfive2-i2c-eeprom.c +++ b/board/starfive/visionfive2/visionfive2-i2c-eeprom.c @@ -504,7 +504,7 @@ int mac_read_from_eeprom(void) } // 1, setup ethaddr env - eth_env_set_enetaddr("eth0addr", pbuf.eeprom.atom4.data.mac0_addr); + eth_env_set_enetaddr("ethaddr", pbuf.eeprom.atom4.data.mac0_addr); eth_env_set_enetaddr("eth1addr", pbuf.eeprom.atom4.data.mac1_addr); /** From f39f8f77a5268530e982aa38e921c640d532a9ae Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Mon, 14 Aug 2023 18:05:28 +0200 Subject: [PATCH 02/12] riscv: allow riscv timer to be instantiated via device tree For the architectural timer on riscv, there already is a defined device tree binding[1]. Allow timer instances to be created from device tree matches, but for now retain the old mechanism, which registers the timer biggy-back with the CPU. [1] linux/Documentation/devicetree/bindings/timer/riscv,timer.yaml Signed-off-by: Torsten Duwe Reviewed-by: Leo Yu-Chi Liang --- drivers/timer/riscv_timer.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 3627ed79b81..28a6a6870b8 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer/riscv_timer.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -53,9 +54,26 @@ u64 notrace timer_early_get_count(void) static int riscv_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + u32 rate; - /* clock frequency was passed from the cpu driver as driver data */ - uc_priv->clock_rate = dev->driver_data; + /* When this function was called from the CPU driver, clock + * frequency is passed as driver data. + */ + rate = dev->driver_data; + + /* When called from an FDT match, the rate needs to be looked up. */ + if (!rate && gd->fdt_blob) { + rate = fdt_getprop_u32_default(gd->fdt_blob, + "/cpus", "timebase-frequency", 0); + } + + uc_priv->clock_rate = rate; + + /* With rate==0, timer uclass post_probe might later fail with -EINVAL. + * Give a hint at the cause for debugging. + */ + if (!rate) + log_err("riscv_timer_probe with invalid clock rate 0!\n"); return 0; } @@ -64,9 +82,15 @@ static const struct timer_ops riscv_timer_ops = { .get_count = riscv_timer_get_count, }; +static const struct udevice_id riscv_timer_ids[] = { + { .compatible = "riscv,timer", }, + { } +}; + U_BOOT_DRIVER(riscv_timer) = { .name = "riscv_timer", .id = UCLASS_TIMER, + .of_match = of_match_ptr(riscv_timer_ids), .probe = riscv_timer_probe, .ops = &riscv_timer_ops, .flags = DM_FLAG_PRE_RELOC, From 6164d86984cb6246680e5d94d9ec0633f2b70e98 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Mon, 14 Aug 2023 18:05:33 +0200 Subject: [PATCH 03/12] riscv: jh7110: enable riscv,timer in the device tree The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. Note that in the device tree. Signed-off-by: Torsten Duwe Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 081b833331b..ec237a46ffb 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -163,6 +163,15 @@ }; }; + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc"; From dccf4a843a5f0fb2befd31c47b70aecfd0a49ecb Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Tue, 22 Aug 2023 22:33:56 +0800 Subject: [PATCH 04/12] configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Although PCIE driver already exists, board defconfig isn't configured to enable PCIE enum on boot, thus USB storage device and NVME drive are not supported by default. So modify defconfig to enable PCIE auto enum, then start USB subsystem and scan nvme drive on boot. Signed-off-by: Shengyu Qu Tested-by: Milan P. Stanić --- configs/starfive_visionfive2_defconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index e9b63e5b847..3002c96f0ea 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_SYS_PCI_64BIT=y CONFIG_PCI=y +CONFIG_PCI_INIT_R=y CONFIG_TARGET_STARFIVE_VISIONFIVE2=y CONFIG_SPL_OPENSBI_LOAD_ADDR=0x40000000 CONFIG_ARCH_RV64I=y @@ -43,7 +44,7 @@ CONFIG_SD_BOOT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi" CONFIG_USE_PREBOOT=y -CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};" +CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb" CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y @@ -124,4 +125,9 @@ CONFIG_TIMER_EARLY=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_PCI=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_PCI=y +CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y From f943417737cd9b230ccaab94a717b338028a4f36 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Tue, 22 Aug 2023 22:33:57 +0800 Subject: [PATCH 05/12] doc: board: starfive: Add more info about supported driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since PLDA PCIE driver is added and VL805 support is enabled in defconfig for Starfive Visionfive 2, modify the document to keep consistent. Signed-off-by: Shengyu Qu Tested-by: Milan P. Stanić --- doc/board/starfive/visionfive2.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 941899a0a4e..460f23aec3a 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -20,6 +20,8 @@ The support for following drivers are already enabled: 3. StarFive JH7110 reset Driver. 4. Cadence QSPI controller Driver. 5. MMC SPI Driver for MMC/SD support. +6. PLDA PCIE controller driver. +7. On-board VL805 PCIE-USB controller driver. Booting from MMC using U-Boot SPL --------------------------------- From dd1eb1af2683f5d0e30e70af5bef1bab83f3e594 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Fri, 25 Aug 2023 00:25:18 +0800 Subject: [PATCH 06/12] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT Add SPL version of SYS_MALLOC_CLEAR_ON_INIT, this would help devices that need to clear ram before use to work correctly. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Tom Rini --- Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Kconfig b/Kconfig index 91170bf8d22..6ba605a5641 100644 --- a/Kconfig +++ b/Kconfig @@ -372,6 +372,17 @@ if EXPERT When disabling this, please check if malloc calls, maybe should be replaced by calloc - if one expects zeroed memory. +config SPL_SYS_MALLOC_CLEAR_ON_INIT + bool "Init with zeros the memory reserved for malloc (slow) in SPL" + depends on SPL + default SYS_MALLOC_CLEAR_ON_INIT + help + Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to + Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards + that must have particular memory regions zero'ed before first use. + If SYS_SPL_MALLOC_START is configured to be in such region, this + option should be enabled. + config SYS_MALLOC_DEFAULT_TO_INIT bool "Default malloc to init while reserving the memory for it" help From c9db9a2ef5558dc1e83965e452030dbf5ce93de2 Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Fri, 25 Aug 2023 00:25:19 +0800 Subject: [PATCH 07/12] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT To support SPL_SYS_MALLOC_CLEAR_ON_INIT, we have to modify #ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT to #if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Tom Rini --- common/dlmalloc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 0f9b7262d51..dcecdb8623c 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -631,7 +631,7 @@ void mem_malloc_init(ulong start, ulong size) debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start, mem_malloc_end); -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) memset((void *)mem_malloc_start, 0x0, size); #endif malloc_bin_reloc(); @@ -2153,7 +2153,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; /* check if expand_top called, in which case don't need to clear */ -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) #if MORECORE_CLEARS mchunkptr oldtop = top; INTERNAL_SIZE_T oldtopsize = chunksize(top); @@ -2184,7 +2184,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size; csz = chunksize(p); -#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT +#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT) #if MORECORE_CLEARS if (p == oldtop && csz > oldtopsize) { From 64339bc1f2ae2c0bfcc058a5001284a9a222f15b Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Fri, 25 Aug 2023 00:25:20 +0800 Subject: [PATCH 08/12] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5d..e5549a01b83 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT From f39e24496af503c7968cc5e15940701fdf2a0c5b Mon Sep 17 00:00:00 2001 From: Shengyu Qu Date: Fri, 25 Aug 2023 00:25:21 +0800 Subject: [PATCH 09/12] configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default SPL_SYS_MALLOC_CLEAR_ON_INIT would enable SYS_MALLOC_CLEAR_ON_INIT by default, but that's not need on JH7110, so disable that. Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 3002c96f0ea..9df6fcee0f5 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -59,6 +59,8 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x80000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x400000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_SYS_MALLOC_CLEAR_ON_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 CONFIG_SPL_I2C=y From ef08687ea0e2b5d57a1df51e6613bc4263747943 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Tue, 29 Aug 2023 10:20:14 +0900 Subject: [PATCH 10/12] spl: add __noreturn attribute to spl_invoke_opensbi function spl_invoke_opensbi function is not returned to SPL. Thus, we need to set __noreturn function attribute. Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- common/spl/spl_opensbi.c | 7 ++++--- include/spl.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index b0f40076c34..e2aaa460468 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -43,11 +43,12 @@ static int spl_opensbi_find_uboot_node(void *blob, int *uboot_node) return -ENODEV; } -void spl_invoke_opensbi(struct spl_image_info *spl_image) +void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image) { int ret, uboot_node; ulong uboot_entry; - void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info); + typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb, ulong info); + opensbi_entry_t opensbi_entry; if (!spl_image->fdt_addr) { pr_err("No device tree specified in SPL image\n"); @@ -74,7 +75,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS; opensbi_info.boot_hart = gd->arch.boot_hart; - opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; + opensbi_entry = (opensbi_entry_t)spl_image->entry_point; invalidate_icache_all(); #ifdef CONFIG_SPL_SMP diff --git a/include/spl.h b/include/spl.h index 92bcaa90a4a..93e906431e7 100644 --- a/include/spl.h +++ b/include/spl.h @@ -862,7 +862,7 @@ void __noreturn spl_optee_entry(void *arg0, void *arg1, void *arg2, void *arg3); /** * spl_invoke_opensbi - boot using a RISC-V OpenSBI image */ -void spl_invoke_opensbi(struct spl_image_info *spl_image); +void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image); /** * board_return_to_bootrom - allow for boards to continue with the boot ROM From d14222e7c152e36bf7d370c2623242a22fb9e821 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 4 Sep 2023 13:24:03 +0200 Subject: [PATCH 11/12] risc-v: implement DBCN write byte The DBCN extension provides a Console Write Byte call. Implement function sbi_dbcn_write_byte to invoke it. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/sbi.h | 1 + arch/riscv/lib/sbi.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 009a26885c6..bf4c9af6220 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -170,5 +170,6 @@ int sbi_get_mvendorid(long *mvendorid); int sbi_get_marchid(long *marchid); int sbi_get_mimpid(long *mimpid); void sbi_srst_reset(unsigned long type, unsigned long reason); +int sbi_dbcn_write_byte(unsigned char ch); #endif diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 8724e3a4600..55a3bc3b5c9 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -204,6 +204,22 @@ void sbi_srst_reset(unsigned long type, unsigned long reason) 0, 0, 0, 0); } +/** + * sbi_dbcn_write_byte() - write byte to debug console + * + * @ch: byte to be written + * Return: SBI error code (SBI_SUCCESS = 0 on success) + */ +int sbi_dbcn_write_byte(unsigned char ch) +{ + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_DBCN, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, + ch, 0, 0, 0, 0, 0); + return ret.error; +} + #ifdef CONFIG_SBI_V01 /** From dfe08374943c0e898fcfaf7327f69e0fb56b7d23 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 4 Sep 2023 13:24:04 +0200 Subject: [PATCH 12/12] risc-v: implement DBCN based debug console Use the DBCN SBI extension to implement a debug console. Make it the default for S-mode RISC-V. Signed-off-by: Heinrich Schuchardt Reviewed-by: Leo Yu-Chi Liang --- drivers/serial/Kconfig | 5 ++++- drivers/serial/serial_sbi.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index a1e089962a9..8c54bc9c470 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -218,6 +218,7 @@ config DEBUG_UART choice prompt "Select which UART will provide the debug UART" depends on DEBUG_UART + default DEBUG_SBI_CONSOLE if RISCV_SMODE default DEBUG_UART_NS16550 config DEBUG_UART_ALTERA_JTAGUART @@ -289,11 +290,13 @@ config DEBUG_EFI_CONSOLE config DEBUG_SBI_CONSOLE bool "SBI" - depends on SBI_V01 + depends on RISCV_SMODE help Select this to enable a debug console which calls back to SBI to output to the console. This can be useful for early debugging of U-Boot when running on top of SBI (Supervisor Binary Interface). + This implementation of the debug UART is not available while in + M-mode (e.g. during SPL). config DEBUG_UART_S5P bool "Samsung S5P" diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c index b9f35ed36e6..a51a96c1ef0 100644 --- a/drivers/serial/serial_sbi.c +++ b/drivers/serial/serial_sbi.c @@ -3,6 +3,8 @@ #include #include +#ifdef CONFIG_SBI_V01 + static inline void _debug_uart_init(void) { } @@ -13,4 +15,22 @@ static inline void _debug_uart_putc(int c) sbi_console_putchar(c); } +#else + +static int sbi_dbcn_available; + +static inline void _debug_uart_init(void) +{ + if (CONFIG_IS_ENABLED(RISCV_SMODE)) + sbi_dbcn_available = sbi_probe_extension(SBI_EXT_DBCN); +} + +static inline void _debug_uart_putc(int ch) +{ + if (CONFIG_IS_ENABLED(RISCV_SMODE) && sbi_dbcn_available) + sbi_dbcn_write_byte(ch); +} + +#endif + DEBUG_UART_FUNCS