ARM: vf610: Initial integration for Colibri VF50/VF61

This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.

- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
  - for VF50, use PLL2 as memory clock (synchronous mode)
  - for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default

Tested on Colibri VF50/VF61 booting using serial loader over UART.

Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Acked-by: Stefan Agner <stefan@agner.ch>

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -263,6 +263,11 @@
 #define SRC_SRSR_WDOG_M4				(0x1 << 4)
 #define SRC_SRSR_WDOG_A5				(0x1 << 3)
 #define SRC_SRSR_POR_RST				(0x1 << 0)
+#define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
+#define SRC_SBMR2_BMOD_SHIFT            24
+#define SRC_SBMR2_BMOD_FUSES            0x0
+#define SRC_SBMR2_BMOD_SERIAL           0x1
+#define SRC_SBMR2_BMOD_RCON             0x2
 
 /* Slow Clock Source Controller Module (SCSC) */
 #define SCSC_SOSC_CTR_SOSC_EN            0x1