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OMAP5: Configure the io settings for omap5432 uevm board

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This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla
2012-05-22 00:03:23 +00:00
committed by Albert ARIBAUD
parent 0a0bf7b217
commit eb4e18e89e
2 changed files with 93 additions and 20 deletions
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15
arch/arm/include/asm/arch-omap5/omap.h
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@@ -179,7 +179,14 @@ struct omap_sys_ctrl_regs {
u32 control_srcomp_east_side; /*0x4A002E7C*/
u32 control_srcomp_west_side; /*0x4A002E80*/
u32 control_srcomp_code_latch; /*0x4A002E84*/
u32 pad4[3680198];
u32 pad4[3679394];
u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
u32 pad5[10];
u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
u32 pad6[789];
u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
u32 control_padconf_mode; /* 0x4AE0CDA8 */
@@ -234,6 +241,12 @@ struct omap_sys_ctrl_regs {
#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100