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Move ICS CLK chip frequency calculation code into a common board library

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We have several boards that use the same ICS307 CLK chip to drive the
System clock and DDR clock.  Move the code into a common location so we
share it.

Convert the P2020DS board as the first to use the new common ICS307
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Timur Tabi <timur@freescale.com>
This commit is contained in:
Kumar Gala
2010-05-21 03:02:16 -05:00
parent b4a60e521c
commit ebf9d5261e
5 changed files with 124 additions and 160 deletions
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16
include/configs/P2020DS.h
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@@ -1,5 +1,5 @@
/*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -27,6 +27,8 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_MK_36BIT
#define CONFIG_PHYS_64BIT
#endif
@@ -54,17 +56,9 @@
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
extern unsigned long calculate_board_sys_clk(unsigned long dummy);
extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
/* extern unsigned long get_board_sys_clk(unsigned long dummy); */
/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
#endif
#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
from ICS307 instead of switches */
/*
* These can be toggled for performance analysis, otherwise use default.