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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini
2018-01-28 13:56:19 -05:00
parent 4f6c7b12ed 0289e291a5
commit f2ee915018
32 changed files with 2554 additions and 1010 deletions
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8
include/clk-uclass.h
View File

@@ -77,6 +77,14 @@ struct clk_ops {
* @return new rate, or -ve error code.
*/
ulong (*set_rate)(struct clk *clk, ulong rate);
/**
* set_parent() - Set current clock parent
*
* @clk: The clock to manipulate.
* @parent: New clock parent.
* @return zero on success, or -ve error code.
*/
int (*set_parent)(struct clk *clk, struct clk *parent);
/**
* enable() - Enable a clock.
*

28
include/clk.h
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@@ -133,6 +133,23 @@ static inline int clk_release_all(struct clk *clk, int count)
#endif
#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
CONFIG_IS_ENABLED(CLK)
/**
* clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}'
* properties to configure clocks
*
* @dev: A device to process (the ofnode associated with this device
* will be processed).
*/
int clk_set_defaults(struct udevice *dev);
#else
static inline int clk_set_defaults(struct udevice *dev)
{
return 0;
}
#endif
/**
* clk_request - Request a clock by provider-specific ID.
*
@@ -177,6 +194,17 @@ ulong clk_get_rate(struct clk *clk);
*/
ulong clk_set_rate(struct clk *clk, ulong rate);
/**
* clk_set_parent() - Set current clock parent.
*
* @clk: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
* @parent: A clock struct that was previously successfully requested by
* clk_request/get_by_*().
* @return new rate, or -ve error code.
*/
int clk_set_parent(struct clk *clk, struct clk *parent);
/**
* clk_enable() - Enable (turn on) a clock.
*

1
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -76,6 +76,7 @@
#define SCLK_PVTM_CORE 123
#define SCLK_PVTM_GPU 124
#define SCLK_MAC_PLL 150
#define SCLK_MAC 151
#define SCLK_MACREF_OUT 152

6
include/dt-bindings/clock/rk3328-cru.h
View File

@@ -86,6 +86,9 @@
#define SCLK_USB3OTG_SUSPEND 97
#define SCLK_REF_USB3OTG_SRC 98
#define SCLK_MAC2IO_SRC 99
#define SCLK_MAC2IO 100
#define SCLK_MAC2PHY 101
#define SCLK_MAC2IO_EXT 102
/* dclk gates */
#define DCLK_LCDC 180
@@ -199,9 +202,6 @@
#define CLK_NR_CLKS (HCLK_HDCP + 1)
#define SCLK_MAC2IO 0
#define SCLK_MAC2PHY 1
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */