Merge git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini
2018-02-12 12:08:32 -05:00
37 changed files with 126 additions and 75 deletions

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@@ -1,7 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0
* SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
*/
#ifndef COMMON_TIMING_PARAMS_H

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@@ -63,16 +63,20 @@
"initrd_high=0xffffffffffffffff\0" \
"fdt_addr=0x00f00000\0" \
"kernel_addr=0x01000000\0" \
"kernelheader_addr=0x800000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"kernelheader_size=0x40000\0" \
"console=ttyS0,115200\0" \
BOOTENV \
"boot_scripts=ls1012ardb_boot.scr\0" \
"boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
@@ -90,15 +94,27 @@
"run scan_dev_for_scripts; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"installer=load mmc 0:2 $load_addr " \
"/flex_installer_arm64.itb; " \
"bootm $load_addr#$board\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#include <asm/fsl_secure_boot.h>

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@@ -1,7 +1,7 @@
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0
* SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
*/
#ifndef FSL_DDR_MAIN_H

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@@ -2,7 +2,7 @@
* Copyright 2008-2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP Semiconductor
*
* SPDX-License-Identifier: GPL-2.0
* SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
*/
#ifndef DDR2_DIMM_PARAMS_H

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@@ -1,7 +1,7 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
#ifndef __FSL_DDRC_VER_H

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@@ -3,7 +3,7 @@
*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
#ifndef __FSL_IMMAP_H

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@@ -1,7 +1,7 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
#ifndef FSL_MMDC_H

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@@ -67,6 +67,9 @@ struct rng4tst {
};
u32 rsvd1[40];
#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002
#define RNG_STATE_HANDLE_MASK \
(RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED)
u32 rdsta; /*RNG DRNG Status Register*/
u32 rsvd2[15];
};