mirror of
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include/dt-bindings: Remove identical headers
As part of moving to using OF_UPSTREAM and so the upstream dt-bindings headers we have a number of these headers that are in our include directory and are currently identical to the versions in dts/upstream. We can remove these now to prevent future conflicts. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
@@ -1,118 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Device Tree binding constants for Actions Semi S700 Clock Management Unit
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Author: David Liu <liuwei@actions-semi.com>
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*
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* Author: Pathiban Nallathambi <pn@denx.de>
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* Author: Saravanan Sekar <sravanhome@gmail.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_S700_H
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#define __DT_BINDINGS_CLOCK_S700_H
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#define CLK_NONE 0
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/* pll clocks */
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#define CLK_CORE_PLL 1
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#define CLK_DEV_PLL 2
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#define CLK_DDR_PLL 3
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#define CLK_NAND_PLL 4
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#define CLK_DISPLAY_PLL 5
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#define CLK_TVOUT_PLL 6
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#define CLK_CVBS_PLL 7
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#define CLK_AUDIO_PLL 8
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#define CLK_ETHERNET_PLL 9
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/* system clock */
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#define CLK_CPU 10
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#define CLK_DEV 11
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#define CLK_AHB 12
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#define CLK_APB 13
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#define CLK_DMAC 14
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#define CLK_NOC0_CLK_MUX 15
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#define CLK_NOC1_CLK_MUX 16
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#define CLK_HP_CLK_MUX 17
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#define CLK_HP_CLK_DIV 18
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#define CLK_NOC1_CLK_DIV 19
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#define CLK_NOC0 20
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#define CLK_NOC1 21
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#define CLK_SENOR_SRC 22
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/* peripheral device clock */
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#define CLK_GPIO 23
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#define CLK_TIMER 24
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#define CLK_DSI 25
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#define CLK_CSI 26
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#define CLK_SI 27
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#define CLK_DE 28
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#define CLK_HDE 29
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#define CLK_VDE 30
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#define CLK_VCE 31
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#define CLK_NAND 32
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#define CLK_SD0 33
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#define CLK_SD1 34
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#define CLK_SD2 35
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#define CLK_UART0 36
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#define CLK_UART1 37
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#define CLK_UART2 38
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#define CLK_UART3 39
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#define CLK_UART4 40
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#define CLK_UART5 41
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#define CLK_UART6 42
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#define CLK_PWM0 43
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#define CLK_PWM1 44
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#define CLK_PWM2 45
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#define CLK_PWM3 46
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#define CLK_PWM4 47
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#define CLK_PWM5 48
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#define CLK_GPU3D 49
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#define CLK_I2C0 50
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#define CLK_I2C1 51
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#define CLK_I2C2 52
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#define CLK_I2C3 53
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#define CLK_SPI0 54
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#define CLK_SPI1 55
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#define CLK_SPI2 56
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#define CLK_SPI3 57
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#define CLK_USB3_480MPLL0 58
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#define CLK_USB3_480MPHY0 59
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#define CLK_USB3_5GPHY 60
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#define CLK_USB3_CCE 61
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#define CLK_USB3_MAC 62
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#define CLK_LCD 63
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#define CLK_HDMI_AUDIO 64
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#define CLK_I2SRX 65
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#define CLK_I2STX 66
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#define CLK_SENSOR0 67
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#define CLK_SENSOR1 68
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#define CLK_HDMI_DEV 69
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#define CLK_ETHERNET 70
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#define CLK_RMII_REF 71
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#define CLK_USB2H0_PLLEN 72
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#define CLK_USB2H0_PHY 73
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#define CLK_USB2H0_CCE 74
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#define CLK_USB2H1_PLLEN 75
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#define CLK_USB2H1_PHY 76
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#define CLK_USB2H1_CCE 77
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#define CLK_TVOUT 78
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#define CLK_THERMAL_SENSOR 79
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#define CLK_IRC_SWITCH 80
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#define CLK_PCM1 81
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#define CLK_NR_CLKS (CLK_PCM1 + 1)
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#endif /* __DT_BINDINGS_CLOCK_S700_H */
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@@ -1,129 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Device Tree binding constants for Actions Semi S900 Clock Management Unit
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Copyright (c) 2018 Linaro Ltd.
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#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
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#define __DT_BINDINGS_CLOCK_S900_CMU_H
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#define CLK_NONE 0
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/* fixed rate clocks */
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#define CLK_LOSC 1
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#define CLK_HOSC 2
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/* pll clocks */
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#define CLK_CORE_PLL 3
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#define CLK_DEV_PLL 4
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#define CLK_DDR_PLL 5
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#define CLK_NAND_PLL 6
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#define CLK_DISPLAY_PLL 7
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#define CLK_DSI_PLL 8
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#define CLK_ASSIST_PLL 9
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#define CLK_AUDIO_PLL 10
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/* system clock */
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#define CLK_CPU 15
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#define CLK_DEV 16
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#define CLK_NOC 17
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#define CLK_NOC_MUX 18
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#define CLK_NOC_DIV 19
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#define CLK_AHB 20
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#define CLK_APB 21
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#define CLK_DMAC 22
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/* peripheral device clock */
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#define CLK_GPIO 23
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#define CLK_BISP 24
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#define CLK_CSI0 25
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#define CLK_CSI1 26
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#define CLK_DE0 27
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#define CLK_DE1 28
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#define CLK_DE2 29
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#define CLK_DE3 30
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#define CLK_DSI 32
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#define CLK_GPU 33
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#define CLK_GPU_CORE 34
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#define CLK_GPU_MEM 35
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#define CLK_GPU_SYS 36
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#define CLK_HDE 37
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#define CLK_I2C0 38
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#define CLK_I2C1 39
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#define CLK_I2C2 40
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#define CLK_I2C3 41
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#define CLK_I2C4 42
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#define CLK_I2C5 43
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#define CLK_I2SRX 44
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#define CLK_I2STX 45
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#define CLK_IMX 46
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#define CLK_LCD 47
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#define CLK_NAND0 48
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#define CLK_NAND1 49
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#define CLK_PWM0 50
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#define CLK_PWM1 51
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#define CLK_PWM2 52
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#define CLK_PWM3 53
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#define CLK_PWM4 54
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#define CLK_PWM5 55
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#define CLK_SD0 56
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#define CLK_SD1 57
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#define CLK_SD2 58
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#define CLK_SD3 59
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#define CLK_SENSOR 60
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#define CLK_SPEED_SENSOR 61
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#define CLK_SPI0 62
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#define CLK_SPI1 63
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#define CLK_SPI2 64
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#define CLK_SPI3 65
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#define CLK_THERMAL_SENSOR 66
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#define CLK_UART0 67
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#define CLK_UART1 68
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#define CLK_UART2 69
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#define CLK_UART3 70
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#define CLK_UART4 71
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#define CLK_UART5 72
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#define CLK_UART6 73
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#define CLK_VCE 74
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#define CLK_VDE 75
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#define CLK_USB3_480MPLL0 76
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#define CLK_USB3_480MPHY0 77
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#define CLK_USB3_5GPHY 78
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#define CLK_USB3_CCE 79
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#define CLK_USB3_MAC 80
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#define CLK_TIMER 83
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#define CLK_HDMI_AUDIO 84
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#define CLK_24M 85
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#define CLK_EDP 86
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#define CLK_24M_EDP 87
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#define CLK_EDP_PLL 88
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#define CLK_EDP_LINK 89
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#define CLK_USB2H0_PLLEN 90
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#define CLK_USB2H0_PHY 91
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#define CLK_USB2H0_CCE 92
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#define CLK_USB2H1_PLLEN 93
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#define CLK_USB2H1_PHY 94
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#define CLK_USB2H1_CCE 95
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#define CLK_DDR0 96
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#define CLK_DDR1 97
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#define CLK_DMM 98
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#define CLK_ETH_MAC 99
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#define CLK_RMII_REF 100
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#define CLK_NR_CLKS (CLK_RMII_REF + 1)
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#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
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@@ -1,51 +0,0 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_BCM_NSP_H
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#define _CLOCK_BCM_NSP_H
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/* GENPLL clock channel ID */
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#define BCM_NSP_GENPLL 0
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#define BCM_NSP_GENPLL_PHY_CLK 1
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#define BCM_NSP_GENPLL_ENET_SW_CLK 2
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#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
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#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
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#define BCM_NSP_GENPLL_SATA1_CLK 5
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#define BCM_NSP_GENPLL_SATA2_CLK 6
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/* LCPLL0 clock channel ID */
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#define BCM_NSP_LCPLL0 0
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#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
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#define BCM_NSP_LCPLL0_SDIO_CLK 2
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#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
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#endif /* _CLOCK_BCM_NSP_H */
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@@ -1,9 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*/
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#define BCM2835_AUX_CLOCK_UART 0
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#define BCM2835_AUX_CLOCK_SPI1 1
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#define BCM2835_AUX_CLOCK_SPI2 2
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#define BCM2835_AUX_CLOCK_COUNT 3
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@@ -1,62 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*/
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#define BCM2835_PLLA 0
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#define BCM2835_PLLB 1
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#define BCM2835_PLLC 2
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#define BCM2835_PLLD 3
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#define BCM2835_PLLH 4
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#define BCM2835_PLLA_CORE 5
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#define BCM2835_PLLA_PER 6
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#define BCM2835_PLLB_ARM 7
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#define BCM2835_PLLC_CORE0 8
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#define BCM2835_PLLC_CORE1 9
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#define BCM2835_PLLC_CORE2 10
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#define BCM2835_PLLC_PER 11
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#define BCM2835_PLLD_CORE 12
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#define BCM2835_PLLD_PER 13
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#define BCM2835_PLLH_RCAL 14
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#define BCM2835_PLLH_AUX 15
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#define BCM2835_PLLH_PIX 16
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#define BCM2835_CLOCK_TIMER 17
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#define BCM2835_CLOCK_OTP 18
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#define BCM2835_CLOCK_UART 19
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#define BCM2835_CLOCK_VPU 20
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#define BCM2835_CLOCK_V3D 21
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#define BCM2835_CLOCK_ISP 22
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#define BCM2835_CLOCK_H264 23
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#define BCM2835_CLOCK_VEC 24
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#define BCM2835_CLOCK_HSM 25
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#define BCM2835_CLOCK_SDRAM 26
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#define BCM2835_CLOCK_TSENS 27
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#define BCM2835_CLOCK_EMMC 28
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#define BCM2835_CLOCK_PERI_IMAGE 29
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#define BCM2835_CLOCK_PWM 30
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#define BCM2835_CLOCK_PCM 31
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#define BCM2835_PLLA_DSI0 32
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#define BCM2835_PLLA_CCP2 33
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#define BCM2835_PLLD_DSI0 34
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#define BCM2835_PLLD_DSI1 35
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#define BCM2835_CLOCK_AVEO 36
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#define BCM2835_CLOCK_DFT 37
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#define BCM2835_CLOCK_GP0 38
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#define BCM2835_CLOCK_GP1 39
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#define BCM2835_CLOCK_GP2 40
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#define BCM2835_CLOCK_SLIM 41
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#define BCM2835_CLOCK_SMI 42
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#define BCM2835_CLOCK_TEC 43
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#define BCM2835_CLOCK_DPI 44
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#define BCM2835_CLOCK_CAM0 45
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#define BCM2835_CLOCK_CAM1 46
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#define BCM2835_CLOCK_DSI0E 47
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#define BCM2835_CLOCK_DSI1E 48
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#define BCM2835_CLOCK_DSI0P 49
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#define BCM2835_CLOCK_DSI1P 50
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#define BCM2711_CLOCK_EMMC2 51
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@@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
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#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
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#define QORIQ_CLK_SYSCLK 0
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#define QORIQ_CLK_CMUX 1
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#define QORIQ_CLK_HWACCEL 2
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#define QORIQ_CLK_FMAN 3
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#define QORIQ_CLK_PLATFORM_PLL 4
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#define QORIQ_CLK_CORECLK 5
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#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
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#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
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@@ -1,214 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
|
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/*
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* Copyright (c) 2016-2017 Linaro Ltd.
|
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
|
||||
*/
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||||
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#ifndef __DTS_HI3660_CLOCK_H
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#define __DTS_HI3660_CLOCK_H
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/* fixed rate clocks */
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#define HI3660_CLKIN_SYS 0
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#define HI3660_CLKIN_REF 1
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#define HI3660_CLK_FLL_SRC 2
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#define HI3660_CLK_PPLL0 3
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#define HI3660_CLK_PPLL1 4
|
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#define HI3660_CLK_PPLL2 5
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#define HI3660_CLK_PPLL3 6
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#define HI3660_CLK_SCPLL 7
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#define HI3660_PCLK 8
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#define HI3660_CLK_UART0_DBG 9
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#define HI3660_CLK_UART6 10
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#define HI3660_OSC32K 11
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#define HI3660_OSC19M 12
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#define HI3660_CLK_480M 13
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#define HI3660_CLK_INV 14
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|
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/* clk in crgctrl */
|
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#define HI3660_FACTOR_UART3 15
|
||||
#define HI3660_CLK_FACTOR_MMC 16
|
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#define HI3660_CLK_GATE_I2C0 17
|
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#define HI3660_CLK_GATE_I2C1 18
|
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#define HI3660_CLK_GATE_I2C2 19
|
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#define HI3660_CLK_GATE_I2C6 20
|
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#define HI3660_CLK_DIV_SYSBUS 21
|
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#define HI3660_CLK_DIV_320M 22
|
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#define HI3660_CLK_DIV_A53 23
|
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#define HI3660_CLK_GATE_SPI0 24
|
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#define HI3660_CLK_GATE_SPI2 25
|
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#define HI3660_PCIEPHY_REF 26
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#define HI3660_CLK_ABB_USB 27
|
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#define HI3660_HCLK_GATE_SDIO0 28
|
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#define HI3660_HCLK_GATE_SD 29
|
||||
#define HI3660_CLK_GATE_AOMM 30
|
||||
#define HI3660_PCLK_GPIO0 31
|
||||
#define HI3660_PCLK_GPIO1 32
|
||||
#define HI3660_PCLK_GPIO2 33
|
||||
#define HI3660_PCLK_GPIO3 34
|
||||
#define HI3660_PCLK_GPIO4 35
|
||||
#define HI3660_PCLK_GPIO5 36
|
||||
#define HI3660_PCLK_GPIO6 37
|
||||
#define HI3660_PCLK_GPIO7 38
|
||||
#define HI3660_PCLK_GPIO8 39
|
||||
#define HI3660_PCLK_GPIO9 40
|
||||
#define HI3660_PCLK_GPIO10 41
|
||||
#define HI3660_PCLK_GPIO11 42
|
||||
#define HI3660_PCLK_GPIO12 43
|
||||
#define HI3660_PCLK_GPIO13 44
|
||||
#define HI3660_PCLK_GPIO14 45
|
||||
#define HI3660_PCLK_GPIO15 46
|
||||
#define HI3660_PCLK_GPIO16 47
|
||||
#define HI3660_PCLK_GPIO17 48
|
||||
#define HI3660_PCLK_GPIO18 49
|
||||
#define HI3660_PCLK_GPIO19 50
|
||||
#define HI3660_PCLK_GPIO20 51
|
||||
#define HI3660_PCLK_GPIO21 52
|
||||
#define HI3660_CLK_GATE_SPI3 53
|
||||
#define HI3660_CLK_GATE_I2C7 54
|
||||
#define HI3660_CLK_GATE_I2C3 55
|
||||
#define HI3660_CLK_GATE_SPI1 56
|
||||
#define HI3660_CLK_GATE_UART1 57
|
||||
#define HI3660_CLK_GATE_UART2 58
|
||||
#define HI3660_CLK_GATE_UART4 59
|
||||
#define HI3660_CLK_GATE_UART5 60
|
||||
#define HI3660_CLK_GATE_I2C4 61
|
||||
#define HI3660_CLK_GATE_DMAC 62
|
||||
#define HI3660_PCLK_GATE_DSS 63
|
||||
#define HI3660_ACLK_GATE_DSS 64
|
||||
#define HI3660_CLK_GATE_LDI1 65
|
||||
#define HI3660_CLK_GATE_LDI0 66
|
||||
#define HI3660_CLK_GATE_VIVOBUS 67
|
||||
#define HI3660_CLK_GATE_EDC0 68
|
||||
#define HI3660_CLK_GATE_TXDPHY0_CFG 69
|
||||
#define HI3660_CLK_GATE_TXDPHY0_REF 70
|
||||
#define HI3660_CLK_GATE_TXDPHY1_CFG 71
|
||||
#define HI3660_CLK_GATE_TXDPHY1_REF 72
|
||||
#define HI3660_ACLK_GATE_USB3OTG 73
|
||||
#define HI3660_CLK_GATE_SPI4 74
|
||||
#define HI3660_CLK_GATE_SD 75
|
||||
#define HI3660_CLK_GATE_SDIO0 76
|
||||
#define HI3660_CLK_GATE_UFS_SUBSYS 77
|
||||
#define HI3660_PCLK_GATE_DSI0 78
|
||||
#define HI3660_PCLK_GATE_DSI1 79
|
||||
#define HI3660_ACLK_GATE_PCIE 80
|
||||
#define HI3660_PCLK_GATE_PCIE_SYS 81
|
||||
#define HI3660_CLK_GATE_PCIEAUX 82
|
||||
#define HI3660_PCLK_GATE_PCIE_PHY 83
|
||||
#define HI3660_CLK_ANDGT_LDI0 84
|
||||
#define HI3660_CLK_ANDGT_LDI1 85
|
||||
#define HI3660_CLK_ANDGT_EDC0 86
|
||||
#define HI3660_CLK_GATE_UFSPHY_GT 87
|
||||
#define HI3660_CLK_ANDGT_MMC 88
|
||||
#define HI3660_CLK_ANDGT_SD 89
|
||||
#define HI3660_CLK_A53HPM_ANDGT 90
|
||||
#define HI3660_CLK_ANDGT_SDIO 91
|
||||
#define HI3660_CLK_ANDGT_UART0 92
|
||||
#define HI3660_CLK_ANDGT_UART1 93
|
||||
#define HI3660_CLK_ANDGT_UARTH 94
|
||||
#define HI3660_CLK_ANDGT_SPI 95
|
||||
#define HI3660_CLK_VIVOBUS_ANDGT 96
|
||||
#define HI3660_CLK_AOMM_ANDGT 97
|
||||
#define HI3660_CLK_320M_PLL_GT 98
|
||||
#define HI3660_AUTODIV_EMMC0BUS 99
|
||||
#define HI3660_AUTODIV_SYSBUS 100
|
||||
#define HI3660_CLK_GATE_UFSPHY_CFG 101
|
||||
#define HI3660_CLK_GATE_UFSIO_REF 102
|
||||
#define HI3660_CLK_MUX_SYSBUS 103
|
||||
#define HI3660_CLK_MUX_UART0 104
|
||||
#define HI3660_CLK_MUX_UART1 105
|
||||
#define HI3660_CLK_MUX_UARTH 106
|
||||
#define HI3660_CLK_MUX_SPI 107
|
||||
#define HI3660_CLK_MUX_I2C 108
|
||||
#define HI3660_CLK_MUX_MMC_PLL 109
|
||||
#define HI3660_CLK_MUX_LDI1 110
|
||||
#define HI3660_CLK_MUX_LDI0 111
|
||||
#define HI3660_CLK_MUX_SD_PLL 112
|
||||
#define HI3660_CLK_MUX_SD_SYS 113
|
||||
#define HI3660_CLK_MUX_EDC0 114
|
||||
#define HI3660_CLK_MUX_SDIO_SYS 115
|
||||
#define HI3660_CLK_MUX_SDIO_PLL 116
|
||||
#define HI3660_CLK_MUX_VIVOBUS 117
|
||||
#define HI3660_CLK_MUX_A53HPM 118
|
||||
#define HI3660_CLK_MUX_320M 119
|
||||
#define HI3660_CLK_MUX_IOPERI 120
|
||||
#define HI3660_CLK_DIV_UART0 121
|
||||
#define HI3660_CLK_DIV_UART1 122
|
||||
#define HI3660_CLK_DIV_UARTH 123
|
||||
#define HI3660_CLK_DIV_MMC 124
|
||||
#define HI3660_CLK_DIV_SD 125
|
||||
#define HI3660_CLK_DIV_EDC0 126
|
||||
#define HI3660_CLK_DIV_LDI0 127
|
||||
#define HI3660_CLK_DIV_SDIO 128
|
||||
#define HI3660_CLK_DIV_LDI1 129
|
||||
#define HI3660_CLK_DIV_SPI 130
|
||||
#define HI3660_CLK_DIV_VIVOBUS 131
|
||||
#define HI3660_CLK_DIV_I2C 132
|
||||
#define HI3660_CLK_DIV_UFSPHY 133
|
||||
#define HI3660_CLK_DIV_CFGBUS 134
|
||||
#define HI3660_CLK_DIV_MMC0BUS 135
|
||||
#define HI3660_CLK_DIV_MMC1BUS 136
|
||||
#define HI3660_CLK_DIV_UFSPERI 137
|
||||
#define HI3660_CLK_DIV_AOMM 138
|
||||
#define HI3660_CLK_DIV_IOPERI 139
|
||||
#define HI3660_VENC_VOLT_HOLD 140
|
||||
#define HI3660_PERI_VOLT_HOLD 141
|
||||
#define HI3660_CLK_GATE_VENC 142
|
||||
#define HI3660_CLK_GATE_VDEC 143
|
||||
#define HI3660_CLK_ANDGT_VENC 144
|
||||
#define HI3660_CLK_ANDGT_VDEC 145
|
||||
#define HI3660_CLK_MUX_VENC 146
|
||||
#define HI3660_CLK_MUX_VDEC 147
|
||||
#define HI3660_CLK_DIV_VENC 148
|
||||
#define HI3660_CLK_DIV_VDEC 149
|
||||
#define HI3660_CLK_FAC_ISP_SNCLK 150
|
||||
#define HI3660_CLK_GATE_ISP_SNCLK0 151
|
||||
#define HI3660_CLK_GATE_ISP_SNCLK1 152
|
||||
#define HI3660_CLK_GATE_ISP_SNCLK2 153
|
||||
#define HI3660_CLK_ANGT_ISP_SNCLK 154
|
||||
#define HI3660_CLK_MUX_ISP_SNCLK 155
|
||||
#define HI3660_CLK_DIV_ISP_SNCLK 156
|
||||
|
||||
/* clk in pmuctrl */
|
||||
#define HI3660_GATE_ABB_192 0
|
||||
|
||||
/* clk in pctrl */
|
||||
#define HI3660_GATE_UFS_TCXO_EN 0
|
||||
#define HI3660_GATE_USB_TCXO_EN 1
|
||||
|
||||
/* clk in sctrl */
|
||||
#define HI3660_PCLK_AO_GPIO0 0
|
||||
#define HI3660_PCLK_AO_GPIO1 1
|
||||
#define HI3660_PCLK_AO_GPIO2 2
|
||||
#define HI3660_PCLK_AO_GPIO3 3
|
||||
#define HI3660_PCLK_AO_GPIO4 4
|
||||
#define HI3660_PCLK_AO_GPIO5 5
|
||||
#define HI3660_PCLK_AO_GPIO6 6
|
||||
#define HI3660_PCLK_GATE_MMBUF 7
|
||||
#define HI3660_CLK_GATE_DSS_AXI_MM 8
|
||||
#define HI3660_PCLK_MMBUF_ANDGT 9
|
||||
#define HI3660_CLK_MMBUF_PLL_ANDGT 10
|
||||
#define HI3660_CLK_FLL_MMBUF_ANDGT 11
|
||||
#define HI3660_CLK_SYS_MMBUF_ANDGT 12
|
||||
#define HI3660_CLK_GATE_PCIEPHY_GT 13
|
||||
#define HI3660_ACLK_MUX_MMBUF 14
|
||||
#define HI3660_CLK_SW_MMBUF 15
|
||||
#define HI3660_CLK_DIV_AOBUS 16
|
||||
#define HI3660_PCLK_DIV_MMBUF 17
|
||||
#define HI3660_ACLK_DIV_MMBUF 18
|
||||
#define HI3660_CLK_DIV_PCIEPHY 19
|
||||
|
||||
/* clk in iomcu */
|
||||
#define HI3660_CLK_I2C0_IOMCU 0
|
||||
#define HI3660_CLK_I2C1_IOMCU 1
|
||||
#define HI3660_CLK_I2C2_IOMCU 2
|
||||
#define HI3660_CLK_I2C6_IOMCU 3
|
||||
#define HI3660_CLK_IOMCU_PERI0 4
|
||||
|
||||
/* clk in stub clock */
|
||||
#define HI3660_CLK_STUB_CLUSTER0 0
|
||||
#define HI3660_CLK_STUB_CLUSTER1 1
|
||||
#define HI3660_CLK_STUB_GPU 2
|
||||
#define HI3660_CLK_STUB_DDR 3
|
||||
#define HI3660_CLK_STUB_NUM 4
|
||||
|
||||
#endif /* __DTS_HI3660_CLOCK_H */
|
||||
@@ -1,58 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
|
||||
*
|
||||
* This code is released using a dual license strategy: BSD/GPL
|
||||
* You can choose the licence that better fits your requirements.
|
||||
*
|
||||
* Released under the terms of 3-clause BSD License
|
||||
* Released under the terms of GNU General Public License Version 2.0
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
|
||||
#define __DT_BINDINGS_LPC32XX_CLOCK_H
|
||||
|
||||
/* LPC32XX System Control Block clocks */
|
||||
#define LPC32XX_CLK_RTC 1
|
||||
#define LPC32XX_CLK_DMA 2
|
||||
#define LPC32XX_CLK_MLC 3
|
||||
#define LPC32XX_CLK_SLC 4
|
||||
#define LPC32XX_CLK_LCD 5
|
||||
#define LPC32XX_CLK_MAC 6
|
||||
#define LPC32XX_CLK_SD 7
|
||||
#define LPC32XX_CLK_DDRAM 8
|
||||
#define LPC32XX_CLK_SSP0 9
|
||||
#define LPC32XX_CLK_SSP1 10
|
||||
#define LPC32XX_CLK_UART3 11
|
||||
#define LPC32XX_CLK_UART4 12
|
||||
#define LPC32XX_CLK_UART5 13
|
||||
#define LPC32XX_CLK_UART6 14
|
||||
#define LPC32XX_CLK_IRDA 15
|
||||
#define LPC32XX_CLK_I2C1 16
|
||||
#define LPC32XX_CLK_I2C2 17
|
||||
#define LPC32XX_CLK_TIMER0 18
|
||||
#define LPC32XX_CLK_TIMER1 19
|
||||
#define LPC32XX_CLK_TIMER2 20
|
||||
#define LPC32XX_CLK_TIMER3 21
|
||||
#define LPC32XX_CLK_TIMER4 22
|
||||
#define LPC32XX_CLK_TIMER5 23
|
||||
#define LPC32XX_CLK_WDOG 24
|
||||
#define LPC32XX_CLK_I2S0 25
|
||||
#define LPC32XX_CLK_I2S1 26
|
||||
#define LPC32XX_CLK_SPI1 27
|
||||
#define LPC32XX_CLK_SPI2 28
|
||||
#define LPC32XX_CLK_MCPWM 29
|
||||
#define LPC32XX_CLK_HSTIMER 30
|
||||
#define LPC32XX_CLK_KEY 31
|
||||
#define LPC32XX_CLK_PWM1 32
|
||||
#define LPC32XX_CLK_PWM2 33
|
||||
#define LPC32XX_CLK_ADC 34
|
||||
#define LPC32XX_CLK_HCLK_PLL 35
|
||||
#define LPC32XX_CLK_PERIPH 36
|
||||
|
||||
/* LPC32XX USB clocks */
|
||||
#define LPC32XX_USB_CLK_I2C 1
|
||||
#define LPC32XX_USB_CLK_DEVICE 2
|
||||
#define LPC32XX_USB_CLK_HOST 3
|
||||
|
||||
#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */
|
||||
@@ -1,112 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Solutions Corp.
|
||||
* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
|
||||
#define __DT_BINDINGS_CLOCK_R7S72100_H__
|
||||
|
||||
#define R7S72100_CLK_PLL 0
|
||||
#define R7S72100_CLK_I 1
|
||||
#define R7S72100_CLK_G 2
|
||||
|
||||
/* MSTP2 */
|
||||
#define R7S72100_CLK_CORESIGHT 0
|
||||
|
||||
/* MSTP3 */
|
||||
#define R7S72100_CLK_IEBUS 7
|
||||
#define R7S72100_CLK_IRDA 6
|
||||
#define R7S72100_CLK_LIN0 5
|
||||
#define R7S72100_CLK_LIN1 4
|
||||
#define R7S72100_CLK_MTU2 3
|
||||
#define R7S72100_CLK_CAN 2
|
||||
#define R7S72100_CLK_ADCPWR 1
|
||||
#define R7S72100_CLK_PWM 0
|
||||
|
||||
/* MSTP4 */
|
||||
#define R7S72100_CLK_SCIF0 7
|
||||
#define R7S72100_CLK_SCIF1 6
|
||||
#define R7S72100_CLK_SCIF2 5
|
||||
#define R7S72100_CLK_SCIF3 4
|
||||
#define R7S72100_CLK_SCIF4 3
|
||||
#define R7S72100_CLK_SCIF5 2
|
||||
#define R7S72100_CLK_SCIF6 1
|
||||
#define R7S72100_CLK_SCIF7 0
|
||||
|
||||
/* MSTP5 */
|
||||
#define R7S72100_CLK_SCI0 7
|
||||
#define R7S72100_CLK_SCI1 6
|
||||
#define R7S72100_CLK_SG0 5
|
||||
#define R7S72100_CLK_SG1 4
|
||||
#define R7S72100_CLK_SG2 3
|
||||
#define R7S72100_CLK_SG3 2
|
||||
#define R7S72100_CLK_OSTM0 1
|
||||
#define R7S72100_CLK_OSTM1 0
|
||||
|
||||
/* MSTP6 */
|
||||
#define R7S72100_CLK_ADC 7
|
||||
#define R7S72100_CLK_CEU 6
|
||||
#define R7S72100_CLK_DOC0 5
|
||||
#define R7S72100_CLK_DOC1 4
|
||||
#define R7S72100_CLK_DRC0 3
|
||||
#define R7S72100_CLK_DRC1 2
|
||||
#define R7S72100_CLK_JCU 1
|
||||
#define R7S72100_CLK_RTC 0
|
||||
|
||||
/* MSTP7 */
|
||||
#define R7S72100_CLK_VDEC0 7
|
||||
#define R7S72100_CLK_VDEC1 6
|
||||
#define R7S72100_CLK_ETHER 4
|
||||
#define R7S72100_CLK_NAND 3
|
||||
#define R7S72100_CLK_USB0 1
|
||||
#define R7S72100_CLK_USB1 0
|
||||
|
||||
/* MSTP8 */
|
||||
#define R7S72100_CLK_IMR0 7
|
||||
#define R7S72100_CLK_IMR1 6
|
||||
#define R7S72100_CLK_IMRDISP 5
|
||||
#define R7S72100_CLK_MMCIF 4
|
||||
#define R7S72100_CLK_MLB 3
|
||||
#define R7S72100_CLK_ETHAVB 2
|
||||
#define R7S72100_CLK_SCUX 1
|
||||
|
||||
/* MSTP9 */
|
||||
#define R7S72100_CLK_I2C0 7
|
||||
#define R7S72100_CLK_I2C1 6
|
||||
#define R7S72100_CLK_I2C2 5
|
||||
#define R7S72100_CLK_I2C3 4
|
||||
#define R7S72100_CLK_SPIBSC0 3
|
||||
#define R7S72100_CLK_SPIBSC1 2
|
||||
#define R7S72100_CLK_VDC50 1 /* and LVDS */
|
||||
#define R7S72100_CLK_VDC51 0
|
||||
|
||||
/* MSTP10 */
|
||||
#define R7S72100_CLK_SPI0 7
|
||||
#define R7S72100_CLK_SPI1 6
|
||||
#define R7S72100_CLK_SPI2 5
|
||||
#define R7S72100_CLK_SPI3 4
|
||||
#define R7S72100_CLK_SPI4 3
|
||||
#define R7S72100_CLK_CDROM 2
|
||||
#define R7S72100_CLK_SPDIF 1
|
||||
#define R7S72100_CLK_RGPVG2 0
|
||||
|
||||
/* MSTP11 */
|
||||
#define R7S72100_CLK_SSI0 5
|
||||
#define R7S72100_CLK_SSI1 4
|
||||
#define R7S72100_CLK_SSI2 3
|
||||
#define R7S72100_CLK_SSI3 2
|
||||
#define R7S72100_CLK_SSI4 1
|
||||
#define R7S72100_CLK_SSI5 0
|
||||
|
||||
/* MSTP12 */
|
||||
#define R7S72100_CLK_SDHI00 3
|
||||
#define R7S72100_CLK_SDHI01 2
|
||||
#define R7S72100_CLK_SDHI10 1
|
||||
#define R7S72100_CLK_SDHI11 0
|
||||
|
||||
/* MSTP13 */
|
||||
#define R7S72100_CLK_PIX1 2
|
||||
#define R7S72100_CLK_PIX0 1
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
|
||||
@@ -1,149 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* R9A06G032 sysctrl IDs
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Europe Limited
|
||||
*
|
||||
* Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
|
||||
#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
|
||||
|
||||
#define R9A06G032_CLK_PLL_USB 1
|
||||
#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */
|
||||
#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
|
||||
#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
|
||||
#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
|
||||
#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */
|
||||
#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */
|
||||
#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */
|
||||
#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
|
||||
#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
|
||||
#define R9A06G032_CLK_25_PG4 26
|
||||
#define R9A06G032_CLK_25_PG5 27
|
||||
#define R9A06G032_CLK_25_PG6 28
|
||||
#define R9A06G032_CLK_25_PG7 29
|
||||
#define R9A06G032_CLK_25_PG8 30
|
||||
#define R9A06G032_CLK_ADC 31
|
||||
#define R9A06G032_CLK_ECAT100 32
|
||||
#define R9A06G032_CLK_HSR100 33
|
||||
#define R9A06G032_CLK_I2C0 34
|
||||
#define R9A06G032_CLK_I2C1 35
|
||||
#define R9A06G032_CLK_MII_REF 36
|
||||
#define R9A06G032_CLK_NAND 37
|
||||
#define R9A06G032_CLK_NOUSBP2_PG6 38
|
||||
#define R9A06G032_CLK_P1_PG2 39
|
||||
#define R9A06G032_CLK_P1_PG3 40
|
||||
#define R9A06G032_CLK_P1_PG4 41
|
||||
#define R9A06G032_CLK_P4_PG3 42
|
||||
#define R9A06G032_CLK_P4_PG4 43
|
||||
#define R9A06G032_CLK_P6_PG1 44
|
||||
#define R9A06G032_CLK_P6_PG2 45
|
||||
#define R9A06G032_CLK_P6_PG3 46
|
||||
#define R9A06G032_CLK_P6_PG4 47
|
||||
#define R9A06G032_CLK_PCI_USB 48
|
||||
#define R9A06G032_CLK_QSPI0 49
|
||||
#define R9A06G032_CLK_QSPI1 50
|
||||
#define R9A06G032_CLK_RGMII_REF 51
|
||||
#define R9A06G032_CLK_RMII_REF 52
|
||||
#define R9A06G032_CLK_SDIO0 53
|
||||
#define R9A06G032_CLK_SDIO1 54
|
||||
#define R9A06G032_CLK_SERCOS100 55
|
||||
#define R9A06G032_CLK_SLCD 56
|
||||
#define R9A06G032_CLK_SPI0 57
|
||||
#define R9A06G032_CLK_SPI1 58
|
||||
#define R9A06G032_CLK_SPI2 59
|
||||
#define R9A06G032_CLK_SPI3 60
|
||||
#define R9A06G032_CLK_SPI4 61
|
||||
#define R9A06G032_CLK_SPI5 62
|
||||
#define R9A06G032_CLK_SWITCH 63
|
||||
#define R9A06G032_HCLK_ECAT125 65
|
||||
#define R9A06G032_HCLK_PINCONFIG 66
|
||||
#define R9A06G032_HCLK_SERCOS 67
|
||||
#define R9A06G032_HCLK_SGPIO2 68
|
||||
#define R9A06G032_HCLK_SGPIO3 69
|
||||
#define R9A06G032_HCLK_SGPIO4 70
|
||||
#define R9A06G032_HCLK_TIMER0 71
|
||||
#define R9A06G032_HCLK_TIMER1 72
|
||||
#define R9A06G032_HCLK_USBF 73
|
||||
#define R9A06G032_HCLK_USBH 74
|
||||
#define R9A06G032_HCLK_USBPM 75
|
||||
#define R9A06G032_CLK_48_PG_F 76
|
||||
#define R9A06G032_CLK_48_PG4 77
|
||||
#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
|
||||
#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */
|
||||
#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */
|
||||
#define R9A06G032_HCLK_CAN0 85
|
||||
#define R9A06G032_HCLK_CAN1 86
|
||||
#define R9A06G032_HCLK_DELTASIGMA 87
|
||||
#define R9A06G032_HCLK_PWMPTO 88
|
||||
#define R9A06G032_HCLK_RSV 89
|
||||
#define R9A06G032_HCLK_SGPIO0 90
|
||||
#define R9A06G032_HCLK_SGPIO1 91
|
||||
#define R9A06G032_RTOS_MDC 92
|
||||
#define R9A06G032_CLK_CM3 93
|
||||
#define R9A06G032_CLK_DDRC 94
|
||||
#define R9A06G032_CLK_ECAT25 95
|
||||
#define R9A06G032_CLK_HSR50 96
|
||||
#define R9A06G032_CLK_HW_RTOS 97
|
||||
#define R9A06G032_CLK_SERCOS50 98
|
||||
#define R9A06G032_HCLK_ADC 99
|
||||
#define R9A06G032_HCLK_CM3 100
|
||||
#define R9A06G032_HCLK_CRYPTO_EIP150 101
|
||||
#define R9A06G032_HCLK_CRYPTO_EIP93 102
|
||||
#define R9A06G032_HCLK_DDRC 103
|
||||
#define R9A06G032_HCLK_DMA0 104
|
||||
#define R9A06G032_HCLK_DMA1 105
|
||||
#define R9A06G032_HCLK_GMAC0 106
|
||||
#define R9A06G032_HCLK_GMAC1 107
|
||||
#define R9A06G032_HCLK_GPIO0 108
|
||||
#define R9A06G032_HCLK_GPIO1 109
|
||||
#define R9A06G032_HCLK_GPIO2 110
|
||||
#define R9A06G032_HCLK_HSR 111
|
||||
#define R9A06G032_HCLK_I2C0 112
|
||||
#define R9A06G032_HCLK_I2C1 113
|
||||
#define R9A06G032_HCLK_LCD 114
|
||||
#define R9A06G032_HCLK_MSEBI_M 115
|
||||
#define R9A06G032_HCLK_MSEBI_S 116
|
||||
#define R9A06G032_HCLK_NAND 117
|
||||
#define R9A06G032_HCLK_PG_I 118
|
||||
#define R9A06G032_HCLK_PG19 119
|
||||
#define R9A06G032_HCLK_PG20 120
|
||||
#define R9A06G032_HCLK_PG3 121
|
||||
#define R9A06G032_HCLK_PG4 122
|
||||
#define R9A06G032_HCLK_QSPI0 123
|
||||
#define R9A06G032_HCLK_QSPI1 124
|
||||
#define R9A06G032_HCLK_ROM 125
|
||||
#define R9A06G032_HCLK_RTC 126
|
||||
#define R9A06G032_HCLK_SDIO0 127
|
||||
#define R9A06G032_HCLK_SDIO1 128
|
||||
#define R9A06G032_HCLK_SEMAP 129
|
||||
#define R9A06G032_HCLK_SPI0 130
|
||||
#define R9A06G032_HCLK_SPI1 131
|
||||
#define R9A06G032_HCLK_SPI2 132
|
||||
#define R9A06G032_HCLK_SPI3 133
|
||||
#define R9A06G032_HCLK_SPI4 134
|
||||
#define R9A06G032_HCLK_SPI5 135
|
||||
#define R9A06G032_HCLK_SWITCH 136
|
||||
#define R9A06G032_HCLK_SWITCH_RG 137
|
||||
#define R9A06G032_HCLK_UART0 138
|
||||
#define R9A06G032_HCLK_UART1 139
|
||||
#define R9A06G032_HCLK_UART2 140
|
||||
#define R9A06G032_HCLK_UART3 141
|
||||
#define R9A06G032_HCLK_UART4 142
|
||||
#define R9A06G032_HCLK_UART5 143
|
||||
#define R9A06G032_HCLK_UART6 144
|
||||
#define R9A06G032_HCLK_UART7 145
|
||||
#define R9A06G032_CLK_UART0 146
|
||||
#define R9A06G032_CLK_UART1 147
|
||||
#define R9A06G032_CLK_UART2 148
|
||||
#define R9A06G032_CLK_UART3 149
|
||||
#define R9A06G032_CLK_UART4 150
|
||||
#define R9A06G032_CLK_UART5 151
|
||||
#define R9A06G032_CLK_UART6 152
|
||||
#define R9A06G032_CLK_UART7 153
|
||||
|
||||
#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
|
||||
@@ -1,24 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2019 SiFive, Inc.
|
||||
* Wesley Terpstra
|
||||
* Paul Walmsley
|
||||
* Zong Li
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
|
||||
#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
|
||||
|
||||
/* Clock indexes for use by Device Tree data and the PRCI driver */
|
||||
|
||||
#define FU740_PRCI_CLK_COREPLL 0
|
||||
#define FU740_PRCI_CLK_DDRPLL 1
|
||||
#define FU740_PRCI_CLK_GEMGXLPLL 2
|
||||
#define FU740_PRCI_CLK_DVFSCOREPLL 3
|
||||
#define FU740_PRCI_CLK_HFPCLKPLL 4
|
||||
#define FU740_PRCI_CLK_CLTXPLL 5
|
||||
#define FU740_PRCI_CLK_TLCLK 6
|
||||
#define FU740_PRCI_CLK_PCLK 7
|
||||
#define FU740_PRCI_CLK_PCIE_AUX 8
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
|
||||
@@ -1,176 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
||||
/*
|
||||
* Copyright (C) 2023 Sophgo Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
|
||||
#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__
|
||||
|
||||
#define CLK_MPLL 0
|
||||
#define CLK_TPLL 1
|
||||
#define CLK_FPLL 2
|
||||
#define CLK_MIPIMPLL 3
|
||||
#define CLK_A0PLL 4
|
||||
#define CLK_DISPPLL 5
|
||||
#define CLK_CAM0PLL 6
|
||||
#define CLK_CAM1PLL 7
|
||||
|
||||
#define CLK_MIPIMPLL_D3 8
|
||||
#define CLK_CAM0PLL_D2 9
|
||||
#define CLK_CAM0PLL_D3 10
|
||||
|
||||
#define CLK_TPU 11
|
||||
#define CLK_TPU_FAB 12
|
||||
#define CLK_AHB_ROM 13
|
||||
#define CLK_DDR_AXI_REG 14
|
||||
#define CLK_RTC_25M 15
|
||||
#define CLK_SRC_RTC_SYS_0 16
|
||||
#define CLK_TEMPSEN 17
|
||||
#define CLK_SARADC 18
|
||||
#define CLK_EFUSE 19
|
||||
#define CLK_APB_EFUSE 20
|
||||
#define CLK_DEBUG 21
|
||||
#define CLK_AP_DEBUG 22
|
||||
#define CLK_XTAL_MISC 23
|
||||
#define CLK_AXI4_EMMC 24
|
||||
#define CLK_EMMC 25
|
||||
#define CLK_EMMC_100K 26
|
||||
#define CLK_AXI4_SD0 27
|
||||
#define CLK_SD0 28
|
||||
#define CLK_SD0_100K 29
|
||||
#define CLK_AXI4_SD1 30
|
||||
#define CLK_SD1 31
|
||||
#define CLK_SD1_100K 32
|
||||
#define CLK_SPI_NAND 33
|
||||
#define CLK_ETH0_500M 34
|
||||
#define CLK_AXI4_ETH0 35
|
||||
#define CLK_ETH1_500M 36
|
||||
#define CLK_AXI4_ETH1 37
|
||||
#define CLK_APB_GPIO 38
|
||||
#define CLK_APB_GPIO_INTR 39
|
||||
#define CLK_GPIO_DB 40
|
||||
#define CLK_AHB_SF 41
|
||||
#define CLK_AHB_SF1 42
|
||||
#define CLK_A24M 43
|
||||
#define CLK_AUDSRC 44
|
||||
#define CLK_APB_AUDSRC 45
|
||||
#define CLK_SDMA_AXI 46
|
||||
#define CLK_SDMA_AUD0 47
|
||||
#define CLK_SDMA_AUD1 48
|
||||
#define CLK_SDMA_AUD2 49
|
||||
#define CLK_SDMA_AUD3 50
|
||||
#define CLK_I2C 51
|
||||
#define CLK_APB_I2C 52
|
||||
#define CLK_APB_I2C0 53
|
||||
#define CLK_APB_I2C1 54
|
||||
#define CLK_APB_I2C2 55
|
||||
#define CLK_APB_I2C3 56
|
||||
#define CLK_APB_I2C4 57
|
||||
#define CLK_APB_WDT 58
|
||||
#define CLK_PWM_SRC 59
|
||||
#define CLK_PWM 60
|
||||
#define CLK_SPI 61
|
||||
#define CLK_APB_SPI0 62
|
||||
#define CLK_APB_SPI1 63
|
||||
#define CLK_APB_SPI2 64
|
||||
#define CLK_APB_SPI3 65
|
||||
#define CLK_1M 66
|
||||
#define CLK_CAM0_200 67
|
||||
#define CLK_PM 68
|
||||
#define CLK_TIMER0 69
|
||||
#define CLK_TIMER1 70
|
||||
#define CLK_TIMER2 71
|
||||
#define CLK_TIMER3 72
|
||||
#define CLK_TIMER4 73
|
||||
#define CLK_TIMER5 74
|
||||
#define CLK_TIMER6 75
|
||||
#define CLK_TIMER7 76
|
||||
#define CLK_UART0 77
|
||||
#define CLK_APB_UART0 78
|
||||
#define CLK_UART1 79
|
||||
#define CLK_APB_UART1 80
|
||||
#define CLK_UART2 81
|
||||
#define CLK_APB_UART2 82
|
||||
#define CLK_UART3 83
|
||||
#define CLK_APB_UART3 84
|
||||
#define CLK_UART4 85
|
||||
#define CLK_APB_UART4 86
|
||||
#define CLK_APB_I2S0 87
|
||||
#define CLK_APB_I2S1 88
|
||||
#define CLK_APB_I2S2 89
|
||||
#define CLK_APB_I2S3 90
|
||||
#define CLK_AXI4_USB 91
|
||||
#define CLK_APB_USB 92
|
||||
#define CLK_USB_125M 93
|
||||
#define CLK_USB_33K 94
|
||||
#define CLK_USB_12M 95
|
||||
#define CLK_AXI4 96
|
||||
#define CLK_AXI6 97
|
||||
#define CLK_DSI_ESC 98
|
||||
#define CLK_AXI_VIP 99
|
||||
#define CLK_SRC_VIP_SYS_0 100
|
||||
#define CLK_SRC_VIP_SYS_1 101
|
||||
#define CLK_SRC_VIP_SYS_2 102
|
||||
#define CLK_SRC_VIP_SYS_3 103
|
||||
#define CLK_SRC_VIP_SYS_4 104
|
||||
#define CLK_CSI_BE_VIP 105
|
||||
#define CLK_CSI_MAC0_VIP 106
|
||||
#define CLK_CSI_MAC1_VIP 107
|
||||
#define CLK_CSI_MAC2_VIP 108
|
||||
#define CLK_CSI0_RX_VIP 109
|
||||
#define CLK_CSI1_RX_VIP 110
|
||||
#define CLK_ISP_TOP_VIP 111
|
||||
#define CLK_IMG_D_VIP 112
|
||||
#define CLK_IMG_V_VIP 113
|
||||
#define CLK_SC_TOP_VIP 114
|
||||
#define CLK_SC_D_VIP 115
|
||||
#define CLK_SC_V1_VIP 116
|
||||
#define CLK_SC_V2_VIP 117
|
||||
#define CLK_SC_V3_VIP 118
|
||||
#define CLK_DWA_VIP 119
|
||||
#define CLK_BT_VIP 120
|
||||
#define CLK_DISP_VIP 121
|
||||
#define CLK_DSI_MAC_VIP 122
|
||||
#define CLK_LVDS0_VIP 123
|
||||
#define CLK_LVDS1_VIP 124
|
||||
#define CLK_PAD_VI_VIP 125
|
||||
#define CLK_PAD_VI1_VIP 126
|
||||
#define CLK_PAD_VI2_VIP 127
|
||||
#define CLK_CFG_REG_VIP 128
|
||||
#define CLK_VIP_IP0 129
|
||||
#define CLK_VIP_IP1 130
|
||||
#define CLK_VIP_IP2 131
|
||||
#define CLK_VIP_IP3 132
|
||||
#define CLK_IVE_VIP 133
|
||||
#define CLK_RAW_VIP 134
|
||||
#define CLK_OSDC_VIP 135
|
||||
#define CLK_CAM0_VIP 136
|
||||
#define CLK_AXI_VIDEO_CODEC 137
|
||||
#define CLK_VC_SRC0 138
|
||||
#define CLK_VC_SRC1 139
|
||||
#define CLK_VC_SRC2 140
|
||||
#define CLK_H264C 141
|
||||
#define CLK_APB_H264C 142
|
||||
#define CLK_H265C 143
|
||||
#define CLK_APB_H265C 144
|
||||
#define CLK_JPEG 145
|
||||
#define CLK_APB_JPEG 146
|
||||
#define CLK_CAM0 147
|
||||
#define CLK_CAM1 148
|
||||
#define CLK_WGN 149
|
||||
#define CLK_WGN0 150
|
||||
#define CLK_WGN1 151
|
||||
#define CLK_WGN2 152
|
||||
#define CLK_KEYSCAN 153
|
||||
#define CLK_CFG_REG_VC 154
|
||||
#define CLK_C906_0 155
|
||||
#define CLK_C906_1 156
|
||||
#define CLK_A53 157
|
||||
#define CLK_CPU_AXI0 158
|
||||
#define CLK_CPU_GIC 159
|
||||
#define CLK_XTAL_AP 160
|
||||
|
||||
// Only for CV181x
|
||||
#define CLK_DISP_SRC_VIP 161
|
||||
|
||||
#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */
|
||||
@@ -1,12 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __STE_CLK_AB8500_H__
|
||||
#define __STE_CLK_AB8500_H__
|
||||
|
||||
#define AB8500_SYSCLK_BUF2 0
|
||||
#define AB8500_SYSCLK_BUF3 1
|
||||
#define AB8500_SYSCLK_BUF4 2
|
||||
#define AB8500_SYSCLK_ULP 3
|
||||
#define AB8500_SYSCLK_INT 4
|
||||
#define AB8500_SYSCLK_AUDIO 5
|
||||
|
||||
#endif
|
||||
@@ -1,158 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2020 huangzhenwei@allwinnertech.com
|
||||
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
|
||||
|
||||
#define CLK_PLL_CPUX 0
|
||||
#define CLK_PLL_DDR0 1
|
||||
#define CLK_PLL_PERIPH0_4X 2
|
||||
#define CLK_PLL_PERIPH0_2X 3
|
||||
#define CLK_PLL_PERIPH0_800M 4
|
||||
#define CLK_PLL_PERIPH0 5
|
||||
#define CLK_PLL_PERIPH0_DIV3 6
|
||||
#define CLK_PLL_VIDEO0_4X 7
|
||||
#define CLK_PLL_VIDEO0_2X 8
|
||||
#define CLK_PLL_VIDEO0 9
|
||||
#define CLK_PLL_VIDEO1_4X 10
|
||||
#define CLK_PLL_VIDEO1_2X 11
|
||||
#define CLK_PLL_VIDEO1 12
|
||||
#define CLK_PLL_VE 13
|
||||
#define CLK_PLL_AUDIO0_4X 14
|
||||
#define CLK_PLL_AUDIO0_2X 15
|
||||
#define CLK_PLL_AUDIO0 16
|
||||
#define CLK_PLL_AUDIO1 17
|
||||
#define CLK_PLL_AUDIO1_DIV2 18
|
||||
#define CLK_PLL_AUDIO1_DIV5 19
|
||||
#define CLK_CPUX 20
|
||||
#define CLK_CPUX_AXI 21
|
||||
#define CLK_CPUX_APB 22
|
||||
#define CLK_PSI_AHB 23
|
||||
#define CLK_APB0 24
|
||||
#define CLK_APB1 25
|
||||
#define CLK_MBUS 26
|
||||
#define CLK_DE 27
|
||||
#define CLK_BUS_DE 28
|
||||
#define CLK_DI 29
|
||||
#define CLK_BUS_DI 30
|
||||
#define CLK_G2D 31
|
||||
#define CLK_BUS_G2D 32
|
||||
#define CLK_CE 33
|
||||
#define CLK_BUS_CE 34
|
||||
#define CLK_VE 35
|
||||
#define CLK_BUS_VE 36
|
||||
#define CLK_BUS_DMA 37
|
||||
#define CLK_BUS_MSGBOX0 38
|
||||
#define CLK_BUS_MSGBOX1 39
|
||||
#define CLK_BUS_MSGBOX2 40
|
||||
#define CLK_BUS_SPINLOCK 41
|
||||
#define CLK_BUS_HSTIMER 42
|
||||
#define CLK_AVS 43
|
||||
#define CLK_BUS_DBG 44
|
||||
#define CLK_BUS_PWM 45
|
||||
#define CLK_BUS_IOMMU 46
|
||||
#define CLK_DRAM 47
|
||||
#define CLK_MBUS_DMA 48
|
||||
#define CLK_MBUS_VE 49
|
||||
#define CLK_MBUS_CE 50
|
||||
#define CLK_MBUS_TVIN 51
|
||||
#define CLK_MBUS_CSI 52
|
||||
#define CLK_MBUS_G2D 53
|
||||
#define CLK_MBUS_RISCV 54
|
||||
#define CLK_BUS_DRAM 55
|
||||
#define CLK_MMC0 56
|
||||
#define CLK_MMC1 57
|
||||
#define CLK_MMC2 58
|
||||
#define CLK_BUS_MMC0 59
|
||||
#define CLK_BUS_MMC1 60
|
||||
#define CLK_BUS_MMC2 61
|
||||
#define CLK_BUS_UART0 62
|
||||
#define CLK_BUS_UART1 63
|
||||
#define CLK_BUS_UART2 64
|
||||
#define CLK_BUS_UART3 65
|
||||
#define CLK_BUS_UART4 66
|
||||
#define CLK_BUS_UART5 67
|
||||
#define CLK_BUS_I2C0 68
|
||||
#define CLK_BUS_I2C1 69
|
||||
#define CLK_BUS_I2C2 70
|
||||
#define CLK_BUS_I2C3 71
|
||||
#define CLK_SPI0 72
|
||||
#define CLK_SPI1 73
|
||||
#define CLK_BUS_SPI0 74
|
||||
#define CLK_BUS_SPI1 75
|
||||
#define CLK_EMAC_25M 76
|
||||
#define CLK_BUS_EMAC 77
|
||||
#define CLK_IR_TX 78
|
||||
#define CLK_BUS_IR_TX 79
|
||||
#define CLK_BUS_GPADC 80
|
||||
#define CLK_BUS_THS 81
|
||||
#define CLK_I2S0 82
|
||||
#define CLK_I2S1 83
|
||||
#define CLK_I2S2 84
|
||||
#define CLK_I2S2_ASRC 85
|
||||
#define CLK_BUS_I2S0 86
|
||||
#define CLK_BUS_I2S1 87
|
||||
#define CLK_BUS_I2S2 88
|
||||
#define CLK_SPDIF_TX 89
|
||||
#define CLK_SPDIF_RX 90
|
||||
#define CLK_BUS_SPDIF 91
|
||||
#define CLK_DMIC 92
|
||||
#define CLK_BUS_DMIC 93
|
||||
#define CLK_AUDIO_DAC 94
|
||||
#define CLK_AUDIO_ADC 95
|
||||
#define CLK_BUS_AUDIO 96
|
||||
#define CLK_USB_OHCI0 97
|
||||
#define CLK_USB_OHCI1 98
|
||||
#define CLK_BUS_OHCI0 99
|
||||
#define CLK_BUS_OHCI1 100
|
||||
#define CLK_BUS_EHCI0 101
|
||||
#define CLK_BUS_EHCI1 102
|
||||
#define CLK_BUS_OTG 103
|
||||
#define CLK_BUS_LRADC 104
|
||||
#define CLK_BUS_DPSS_TOP 105
|
||||
#define CLK_HDMI_24M 106
|
||||
#define CLK_HDMI_CEC_32K 107
|
||||
#define CLK_HDMI_CEC 108
|
||||
#define CLK_BUS_HDMI 109
|
||||
#define CLK_MIPI_DSI 110
|
||||
#define CLK_BUS_MIPI_DSI 111
|
||||
#define CLK_TCON_LCD0 112
|
||||
#define CLK_BUS_TCON_LCD0 113
|
||||
#define CLK_TCON_TV 114
|
||||
#define CLK_BUS_TCON_TV 115
|
||||
#define CLK_TVE 116
|
||||
#define CLK_BUS_TVE_TOP 117
|
||||
#define CLK_BUS_TVE 118
|
||||
#define CLK_TVD 119
|
||||
#define CLK_BUS_TVD_TOP 120
|
||||
#define CLK_BUS_TVD 121
|
||||
#define CLK_LEDC 122
|
||||
#define CLK_BUS_LEDC 123
|
||||
#define CLK_CSI_TOP 124
|
||||
#define CLK_CSI_MCLK 125
|
||||
#define CLK_BUS_CSI 126
|
||||
#define CLK_TPADC 127
|
||||
#define CLK_BUS_TPADC 128
|
||||
#define CLK_BUS_TZMA 129
|
||||
#define CLK_DSP 130
|
||||
#define CLK_BUS_DSP_CFG 131
|
||||
#define CLK_RISCV 132
|
||||
#define CLK_RISCV_AXI 133
|
||||
#define CLK_BUS_RISCV_CFG 134
|
||||
#define CLK_FANOUT_24M 135
|
||||
#define CLK_FANOUT_12M 136
|
||||
#define CLK_FANOUT_16M 137
|
||||
#define CLK_FANOUT_25M 138
|
||||
#define CLK_FANOUT_32K 139
|
||||
#define CLK_FANOUT_27M 140
|
||||
#define CLK_FANOUT_PCLK 141
|
||||
#define CLK_FANOUT0 142
|
||||
#define CLK_FANOUT1 143
|
||||
#define CLK_FANOUT2 144
|
||||
#define CLK_BUS_CAN0 145
|
||||
#define CLK_BUS_CAN1 146
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
|
||||
@@ -1,19 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
|
||||
|
||||
#define CLK_R_AHB 0
|
||||
|
||||
#define CLK_BUS_R_TIMER 2
|
||||
#define CLK_BUS_R_TWD 3
|
||||
#define CLK_BUS_R_PPU 4
|
||||
#define CLK_R_IR_RX 5
|
||||
#define CLK_BUS_R_IR_RX 6
|
||||
#define CLK_BUS_R_RTC 7
|
||||
#define CLK_BUS_R_CPUCFG 8
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
|
||||
@@ -1,202 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Priit Laes <plaes@plaes.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
|
||||
#define _DT_BINDINGS_CLK_SUN4I_A10_H_
|
||||
|
||||
#define CLK_HOSC 1
|
||||
#define CLK_PLL_VIDEO0_2X 9
|
||||
#define CLK_PLL_VIDEO1_2X 18
|
||||
#define CLK_CPU 20
|
||||
|
||||
/* AHB Gates */
|
||||
#define CLK_AHB_OTG 26
|
||||
#define CLK_AHB_EHCI0 27
|
||||
#define CLK_AHB_OHCI0 28
|
||||
#define CLK_AHB_EHCI1 29
|
||||
#define CLK_AHB_OHCI1 30
|
||||
#define CLK_AHB_SS 31
|
||||
#define CLK_AHB_DMA 32
|
||||
#define CLK_AHB_BIST 33
|
||||
#define CLK_AHB_MMC0 34
|
||||
#define CLK_AHB_MMC1 35
|
||||
#define CLK_AHB_MMC2 36
|
||||
#define CLK_AHB_MMC3 37
|
||||
#define CLK_AHB_MS 38
|
||||
#define CLK_AHB_NAND 39
|
||||
#define CLK_AHB_SDRAM 40
|
||||
#define CLK_AHB_ACE 41
|
||||
#define CLK_AHB_EMAC 42
|
||||
#define CLK_AHB_TS 43
|
||||
#define CLK_AHB_SPI0 44
|
||||
#define CLK_AHB_SPI1 45
|
||||
#define CLK_AHB_SPI2 46
|
||||
#define CLK_AHB_SPI3 47
|
||||
#define CLK_AHB_PATA 48
|
||||
#define CLK_AHB_SATA 49
|
||||
#define CLK_AHB_GPS 50
|
||||
#define CLK_AHB_HSTIMER 51
|
||||
#define CLK_AHB_VE 52
|
||||
#define CLK_AHB_TVD 53
|
||||
#define CLK_AHB_TVE0 54
|
||||
#define CLK_AHB_TVE1 55
|
||||
#define CLK_AHB_LCD0 56
|
||||
#define CLK_AHB_LCD1 57
|
||||
#define CLK_AHB_CSI0 58
|
||||
#define CLK_AHB_CSI1 59
|
||||
#define CLK_AHB_HDMI0 60
|
||||
#define CLK_AHB_HDMI1 61
|
||||
#define CLK_AHB_DE_BE0 62
|
||||
#define CLK_AHB_DE_BE1 63
|
||||
#define CLK_AHB_DE_FE0 64
|
||||
#define CLK_AHB_DE_FE1 65
|
||||
#define CLK_AHB_GMAC 66
|
||||
#define CLK_AHB_MP 67
|
||||
#define CLK_AHB_GPU 68
|
||||
|
||||
/* APB0 Gates */
|
||||
#define CLK_APB0_CODEC 69
|
||||
#define CLK_APB0_SPDIF 70
|
||||
#define CLK_APB0_I2S0 71
|
||||
#define CLK_APB0_AC97 72
|
||||
#define CLK_APB0_I2S1 73
|
||||
#define CLK_APB0_PIO 74
|
||||
#define CLK_APB0_IR0 75
|
||||
#define CLK_APB0_IR1 76
|
||||
#define CLK_APB0_I2S2 77
|
||||
#define CLK_APB0_KEYPAD 78
|
||||
|
||||
/* APB1 Gates */
|
||||
#define CLK_APB1_I2C0 79
|
||||
#define CLK_APB1_I2C1 80
|
||||
#define CLK_APB1_I2C2 81
|
||||
#define CLK_APB1_I2C3 82
|
||||
#define CLK_APB1_CAN 83
|
||||
#define CLK_APB1_SCR 84
|
||||
#define CLK_APB1_PS20 85
|
||||
#define CLK_APB1_PS21 86
|
||||
#define CLK_APB1_I2C4 87
|
||||
#define CLK_APB1_UART0 88
|
||||
#define CLK_APB1_UART1 89
|
||||
#define CLK_APB1_UART2 90
|
||||
#define CLK_APB1_UART3 91
|
||||
#define CLK_APB1_UART4 92
|
||||
#define CLK_APB1_UART5 93
|
||||
#define CLK_APB1_UART6 94
|
||||
#define CLK_APB1_UART7 95
|
||||
|
||||
/* IP clocks */
|
||||
#define CLK_NAND 96
|
||||
#define CLK_MS 97
|
||||
#define CLK_MMC0 98
|
||||
#define CLK_MMC0_OUTPUT 99
|
||||
#define CLK_MMC0_SAMPLE 100
|
||||
#define CLK_MMC1 101
|
||||
#define CLK_MMC1_OUTPUT 102
|
||||
#define CLK_MMC1_SAMPLE 103
|
||||
#define CLK_MMC2 104
|
||||
#define CLK_MMC2_OUTPUT 105
|
||||
#define CLK_MMC2_SAMPLE 106
|
||||
#define CLK_MMC3 107
|
||||
#define CLK_MMC3_OUTPUT 108
|
||||
#define CLK_MMC3_SAMPLE 109
|
||||
#define CLK_TS 110
|
||||
#define CLK_SS 111
|
||||
#define CLK_SPI0 112
|
||||
#define CLK_SPI1 113
|
||||
#define CLK_SPI2 114
|
||||
#define CLK_PATA 115
|
||||
#define CLK_IR0 116
|
||||
#define CLK_IR1 117
|
||||
#define CLK_I2S0 118
|
||||
#define CLK_AC97 119
|
||||
#define CLK_SPDIF 120
|
||||
#define CLK_KEYPAD 121
|
||||
#define CLK_SATA 122
|
||||
#define CLK_USB_OHCI0 123
|
||||
#define CLK_USB_OHCI1 124
|
||||
#define CLK_USB_PHY 125
|
||||
#define CLK_GPS 126
|
||||
#define CLK_SPI3 127
|
||||
#define CLK_I2S1 128
|
||||
#define CLK_I2S2 129
|
||||
|
||||
/* DRAM Gates */
|
||||
#define CLK_DRAM_VE 130
|
||||
#define CLK_DRAM_CSI0 131
|
||||
#define CLK_DRAM_CSI1 132
|
||||
#define CLK_DRAM_TS 133
|
||||
#define CLK_DRAM_TVD 134
|
||||
#define CLK_DRAM_TVE0 135
|
||||
#define CLK_DRAM_TVE1 136
|
||||
#define CLK_DRAM_OUT 137
|
||||
#define CLK_DRAM_DE_FE1 138
|
||||
#define CLK_DRAM_DE_FE0 139
|
||||
#define CLK_DRAM_DE_BE0 140
|
||||
#define CLK_DRAM_DE_BE1 141
|
||||
#define CLK_DRAM_MP 142
|
||||
#define CLK_DRAM_ACE 143
|
||||
|
||||
/* Display Engine Clocks */
|
||||
#define CLK_DE_BE0 144
|
||||
#define CLK_DE_BE1 145
|
||||
#define CLK_DE_FE0 146
|
||||
#define CLK_DE_FE1 147
|
||||
#define CLK_DE_MP 148
|
||||
#define CLK_TCON0_CH0 149
|
||||
#define CLK_TCON1_CH0 150
|
||||
#define CLK_CSI_SCLK 151
|
||||
#define CLK_TVD_SCLK2 152
|
||||
#define CLK_TVD 153
|
||||
#define CLK_TCON0_CH1_SCLK2 154
|
||||
#define CLK_TCON0_CH1 155
|
||||
#define CLK_TCON1_CH1_SCLK2 156
|
||||
#define CLK_TCON1_CH1 157
|
||||
#define CLK_CSI0 158
|
||||
#define CLK_CSI1 159
|
||||
#define CLK_CODEC 160
|
||||
#define CLK_VE 161
|
||||
#define CLK_AVS 162
|
||||
#define CLK_ACE 163
|
||||
#define CLK_HDMI 164
|
||||
#define CLK_GPU 165
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
|
||||
@@ -1,125 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_H6_H_
|
||||
|
||||
#define CLK_PLL_PERIPH0 3
|
||||
|
||||
#define CLK_CPUX 21
|
||||
|
||||
#define CLK_APB1 26
|
||||
|
||||
#define CLK_DE 29
|
||||
#define CLK_BUS_DE 30
|
||||
#define CLK_DEINTERLACE 31
|
||||
#define CLK_BUS_DEINTERLACE 32
|
||||
#define CLK_GPU 33
|
||||
#define CLK_BUS_GPU 34
|
||||
#define CLK_CE 35
|
||||
#define CLK_BUS_CE 36
|
||||
#define CLK_VE 37
|
||||
#define CLK_BUS_VE 38
|
||||
#define CLK_EMCE 39
|
||||
#define CLK_BUS_EMCE 40
|
||||
#define CLK_VP9 41
|
||||
#define CLK_BUS_VP9 42
|
||||
#define CLK_BUS_DMA 43
|
||||
#define CLK_BUS_MSGBOX 44
|
||||
#define CLK_BUS_SPINLOCK 45
|
||||
#define CLK_BUS_HSTIMER 46
|
||||
#define CLK_AVS 47
|
||||
#define CLK_BUS_DBG 48
|
||||
#define CLK_BUS_PSI 49
|
||||
#define CLK_BUS_PWM 50
|
||||
#define CLK_BUS_IOMMU 51
|
||||
|
||||
#define CLK_MBUS_DMA 53
|
||||
#define CLK_MBUS_VE 54
|
||||
#define CLK_MBUS_CE 55
|
||||
#define CLK_MBUS_TS 56
|
||||
#define CLK_MBUS_NAND 57
|
||||
#define CLK_MBUS_CSI 58
|
||||
#define CLK_MBUS_DEINTERLACE 59
|
||||
|
||||
#define CLK_NAND0 61
|
||||
#define CLK_NAND1 62
|
||||
#define CLK_BUS_NAND 63
|
||||
#define CLK_MMC0 64
|
||||
#define CLK_MMC1 65
|
||||
#define CLK_MMC2 66
|
||||
#define CLK_BUS_MMC0 67
|
||||
#define CLK_BUS_MMC1 68
|
||||
#define CLK_BUS_MMC2 69
|
||||
#define CLK_BUS_UART0 70
|
||||
#define CLK_BUS_UART1 71
|
||||
#define CLK_BUS_UART2 72
|
||||
#define CLK_BUS_UART3 73
|
||||
#define CLK_BUS_I2C0 74
|
||||
#define CLK_BUS_I2C1 75
|
||||
#define CLK_BUS_I2C2 76
|
||||
#define CLK_BUS_I2C3 77
|
||||
#define CLK_BUS_SCR0 78
|
||||
#define CLK_BUS_SCR1 79
|
||||
#define CLK_SPI0 80
|
||||
#define CLK_SPI1 81
|
||||
#define CLK_BUS_SPI0 82
|
||||
#define CLK_BUS_SPI1 83
|
||||
#define CLK_BUS_EMAC 84
|
||||
#define CLK_TS 85
|
||||
#define CLK_BUS_TS 86
|
||||
#define CLK_IR_TX 87
|
||||
#define CLK_BUS_IR_TX 88
|
||||
#define CLK_BUS_THS 89
|
||||
#define CLK_I2S3 90
|
||||
#define CLK_I2S0 91
|
||||
#define CLK_I2S1 92
|
||||
#define CLK_I2S2 93
|
||||
#define CLK_BUS_I2S0 94
|
||||
#define CLK_BUS_I2S1 95
|
||||
#define CLK_BUS_I2S2 96
|
||||
#define CLK_BUS_I2S3 97
|
||||
#define CLK_SPDIF 98
|
||||
#define CLK_BUS_SPDIF 99
|
||||
#define CLK_DMIC 100
|
||||
#define CLK_BUS_DMIC 101
|
||||
#define CLK_AUDIO_HUB 102
|
||||
#define CLK_BUS_AUDIO_HUB 103
|
||||
#define CLK_USB_OHCI0 104
|
||||
#define CLK_USB_PHY0 105
|
||||
#define CLK_USB_PHY1 106
|
||||
#define CLK_USB_OHCI3 107
|
||||
#define CLK_USB_PHY3 108
|
||||
#define CLK_USB_HSIC_12M 109
|
||||
#define CLK_USB_HSIC 110
|
||||
#define CLK_BUS_OHCI0 111
|
||||
#define CLK_BUS_OHCI3 112
|
||||
#define CLK_BUS_EHCI0 113
|
||||
#define CLK_BUS_XHCI 114
|
||||
#define CLK_BUS_EHCI3 115
|
||||
#define CLK_BUS_OTG 116
|
||||
#define CLK_PCIE_REF_100M 117
|
||||
#define CLK_PCIE_REF 118
|
||||
#define CLK_PCIE_REF_OUT 119
|
||||
#define CLK_PCIE_MAXI 120
|
||||
#define CLK_PCIE_AUX 121
|
||||
#define CLK_BUS_PCIE 122
|
||||
#define CLK_HDMI 123
|
||||
#define CLK_HDMI_SLOW 124
|
||||
#define CLK_HDMI_CEC 125
|
||||
#define CLK_BUS_HDMI 126
|
||||
#define CLK_BUS_TCON_TOP 127
|
||||
#define CLK_TCON_LCD0 128
|
||||
#define CLK_BUS_TCON_LCD0 129
|
||||
#define CLK_TCON_TV0 130
|
||||
#define CLK_BUS_TCON_TV0 131
|
||||
#define CLK_CSI_CCI 132
|
||||
#define CLK_CSI_TOP 133
|
||||
#define CLK_CSI_MCLK 134
|
||||
#define CLK_BUS_CSI 135
|
||||
#define CLK_HDCP 136
|
||||
#define CLK_BUS_HDCP 137
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
|
||||
@@ -1,27 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
|
||||
|
||||
#define CLK_AR100 0
|
||||
|
||||
#define CLK_R_APB1 2
|
||||
|
||||
#define CLK_R_APB1_TIMER 4
|
||||
#define CLK_R_APB1_TWD 5
|
||||
#define CLK_R_APB1_PWM 6
|
||||
#define CLK_R_APB2_UART 7
|
||||
#define CLK_R_APB2_I2C 8
|
||||
#define CLK_R_APB1_IR 9
|
||||
#define CLK_R_APB1_W1 10
|
||||
|
||||
#define CLK_IR 11
|
||||
#define CLK_W1 12
|
||||
|
||||
#define CLK_R_APB2_RSB 13
|
||||
#define CLK_R_APB1_RTC 14
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
|
||||
@@ -1,97 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2016 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN5I_H_
|
||||
#define _DT_BINDINGS_CLK_SUN5I_H_
|
||||
|
||||
#define CLK_HOSC 1
|
||||
|
||||
#define CLK_PLL_VIDEO0_2X 9
|
||||
|
||||
#define CLK_PLL_VIDEO1_2X 16
|
||||
#define CLK_CPU 17
|
||||
|
||||
#define CLK_AHB_OTG 23
|
||||
#define CLK_AHB_EHCI 24
|
||||
#define CLK_AHB_OHCI 25
|
||||
#define CLK_AHB_SS 26
|
||||
#define CLK_AHB_DMA 27
|
||||
#define CLK_AHB_BIST 28
|
||||
#define CLK_AHB_MMC0 29
|
||||
#define CLK_AHB_MMC1 30
|
||||
#define CLK_AHB_MMC2 31
|
||||
#define CLK_AHB_NAND 32
|
||||
#define CLK_AHB_SDRAM 33
|
||||
#define CLK_AHB_EMAC 34
|
||||
#define CLK_AHB_TS 35
|
||||
#define CLK_AHB_SPI0 36
|
||||
#define CLK_AHB_SPI1 37
|
||||
#define CLK_AHB_SPI2 38
|
||||
#define CLK_AHB_GPS 39
|
||||
#define CLK_AHB_HSTIMER 40
|
||||
#define CLK_AHB_VE 41
|
||||
#define CLK_AHB_TVE 42
|
||||
#define CLK_AHB_LCD 43
|
||||
#define CLK_AHB_CSI 44
|
||||
#define CLK_AHB_HDMI 45
|
||||
#define CLK_AHB_DE_BE 46
|
||||
#define CLK_AHB_DE_FE 47
|
||||
#define CLK_AHB_IEP 48
|
||||
#define CLK_AHB_GPU 49
|
||||
#define CLK_APB0_CODEC 50
|
||||
#define CLK_APB0_SPDIF 51
|
||||
#define CLK_APB0_I2S 52
|
||||
#define CLK_APB0_PIO 53
|
||||
#define CLK_APB0_IR 54
|
||||
#define CLK_APB0_KEYPAD 55
|
||||
#define CLK_APB1_I2C0 56
|
||||
#define CLK_APB1_I2C1 57
|
||||
#define CLK_APB1_I2C2 58
|
||||
#define CLK_APB1_UART0 59
|
||||
#define CLK_APB1_UART1 60
|
||||
#define CLK_APB1_UART2 61
|
||||
#define CLK_APB1_UART3 62
|
||||
#define CLK_NAND 63
|
||||
#define CLK_MMC0 64
|
||||
#define CLK_MMC1 65
|
||||
#define CLK_MMC2 66
|
||||
#define CLK_TS 67
|
||||
#define CLK_SS 68
|
||||
#define CLK_SPI0 69
|
||||
#define CLK_SPI1 70
|
||||
#define CLK_SPI2 71
|
||||
#define CLK_IR 72
|
||||
#define CLK_I2S 73
|
||||
#define CLK_SPDIF 74
|
||||
#define CLK_KEYPAD 75
|
||||
#define CLK_USB_OHCI 76
|
||||
#define CLK_USB_PHY0 77
|
||||
#define CLK_USB_PHY1 78
|
||||
#define CLK_GPS 79
|
||||
#define CLK_DRAM_VE 80
|
||||
#define CLK_DRAM_CSI 81
|
||||
#define CLK_DRAM_TS 82
|
||||
#define CLK_DRAM_TVE 83
|
||||
#define CLK_DRAM_DE_FE 84
|
||||
#define CLK_DRAM_DE_BE 85
|
||||
#define CLK_DRAM_ACE 86
|
||||
#define CLK_DRAM_IEP 87
|
||||
#define CLK_DE_BE 88
|
||||
#define CLK_DE_FE 89
|
||||
#define CLK_TCON_CH0 90
|
||||
|
||||
#define CLK_TCON_CH1 92
|
||||
#define CLK_CSI 93
|
||||
#define CLK_VE 94
|
||||
#define CLK_CODEC 95
|
||||
#define CLK_AVS 96
|
||||
#define CLK_HDMI 97
|
||||
#define CLK_GPU 98
|
||||
#define CLK_MBUS 99
|
||||
#define CLK_IEP 100
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
|
||||
@@ -1,193 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
|
||||
#define _DT_BINDINGS_CLK_SUN6I_A31_H_
|
||||
|
||||
#define CLK_PLL_VIDEO0_2X 7
|
||||
|
||||
#define CLK_PLL_PERIPH 10
|
||||
|
||||
#define CLK_PLL_VIDEO1_2X 13
|
||||
|
||||
#define CLK_PLL_MIPI 15
|
||||
|
||||
#define CLK_CPU 18
|
||||
|
||||
#define CLK_AHB1_MIPIDSI 23
|
||||
#define CLK_AHB1_SS 24
|
||||
#define CLK_AHB1_DMA 25
|
||||
#define CLK_AHB1_MMC0 26
|
||||
#define CLK_AHB1_MMC1 27
|
||||
#define CLK_AHB1_MMC2 28
|
||||
#define CLK_AHB1_MMC3 29
|
||||
#define CLK_AHB1_NAND1 30
|
||||
#define CLK_AHB1_NAND0 31
|
||||
#define CLK_AHB1_SDRAM 32
|
||||
#define CLK_AHB1_EMAC 33
|
||||
#define CLK_AHB1_TS 34
|
||||
#define CLK_AHB1_HSTIMER 35
|
||||
#define CLK_AHB1_SPI0 36
|
||||
#define CLK_AHB1_SPI1 37
|
||||
#define CLK_AHB1_SPI2 38
|
||||
#define CLK_AHB1_SPI3 39
|
||||
#define CLK_AHB1_OTG 40
|
||||
#define CLK_AHB1_EHCI0 41
|
||||
#define CLK_AHB1_EHCI1 42
|
||||
#define CLK_AHB1_OHCI0 43
|
||||
#define CLK_AHB1_OHCI1 44
|
||||
#define CLK_AHB1_OHCI2 45
|
||||
#define CLK_AHB1_VE 46
|
||||
#define CLK_AHB1_LCD0 47
|
||||
#define CLK_AHB1_LCD1 48
|
||||
#define CLK_AHB1_CSI 49
|
||||
#define CLK_AHB1_HDMI 50
|
||||
#define CLK_AHB1_BE0 51
|
||||
#define CLK_AHB1_BE1 52
|
||||
#define CLK_AHB1_FE0 53
|
||||
#define CLK_AHB1_FE1 54
|
||||
#define CLK_AHB1_MP 55
|
||||
#define CLK_AHB1_GPU 56
|
||||
#define CLK_AHB1_DEU0 57
|
||||
#define CLK_AHB1_DEU1 58
|
||||
#define CLK_AHB1_DRC0 59
|
||||
#define CLK_AHB1_DRC1 60
|
||||
|
||||
#define CLK_APB1_CODEC 61
|
||||
#define CLK_APB1_SPDIF 62
|
||||
#define CLK_APB1_DIGITAL_MIC 63
|
||||
#define CLK_APB1_PIO 64
|
||||
#define CLK_APB1_DAUDIO0 65
|
||||
#define CLK_APB1_DAUDIO1 66
|
||||
|
||||
#define CLK_APB2_I2C0 67
|
||||
#define CLK_APB2_I2C1 68
|
||||
#define CLK_APB2_I2C2 69
|
||||
#define CLK_APB2_I2C3 70
|
||||
#define CLK_APB2_UART0 71
|
||||
#define CLK_APB2_UART1 72
|
||||
#define CLK_APB2_UART2 73
|
||||
#define CLK_APB2_UART3 74
|
||||
#define CLK_APB2_UART4 75
|
||||
#define CLK_APB2_UART5 76
|
||||
|
||||
#define CLK_NAND0 77
|
||||
#define CLK_NAND1 78
|
||||
#define CLK_MMC0 79
|
||||
#define CLK_MMC0_SAMPLE 80
|
||||
#define CLK_MMC0_OUTPUT 81
|
||||
#define CLK_MMC1 82
|
||||
#define CLK_MMC1_SAMPLE 83
|
||||
#define CLK_MMC1_OUTPUT 84
|
||||
#define CLK_MMC2 85
|
||||
#define CLK_MMC2_SAMPLE 86
|
||||
#define CLK_MMC2_OUTPUT 87
|
||||
#define CLK_MMC3 88
|
||||
#define CLK_MMC3_SAMPLE 89
|
||||
#define CLK_MMC3_OUTPUT 90
|
||||
#define CLK_TS 91
|
||||
#define CLK_SS 92
|
||||
#define CLK_SPI0 93
|
||||
#define CLK_SPI1 94
|
||||
#define CLK_SPI2 95
|
||||
#define CLK_SPI3 96
|
||||
#define CLK_DAUDIO0 97
|
||||
#define CLK_DAUDIO1 98
|
||||
#define CLK_SPDIF 99
|
||||
#define CLK_USB_PHY0 100
|
||||
#define CLK_USB_PHY1 101
|
||||
#define CLK_USB_PHY2 102
|
||||
#define CLK_USB_OHCI0 103
|
||||
#define CLK_USB_OHCI1 104
|
||||
#define CLK_USB_OHCI2 105
|
||||
|
||||
#define CLK_DRAM_VE 110
|
||||
#define CLK_DRAM_CSI_ISP 111
|
||||
#define CLK_DRAM_TS 112
|
||||
#define CLK_DRAM_DRC0 113
|
||||
#define CLK_DRAM_DRC1 114
|
||||
#define CLK_DRAM_DEU0 115
|
||||
#define CLK_DRAM_DEU1 116
|
||||
#define CLK_DRAM_FE0 117
|
||||
#define CLK_DRAM_FE1 118
|
||||
#define CLK_DRAM_BE0 119
|
||||
#define CLK_DRAM_BE1 120
|
||||
#define CLK_DRAM_MP 121
|
||||
|
||||
#define CLK_BE0 122
|
||||
#define CLK_BE1 123
|
||||
#define CLK_FE0 124
|
||||
#define CLK_FE1 125
|
||||
#define CLK_MP 126
|
||||
#define CLK_LCD0_CH0 127
|
||||
#define CLK_LCD1_CH0 128
|
||||
#define CLK_LCD0_CH1 129
|
||||
#define CLK_LCD1_CH1 130
|
||||
#define CLK_CSI0_SCLK 131
|
||||
#define CLK_CSI0_MCLK 132
|
||||
#define CLK_CSI1_MCLK 133
|
||||
#define CLK_VE 134
|
||||
#define CLK_CODEC 135
|
||||
#define CLK_AVS 136
|
||||
#define CLK_DIGITAL_MIC 137
|
||||
#define CLK_HDMI 138
|
||||
#define CLK_HDMI_DDC 139
|
||||
#define CLK_PS 140
|
||||
|
||||
#define CLK_MIPI_DSI 143
|
||||
#define CLK_MIPI_DSI_DPHY 144
|
||||
#define CLK_MIPI_CSI_DPHY 145
|
||||
#define CLK_IEP_DRC0 146
|
||||
#define CLK_IEP_DRC1 147
|
||||
#define CLK_IEP_DEU0 148
|
||||
#define CLK_IEP_DEU1 149
|
||||
#define CLK_GPU_CORE 150
|
||||
#define CLK_GPU_MEMORY 151
|
||||
#define CLK_GPU_HYD 152
|
||||
#define CLK_ATS 153
|
||||
#define CLK_TRACE 154
|
||||
|
||||
#define CLK_OUT_A 155
|
||||
#define CLK_OUT_B 156
|
||||
#define CLK_OUT_C 157
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
|
||||
@@ -1,10 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_
|
||||
#define _DT_BINDINGS_CLK_SUN6I_RTC_H_
|
||||
|
||||
#define CLK_OSC32K 0
|
||||
#define CLK_OSC32K_FANOUT 1
|
||||
#define CLK_IOSC 2
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */
|
||||
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Priit Laes <plaes@plaes.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_
|
||||
#define _DT_BINDINGS_CLK_SUN7I_A20_H_
|
||||
|
||||
#include <dt-bindings/clock/sun4i-a10-ccu.h>
|
||||
|
||||
#define CLK_MBUS 166
|
||||
#define CLK_HDMI1_SLOW 167
|
||||
#define CLK_HDMI1 168
|
||||
#define CLK_OUT_A 169
|
||||
#define CLK_OUT_B 170
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */
|
||||
@@ -1,129 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
|
||||
|
||||
#define CLK_PLL_MIPI 13
|
||||
|
||||
#define CLK_CPUX 18
|
||||
|
||||
#define CLK_BUS_MIPI_DSI 23
|
||||
#define CLK_BUS_SS 24
|
||||
#define CLK_BUS_DMA 25
|
||||
#define CLK_BUS_MMC0 26
|
||||
#define CLK_BUS_MMC1 27
|
||||
#define CLK_BUS_MMC2 28
|
||||
#define CLK_BUS_NAND 29
|
||||
#define CLK_BUS_DRAM 30
|
||||
#define CLK_BUS_HSTIMER 31
|
||||
#define CLK_BUS_SPI0 32
|
||||
#define CLK_BUS_SPI1 33
|
||||
#define CLK_BUS_OTG 34
|
||||
#define CLK_BUS_EHCI 35
|
||||
#define CLK_BUS_OHCI 36
|
||||
#define CLK_BUS_VE 37
|
||||
#define CLK_BUS_LCD 38
|
||||
#define CLK_BUS_CSI 39
|
||||
#define CLK_BUS_DE_BE 40
|
||||
#define CLK_BUS_DE_FE 41
|
||||
#define CLK_BUS_GPU 42
|
||||
#define CLK_BUS_MSGBOX 43
|
||||
#define CLK_BUS_SPINLOCK 44
|
||||
#define CLK_BUS_DRC 45
|
||||
#define CLK_BUS_SAT 46
|
||||
#define CLK_BUS_CODEC 47
|
||||
#define CLK_BUS_PIO 48
|
||||
#define CLK_BUS_I2S0 49
|
||||
#define CLK_BUS_I2S1 50
|
||||
#define CLK_BUS_I2C0 51
|
||||
#define CLK_BUS_I2C1 52
|
||||
#define CLK_BUS_I2C2 53
|
||||
#define CLK_BUS_UART0 54
|
||||
#define CLK_BUS_UART1 55
|
||||
#define CLK_BUS_UART2 56
|
||||
#define CLK_BUS_UART3 57
|
||||
#define CLK_BUS_UART4 58
|
||||
#define CLK_NAND 59
|
||||
#define CLK_MMC0 60
|
||||
#define CLK_MMC0_SAMPLE 61
|
||||
#define CLK_MMC0_OUTPUT 62
|
||||
#define CLK_MMC1 63
|
||||
#define CLK_MMC1_SAMPLE 64
|
||||
#define CLK_MMC1_OUTPUT 65
|
||||
#define CLK_MMC2 66
|
||||
#define CLK_MMC2_SAMPLE 67
|
||||
#define CLK_MMC2_OUTPUT 68
|
||||
#define CLK_SS 69
|
||||
#define CLK_SPI0 70
|
||||
#define CLK_SPI1 71
|
||||
#define CLK_I2S0 72
|
||||
#define CLK_I2S1 73
|
||||
#define CLK_USB_PHY0 74
|
||||
#define CLK_USB_PHY1 75
|
||||
#define CLK_USB_HSIC 76
|
||||
#define CLK_USB_HSIC_12M 77
|
||||
#define CLK_USB_OHCI 78
|
||||
|
||||
#define CLK_DRAM_VE 80
|
||||
#define CLK_DRAM_CSI 81
|
||||
#define CLK_DRAM_DRC 82
|
||||
#define CLK_DRAM_DE_FE 83
|
||||
#define CLK_DRAM_DE_BE 84
|
||||
#define CLK_DE_BE 85
|
||||
#define CLK_DE_FE 86
|
||||
#define CLK_LCD_CH0 87
|
||||
#define CLK_LCD_CH1 88
|
||||
#define CLK_CSI_SCLK 89
|
||||
#define CLK_CSI_MCLK 90
|
||||
#define CLK_VE 91
|
||||
#define CLK_AC_DIG 92
|
||||
#define CLK_AC_DIG_4X 93
|
||||
#define CLK_AVS 94
|
||||
|
||||
#define CLK_DSI_SCLK 96
|
||||
#define CLK_DSI_DPHY 97
|
||||
#define CLK_DRC 98
|
||||
#define CLK_GPU 99
|
||||
#define CLK_ATS 100
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */
|
||||
@@ -1,140 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
|
||||
|
||||
#define CLK_PLL_PERIPH 6
|
||||
|
||||
#define CLK_PLL_DE 9
|
||||
|
||||
#define CLK_C0CPUX 11
|
||||
#define CLK_C1CPUX 12
|
||||
|
||||
#define CLK_BUS_MIPI_DSI 19
|
||||
#define CLK_BUS_SS 20
|
||||
#define CLK_BUS_DMA 21
|
||||
#define CLK_BUS_MMC0 22
|
||||
#define CLK_BUS_MMC1 23
|
||||
#define CLK_BUS_MMC2 24
|
||||
#define CLK_BUS_NAND 25
|
||||
#define CLK_BUS_DRAM 26
|
||||
#define CLK_BUS_EMAC 27
|
||||
#define CLK_BUS_HSTIMER 28
|
||||
#define CLK_BUS_SPI0 29
|
||||
#define CLK_BUS_SPI1 30
|
||||
#define CLK_BUS_OTG 31
|
||||
#define CLK_BUS_EHCI0 32
|
||||
#define CLK_BUS_EHCI1 33
|
||||
#define CLK_BUS_OHCI0 34
|
||||
|
||||
#define CLK_BUS_VE 35
|
||||
#define CLK_BUS_TCON0 36
|
||||
#define CLK_BUS_TCON1 37
|
||||
#define CLK_BUS_CSI 38
|
||||
#define CLK_BUS_HDMI 39
|
||||
#define CLK_BUS_DE 40
|
||||
#define CLK_BUS_GPU 41
|
||||
#define CLK_BUS_MSGBOX 42
|
||||
#define CLK_BUS_SPINLOCK 43
|
||||
|
||||
#define CLK_BUS_SPDIF 44
|
||||
#define CLK_BUS_PIO 45
|
||||
#define CLK_BUS_I2S0 46
|
||||
#define CLK_BUS_I2S1 47
|
||||
#define CLK_BUS_I2S2 48
|
||||
#define CLK_BUS_TDM 49
|
||||
|
||||
#define CLK_BUS_I2C0 50
|
||||
#define CLK_BUS_I2C1 51
|
||||
#define CLK_BUS_I2C2 52
|
||||
#define CLK_BUS_UART0 53
|
||||
#define CLK_BUS_UART1 54
|
||||
#define CLK_BUS_UART2 55
|
||||
#define CLK_BUS_UART3 56
|
||||
#define CLK_BUS_UART4 57
|
||||
|
||||
#define CLK_NAND 59
|
||||
#define CLK_MMC0 60
|
||||
#define CLK_MMC0_SAMPLE 61
|
||||
#define CLK_MMC0_OUTPUT 62
|
||||
#define CLK_MMC1 63
|
||||
#define CLK_MMC1_SAMPLE 64
|
||||
#define CLK_MMC1_OUTPUT 65
|
||||
#define CLK_MMC2 66
|
||||
#define CLK_MMC2_SAMPLE 67
|
||||
#define CLK_MMC2_OUTPUT 68
|
||||
#define CLK_SS 69
|
||||
#define CLK_SPI0 70
|
||||
#define CLK_SPI1 71
|
||||
#define CLK_I2S0 72
|
||||
#define CLK_I2S1 73
|
||||
#define CLK_I2S2 74
|
||||
#define CLK_TDM 75
|
||||
#define CLK_SPDIF 76
|
||||
#define CLK_USB_PHY0 77
|
||||
#define CLK_USB_PHY1 78
|
||||
#define CLK_USB_HSIC 79
|
||||
#define CLK_USB_HSIC_12M 80
|
||||
#define CLK_USB_OHCI0 81
|
||||
|
||||
#define CLK_DRAM_VE 83
|
||||
#define CLK_DRAM_CSI 84
|
||||
|
||||
#define CLK_TCON0 85
|
||||
#define CLK_TCON1 86
|
||||
#define CLK_CSI_MISC 87
|
||||
#define CLK_MIPI_CSI 88
|
||||
#define CLK_CSI_MCLK 89
|
||||
#define CLK_CSI_SCLK 90
|
||||
#define CLK_VE 91
|
||||
#define CLK_AVS 92
|
||||
#define CLK_HDMI 93
|
||||
#define CLK_HDMI_SLOW 94
|
||||
|
||||
#define CLK_MIPI_DSI0 96
|
||||
#define CLK_MIPI_DSI1 97
|
||||
#define CLK_GPU_CORE 98
|
||||
#define CLK_GPU_MEMORY 99
|
||||
#define CLK_GPU_HYD 100
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_
|
||||
|
||||
#define CLK_BUS_MIXER0 0
|
||||
#define CLK_BUS_MIXER1 1
|
||||
#define CLK_BUS_WB 2
|
||||
|
||||
#define CLK_MIXER0 6
|
||||
#define CLK_MIXER1 7
|
||||
#define CLK_WB 8
|
||||
|
||||
#define CLK_BUS_ROT 9
|
||||
#define CLK_ROT 10
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */
|
||||
@@ -1,152 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
|
||||
|
||||
#define CLK_PLL_VIDEO 6
|
||||
|
||||
#define CLK_PLL_PERIPH0 9
|
||||
|
||||
#define CLK_CPUX 14
|
||||
|
||||
#define CLK_BUS_CE 20
|
||||
#define CLK_BUS_DMA 21
|
||||
#define CLK_BUS_MMC0 22
|
||||
#define CLK_BUS_MMC1 23
|
||||
#define CLK_BUS_MMC2 24
|
||||
#define CLK_BUS_NAND 25
|
||||
#define CLK_BUS_DRAM 26
|
||||
#define CLK_BUS_EMAC 27
|
||||
#define CLK_BUS_TS 28
|
||||
#define CLK_BUS_HSTIMER 29
|
||||
#define CLK_BUS_SPI0 30
|
||||
#define CLK_BUS_SPI1 31
|
||||
#define CLK_BUS_OTG 32
|
||||
#define CLK_BUS_EHCI0 33
|
||||
#define CLK_BUS_EHCI1 34
|
||||
#define CLK_BUS_EHCI2 35
|
||||
#define CLK_BUS_EHCI3 36
|
||||
#define CLK_BUS_OHCI0 37
|
||||
#define CLK_BUS_OHCI1 38
|
||||
#define CLK_BUS_OHCI2 39
|
||||
#define CLK_BUS_OHCI3 40
|
||||
#define CLK_BUS_VE 41
|
||||
#define CLK_BUS_TCON0 42
|
||||
#define CLK_BUS_TCON1 43
|
||||
#define CLK_BUS_DEINTERLACE 44
|
||||
#define CLK_BUS_CSI 45
|
||||
#define CLK_BUS_TVE 46
|
||||
#define CLK_BUS_HDMI 47
|
||||
#define CLK_BUS_DE 48
|
||||
#define CLK_BUS_GPU 49
|
||||
#define CLK_BUS_MSGBOX 50
|
||||
#define CLK_BUS_SPINLOCK 51
|
||||
#define CLK_BUS_CODEC 52
|
||||
#define CLK_BUS_SPDIF 53
|
||||
#define CLK_BUS_PIO 54
|
||||
#define CLK_BUS_THS 55
|
||||
#define CLK_BUS_I2S0 56
|
||||
#define CLK_BUS_I2S1 57
|
||||
#define CLK_BUS_I2S2 58
|
||||
#define CLK_BUS_I2C0 59
|
||||
#define CLK_BUS_I2C1 60
|
||||
#define CLK_BUS_I2C2 61
|
||||
#define CLK_BUS_UART0 62
|
||||
#define CLK_BUS_UART1 63
|
||||
#define CLK_BUS_UART2 64
|
||||
#define CLK_BUS_UART3 65
|
||||
#define CLK_BUS_SCR0 66
|
||||
#define CLK_BUS_EPHY 67
|
||||
#define CLK_BUS_DBG 68
|
||||
|
||||
#define CLK_THS 69
|
||||
#define CLK_NAND 70
|
||||
#define CLK_MMC0 71
|
||||
#define CLK_MMC0_SAMPLE 72
|
||||
#define CLK_MMC0_OUTPUT 73
|
||||
#define CLK_MMC1 74
|
||||
#define CLK_MMC1_SAMPLE 75
|
||||
#define CLK_MMC1_OUTPUT 76
|
||||
#define CLK_MMC2 77
|
||||
#define CLK_MMC2_SAMPLE 78
|
||||
#define CLK_MMC2_OUTPUT 79
|
||||
#define CLK_TS 80
|
||||
#define CLK_CE 81
|
||||
#define CLK_SPI0 82
|
||||
#define CLK_SPI1 83
|
||||
#define CLK_I2S0 84
|
||||
#define CLK_I2S1 85
|
||||
#define CLK_I2S2 86
|
||||
#define CLK_SPDIF 87
|
||||
#define CLK_USB_PHY0 88
|
||||
#define CLK_USB_PHY1 89
|
||||
#define CLK_USB_PHY2 90
|
||||
#define CLK_USB_PHY3 91
|
||||
#define CLK_USB_OHCI0 92
|
||||
#define CLK_USB_OHCI1 93
|
||||
#define CLK_USB_OHCI2 94
|
||||
#define CLK_USB_OHCI3 95
|
||||
#define CLK_DRAM 96
|
||||
#define CLK_DRAM_VE 97
|
||||
#define CLK_DRAM_CSI 98
|
||||
#define CLK_DRAM_DEINTERLACE 99
|
||||
#define CLK_DRAM_TS 100
|
||||
#define CLK_DE 101
|
||||
#define CLK_TCON0 102
|
||||
#define CLK_TVE 103
|
||||
#define CLK_DEINTERLACE 104
|
||||
#define CLK_CSI_MISC 105
|
||||
#define CLK_CSI_SCLK 106
|
||||
#define CLK_CSI_MCLK 107
|
||||
#define CLK_VE 108
|
||||
#define CLK_AC_DIG 109
|
||||
#define CLK_AVS 110
|
||||
#define CLK_HDMI 111
|
||||
#define CLK_HDMI_DDC 112
|
||||
#define CLK_MBUS 113
|
||||
#define CLK_GPU 114
|
||||
|
||||
/* New clocks imported in H5 */
|
||||
#define CLK_BUS_SCR1 115
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
|
||||
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
|
||||
|
||||
#define CLK_AR100 0
|
||||
|
||||
#define CLK_APB0_PIO 3
|
||||
#define CLK_APB0_IR 4
|
||||
#define CLK_APB0_TIMER 5
|
||||
#define CLK_APB0_RSB 6
|
||||
#define CLK_APB0_UART 7
|
||||
/* 8 is reserved for CLK_APB0_W1 on A31 */
|
||||
#define CLK_APB0_I2C 9
|
||||
#define CLK_APB0_TWD 10
|
||||
|
||||
#define CLK_IR 11
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
|
||||
@@ -1,191 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
|
||||
|
||||
#define CLK_PLL_VIDEO0 7
|
||||
|
||||
#define CLK_PLL_VIDEO1 16
|
||||
|
||||
#define CLK_CPU 24
|
||||
|
||||
#define CLK_BUS_MIPI_DSI 29
|
||||
#define CLK_BUS_CE 30
|
||||
#define CLK_BUS_DMA 31
|
||||
#define CLK_BUS_MMC0 32
|
||||
#define CLK_BUS_MMC1 33
|
||||
#define CLK_BUS_MMC2 34
|
||||
#define CLK_BUS_MMC3 35
|
||||
#define CLK_BUS_NAND 36
|
||||
#define CLK_BUS_DRAM 37
|
||||
#define CLK_BUS_EMAC 38
|
||||
#define CLK_BUS_TS 39
|
||||
#define CLK_BUS_HSTIMER 40
|
||||
#define CLK_BUS_SPI0 41
|
||||
#define CLK_BUS_SPI1 42
|
||||
#define CLK_BUS_SPI2 43
|
||||
#define CLK_BUS_SPI3 44
|
||||
#define CLK_BUS_SATA 45
|
||||
#define CLK_BUS_OTG 46
|
||||
#define CLK_BUS_EHCI0 47
|
||||
#define CLK_BUS_EHCI1 48
|
||||
#define CLK_BUS_EHCI2 49
|
||||
#define CLK_BUS_OHCI0 50
|
||||
#define CLK_BUS_OHCI1 51
|
||||
#define CLK_BUS_OHCI2 52
|
||||
#define CLK_BUS_VE 53
|
||||
#define CLK_BUS_MP 54
|
||||
#define CLK_BUS_DEINTERLACE 55
|
||||
#define CLK_BUS_CSI0 56
|
||||
#define CLK_BUS_CSI1 57
|
||||
#define CLK_BUS_HDMI1 58
|
||||
#define CLK_BUS_HDMI0 59
|
||||
#define CLK_BUS_DE 60
|
||||
#define CLK_BUS_TVE0 61
|
||||
#define CLK_BUS_TVE1 62
|
||||
#define CLK_BUS_TVE_TOP 63
|
||||
#define CLK_BUS_GMAC 64
|
||||
#define CLK_BUS_GPU 65
|
||||
#define CLK_BUS_TVD0 66
|
||||
#define CLK_BUS_TVD1 67
|
||||
#define CLK_BUS_TVD2 68
|
||||
#define CLK_BUS_TVD3 69
|
||||
#define CLK_BUS_TVD_TOP 70
|
||||
#define CLK_BUS_TCON_LCD0 71
|
||||
#define CLK_BUS_TCON_LCD1 72
|
||||
#define CLK_BUS_TCON_TV0 73
|
||||
#define CLK_BUS_TCON_TV1 74
|
||||
#define CLK_BUS_TCON_TOP 75
|
||||
#define CLK_BUS_CODEC 76
|
||||
#define CLK_BUS_SPDIF 77
|
||||
#define CLK_BUS_AC97 78
|
||||
#define CLK_BUS_PIO 79
|
||||
#define CLK_BUS_IR0 80
|
||||
#define CLK_BUS_IR1 81
|
||||
#define CLK_BUS_THS 82
|
||||
#define CLK_BUS_KEYPAD 83
|
||||
#define CLK_BUS_I2S0 84
|
||||
#define CLK_BUS_I2S1 85
|
||||
#define CLK_BUS_I2S2 86
|
||||
#define CLK_BUS_I2C0 87
|
||||
#define CLK_BUS_I2C1 88
|
||||
#define CLK_BUS_I2C2 89
|
||||
#define CLK_BUS_I2C3 90
|
||||
#define CLK_BUS_CAN 91
|
||||
#define CLK_BUS_SCR 92
|
||||
#define CLK_BUS_PS20 93
|
||||
#define CLK_BUS_PS21 94
|
||||
#define CLK_BUS_I2C4 95
|
||||
#define CLK_BUS_UART0 96
|
||||
#define CLK_BUS_UART1 97
|
||||
#define CLK_BUS_UART2 98
|
||||
#define CLK_BUS_UART3 99
|
||||
#define CLK_BUS_UART4 100
|
||||
#define CLK_BUS_UART5 101
|
||||
#define CLK_BUS_UART6 102
|
||||
#define CLK_BUS_UART7 103
|
||||
#define CLK_BUS_DBG 104
|
||||
|
||||
#define CLK_THS 105
|
||||
#define CLK_NAND 106
|
||||
#define CLK_MMC0 107
|
||||
#define CLK_MMC1 108
|
||||
#define CLK_MMC2 109
|
||||
#define CLK_MMC3 110
|
||||
#define CLK_TS 111
|
||||
#define CLK_CE 112
|
||||
#define CLK_SPI0 113
|
||||
#define CLK_SPI1 114
|
||||
#define CLK_SPI2 115
|
||||
#define CLK_SPI3 116
|
||||
#define CLK_I2S0 117
|
||||
#define CLK_I2S1 118
|
||||
#define CLK_I2S2 119
|
||||
#define CLK_AC97 120
|
||||
#define CLK_SPDIF 121
|
||||
#define CLK_KEYPAD 122
|
||||
#define CLK_SATA 123
|
||||
#define CLK_USB_PHY0 124
|
||||
#define CLK_USB_PHY1 125
|
||||
#define CLK_USB_PHY2 126
|
||||
#define CLK_USB_OHCI0 127
|
||||
#define CLK_USB_OHCI1 128
|
||||
#define CLK_USB_OHCI2 129
|
||||
#define CLK_IR0 130
|
||||
#define CLK_IR1 131
|
||||
|
||||
#define CLK_DRAM_VE 133
|
||||
#define CLK_DRAM_CSI0 134
|
||||
#define CLK_DRAM_CSI1 135
|
||||
#define CLK_DRAM_TS 136
|
||||
#define CLK_DRAM_TVD 137
|
||||
#define CLK_DRAM_MP 138
|
||||
#define CLK_DRAM_DEINTERLACE 139
|
||||
#define CLK_DE 140
|
||||
#define CLK_MP 141
|
||||
#define CLK_TCON_LCD0 142
|
||||
#define CLK_TCON_LCD1 143
|
||||
#define CLK_TCON_TV0 144
|
||||
#define CLK_TCON_TV1 145
|
||||
#define CLK_DEINTERLACE 146
|
||||
#define CLK_CSI1_MCLK 147
|
||||
#define CLK_CSI_SCLK 148
|
||||
#define CLK_CSI0_MCLK 149
|
||||
#define CLK_VE 150
|
||||
#define CLK_CODEC 151
|
||||
#define CLK_AVS 152
|
||||
#define CLK_HDMI 153
|
||||
#define CLK_HDMI_SLOW 154
|
||||
#define CLK_MBUS 155
|
||||
#define CLK_DSI_DPHY 156
|
||||
#define CLK_TVE0 157
|
||||
#define CLK_TVE1 158
|
||||
#define CLK_TVD0 159
|
||||
#define CLK_TVD1 160
|
||||
#define CLK_TVD2 161
|
||||
#define CLK_TVD3 162
|
||||
#define CLK_GPU 163
|
||||
#define CLK_OUTA 164
|
||||
#define CLK_OUTB 165
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */
|
||||
@@ -1,11 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
|
||||
|
||||
#define CLK_TCON_TOP_TV0 0
|
||||
#define CLK_TCON_TOP_TV1 1
|
||||
#define CLK_TCON_TOP_DSI 2
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
|
||||
@@ -1,111 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*
|
||||
* Based on sun8i-h3-ccu.h, which is:
|
||||
* Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
|
||||
|
||||
#define CLK_CPU 14
|
||||
|
||||
#define CLK_BUS_CE 20
|
||||
#define CLK_BUS_DMA 21
|
||||
#define CLK_BUS_MMC0 22
|
||||
#define CLK_BUS_MMC1 23
|
||||
#define CLK_BUS_MMC2 24
|
||||
#define CLK_BUS_DRAM 25
|
||||
#define CLK_BUS_EMAC 26
|
||||
#define CLK_BUS_HSTIMER 27
|
||||
#define CLK_BUS_SPI0 28
|
||||
#define CLK_BUS_OTG 29
|
||||
#define CLK_BUS_EHCI0 30
|
||||
#define CLK_BUS_OHCI0 31
|
||||
#define CLK_BUS_VE 32
|
||||
#define CLK_BUS_TCON0 33
|
||||
#define CLK_BUS_CSI 34
|
||||
#define CLK_BUS_DE 35
|
||||
#define CLK_BUS_CODEC 36
|
||||
#define CLK_BUS_PIO 37
|
||||
#define CLK_BUS_I2C0 38
|
||||
#define CLK_BUS_I2C1 39
|
||||
#define CLK_BUS_UART0 40
|
||||
#define CLK_BUS_UART1 41
|
||||
#define CLK_BUS_UART2 42
|
||||
#define CLK_BUS_EPHY 43
|
||||
#define CLK_BUS_DBG 44
|
||||
|
||||
#define CLK_MMC0 45
|
||||
#define CLK_MMC0_SAMPLE 46
|
||||
#define CLK_MMC0_OUTPUT 47
|
||||
#define CLK_MMC1 48
|
||||
#define CLK_MMC1_SAMPLE 49
|
||||
#define CLK_MMC1_OUTPUT 50
|
||||
#define CLK_MMC2 51
|
||||
#define CLK_MMC2_SAMPLE 52
|
||||
#define CLK_MMC2_OUTPUT 53
|
||||
#define CLK_CE 54
|
||||
#define CLK_SPI0 55
|
||||
#define CLK_USB_PHY0 56
|
||||
#define CLK_USB_OHCI0 57
|
||||
|
||||
#define CLK_DRAM_VE 59
|
||||
#define CLK_DRAM_CSI 60
|
||||
#define CLK_DRAM_EHCI 61
|
||||
#define CLK_DRAM_OHCI 62
|
||||
#define CLK_DE 63
|
||||
#define CLK_TCON0 64
|
||||
#define CLK_CSI_MISC 65
|
||||
#define CLK_CSI0_MCLK 66
|
||||
#define CLK_CSI1_SCLK 67
|
||||
#define CLK_CSI1_MCLK 68
|
||||
#define CLK_VE 69
|
||||
#define CLK_AC_DIG 70
|
||||
#define CLK_AVS 71
|
||||
|
||||
#define CLK_MIPI_CSI 73
|
||||
|
||||
/* Clocks not available on V3s */
|
||||
#define CLK_BUS_I2S0 75
|
||||
#define CLK_I2S0 76
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
|
||||
@@ -1,162 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_
|
||||
|
||||
#define CLK_PLL_AUDIO 2
|
||||
#define CLK_PLL_PERIPH0 3
|
||||
|
||||
#define CLK_C0CPUX 12
|
||||
#define CLK_C1CPUX 13
|
||||
|
||||
#define CLK_OUT_A 27
|
||||
#define CLK_OUT_B 28
|
||||
|
||||
#define CLK_NAND0_0 29
|
||||
#define CLK_NAND0_1 30
|
||||
#define CLK_NAND1_0 31
|
||||
#define CLK_NAND1_1 32
|
||||
#define CLK_MMC0 33
|
||||
#define CLK_MMC0_SAMPLE 34
|
||||
#define CLK_MMC0_OUTPUT 35
|
||||
#define CLK_MMC1 36
|
||||
#define CLK_MMC1_SAMPLE 37
|
||||
#define CLK_MMC1_OUTPUT 38
|
||||
#define CLK_MMC2 39
|
||||
#define CLK_MMC2_SAMPLE 40
|
||||
#define CLK_MMC2_OUTPUT 41
|
||||
#define CLK_MMC3 42
|
||||
#define CLK_MMC3_SAMPLE 43
|
||||
#define CLK_MMC3_OUTPUT 44
|
||||
#define CLK_TS 45
|
||||
#define CLK_SS 46
|
||||
#define CLK_SPI0 47
|
||||
#define CLK_SPI1 48
|
||||
#define CLK_SPI2 49
|
||||
#define CLK_SPI3 50
|
||||
#define CLK_I2S0 51
|
||||
#define CLK_I2S1 52
|
||||
#define CLK_SPDIF 53
|
||||
#define CLK_SDRAM 54
|
||||
#define CLK_DE 55
|
||||
#define CLK_EDP 56
|
||||
#define CLK_MP 57
|
||||
#define CLK_LCD0 58
|
||||
#define CLK_LCD1 59
|
||||
#define CLK_MIPI_DSI0 60
|
||||
#define CLK_MIPI_DSI1 61
|
||||
#define CLK_HDMI 62
|
||||
#define CLK_HDMI_SLOW 63
|
||||
#define CLK_MIPI_CSI 64
|
||||
#define CLK_CSI_ISP 65
|
||||
#define CLK_CSI_MISC 66
|
||||
#define CLK_CSI0_MCLK 67
|
||||
#define CLK_CSI1_MCLK 68
|
||||
#define CLK_FD 69
|
||||
#define CLK_VE 70
|
||||
#define CLK_AVS 71
|
||||
#define CLK_GPU_CORE 72
|
||||
#define CLK_GPU_MEMORY 73
|
||||
#define CLK_GPU_AXI 74
|
||||
#define CLK_SATA 75
|
||||
#define CLK_AC97 76
|
||||
#define CLK_MIPI_HSI 77
|
||||
#define CLK_GPADC 78
|
||||
#define CLK_CIR_TX 79
|
||||
|
||||
#define CLK_BUS_FD 80
|
||||
#define CLK_BUS_VE 81
|
||||
#define CLK_BUS_GPU_CTRL 82
|
||||
#define CLK_BUS_SS 83
|
||||
#define CLK_BUS_MMC 84
|
||||
#define CLK_BUS_NAND0 85
|
||||
#define CLK_BUS_NAND1 86
|
||||
#define CLK_BUS_SDRAM 87
|
||||
#define CLK_BUS_MIPI_HSI 88
|
||||
#define CLK_BUS_SATA 89
|
||||
#define CLK_BUS_TS 90
|
||||
#define CLK_BUS_SPI0 91
|
||||
#define CLK_BUS_SPI1 92
|
||||
#define CLK_BUS_SPI2 93
|
||||
#define CLK_BUS_SPI3 94
|
||||
|
||||
#define CLK_BUS_OTG 95
|
||||
#define CLK_BUS_USB 96
|
||||
#define CLK_BUS_GMAC 97
|
||||
#define CLK_BUS_MSGBOX 98
|
||||
#define CLK_BUS_SPINLOCK 99
|
||||
#define CLK_BUS_HSTIMER 100
|
||||
#define CLK_BUS_DMA 101
|
||||
|
||||
#define CLK_BUS_LCD0 102
|
||||
#define CLK_BUS_LCD1 103
|
||||
#define CLK_BUS_EDP 104
|
||||
#define CLK_BUS_CSI 105
|
||||
#define CLK_BUS_HDMI 106
|
||||
#define CLK_BUS_DE 107
|
||||
#define CLK_BUS_MP 108
|
||||
#define CLK_BUS_MIPI_DSI 109
|
||||
|
||||
#define CLK_BUS_SPDIF 110
|
||||
#define CLK_BUS_PIO 111
|
||||
#define CLK_BUS_AC97 112
|
||||
#define CLK_BUS_I2S0 113
|
||||
#define CLK_BUS_I2S1 114
|
||||
#define CLK_BUS_LRADC 115
|
||||
#define CLK_BUS_GPADC 116
|
||||
#define CLK_BUS_TWD 117
|
||||
#define CLK_BUS_CIR_TX 118
|
||||
|
||||
#define CLK_BUS_I2C0 119
|
||||
#define CLK_BUS_I2C1 120
|
||||
#define CLK_BUS_I2C2 121
|
||||
#define CLK_BUS_I2C3 122
|
||||
#define CLK_BUS_I2C4 123
|
||||
#define CLK_BUS_UART0 124
|
||||
#define CLK_BUS_UART1 125
|
||||
#define CLK_BUS_UART2 126
|
||||
#define CLK_BUS_UART3 127
|
||||
#define CLK_BUS_UART4 128
|
||||
#define CLK_BUS_UART5 129
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_
|
||||
|
||||
#define CLK_FE0 0
|
||||
#define CLK_FE1 1
|
||||
#define CLK_FE2 2
|
||||
#define CLK_IEP_DEU0 3
|
||||
#define CLK_IEP_DEU1 4
|
||||
#define CLK_BE0 5
|
||||
#define CLK_BE1 6
|
||||
#define CLK_BE2 7
|
||||
#define CLK_IEP_DRC0 8
|
||||
#define CLK_IEP_DRC1 9
|
||||
#define CLK_MERGE 10
|
||||
|
||||
#define CLK_DRAM_FE0 11
|
||||
#define CLK_DRAM_FE1 12
|
||||
#define CLK_DRAM_FE2 13
|
||||
#define CLK_DRAM_DEU0 14
|
||||
#define CLK_DRAM_DEU1 15
|
||||
#define CLK_DRAM_BE0 16
|
||||
#define CLK_DRAM_BE1 17
|
||||
#define CLK_DRAM_BE2 18
|
||||
#define CLK_DRAM_DRC0 19
|
||||
#define CLK_DRAM_DRC1 20
|
||||
|
||||
#define CLK_BUS_FE0 21
|
||||
#define CLK_BUS_FE1 22
|
||||
#define CLK_BUS_FE2 23
|
||||
#define CLK_BUS_DEU0 24
|
||||
#define CLK_BUS_DEU1 25
|
||||
#define CLK_BUS_BE0 26
|
||||
#define CLK_BUS_BE1 27
|
||||
#define CLK_BUS_BE2 28
|
||||
#define CLK_BUS_DRC0 29
|
||||
#define CLK_BUS_DRC1 30
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */
|
||||
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
|
||||
#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_
|
||||
|
||||
#define CLK_BUS_HCI0 0
|
||||
#define CLK_USB_OHCI0 1
|
||||
#define CLK_BUS_HCI1 2
|
||||
#define CLK_BUS_HCI2 3
|
||||
#define CLK_USB_OHCI2 4
|
||||
|
||||
#define CLK_USB0_PHY 5
|
||||
#define CLK_USB1_HSIC 6
|
||||
#define CLK_USB1_PHY 7
|
||||
#define CLK_USB2_HSIC 8
|
||||
#define CLK_USB2_PHY 9
|
||||
#define CLK_USB_HSIC 10
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */
|
||||
@@ -1,72 +0,0 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*
|
||||
* Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
|
||||
#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
|
||||
|
||||
#define CLK_CPU 11
|
||||
|
||||
#define CLK_BUS_DMA 14
|
||||
#define CLK_BUS_MMC0 15
|
||||
#define CLK_BUS_MMC1 16
|
||||
#define CLK_BUS_DRAM 17
|
||||
#define CLK_BUS_SPI0 18
|
||||
#define CLK_BUS_SPI1 19
|
||||
#define CLK_BUS_OTG 20
|
||||
#define CLK_BUS_VE 21
|
||||
#define CLK_BUS_LCD 22
|
||||
#define CLK_BUS_DEINTERLACE 23
|
||||
#define CLK_BUS_CSI 24
|
||||
#define CLK_BUS_TVD 25
|
||||
#define CLK_BUS_TVE 26
|
||||
#define CLK_BUS_DE_BE 27
|
||||
#define CLK_BUS_DE_FE 28
|
||||
#define CLK_BUS_CODEC 29
|
||||
#define CLK_BUS_SPDIF 30
|
||||
#define CLK_BUS_IR 31
|
||||
#define CLK_BUS_RSB 32
|
||||
#define CLK_BUS_I2S0 33
|
||||
#define CLK_BUS_I2C0 34
|
||||
#define CLK_BUS_I2C1 35
|
||||
#define CLK_BUS_I2C2 36
|
||||
#define CLK_BUS_PIO 37
|
||||
#define CLK_BUS_UART0 38
|
||||
#define CLK_BUS_UART1 39
|
||||
#define CLK_BUS_UART2 40
|
||||
|
||||
#define CLK_MMC0 41
|
||||
#define CLK_MMC0_SAMPLE 42
|
||||
#define CLK_MMC0_OUTPUT 43
|
||||
#define CLK_MMC1 44
|
||||
#define CLK_MMC1_SAMPLE 45
|
||||
#define CLK_MMC1_OUTPUT 46
|
||||
#define CLK_I2S 47
|
||||
#define CLK_SPDIF 48
|
||||
|
||||
#define CLK_USB_PHY0 49
|
||||
|
||||
#define CLK_DRAM_VE 50
|
||||
#define CLK_DRAM_CSI 51
|
||||
#define CLK_DRAM_DEINTERLACE 52
|
||||
#define CLK_DRAM_TVD 53
|
||||
#define CLK_DRAM_DE_FE 54
|
||||
#define CLK_DRAM_DE_BE 55
|
||||
|
||||
#define CLK_DE_BE 56
|
||||
#define CLK_DE_FE 57
|
||||
#define CLK_TCON 58
|
||||
#define CLK_DEINTERLACE 59
|
||||
#define CLK_TVE2_CLK 60
|
||||
#define CLK_TVE1_CLK 61
|
||||
#define CLK_TVD 62
|
||||
#define CLK_CSI 63
|
||||
#define CLK_VE 64
|
||||
#define CLK_CODEC 65
|
||||
#define CLK_AVS 66
|
||||
|
||||
#define CLK_IR 67
|
||||
|
||||
#endif
|
||||
@@ -1,13 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
/* This file defines field values used by the versaclock 6 family
|
||||
* for defining output type
|
||||
*/
|
||||
|
||||
#define VC5_LVPECL 0
|
||||
#define VC5_CMOS 1
|
||||
#define VC5_HCSL33 2
|
||||
#define VC5_LVDS 3
|
||||
#define VC5_CMOS2 4
|
||||
#define VC5_CMOSD 5
|
||||
#define VC5_HCSL25 6
|
||||
@@ -1,202 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_VF610_H
|
||||
#define __DT_BINDINGS_CLOCK_VF610_H
|
||||
|
||||
#define VF610_CLK_DUMMY 0
|
||||
#define VF610_CLK_SIRC_128K 1
|
||||
#define VF610_CLK_SIRC_32K 2
|
||||
#define VF610_CLK_FIRC 3
|
||||
#define VF610_CLK_SXOSC 4
|
||||
#define VF610_CLK_FXOSC 5
|
||||
#define VF610_CLK_FXOSC_HALF 6
|
||||
#define VF610_CLK_SLOW_CLK_SEL 7
|
||||
#define VF610_CLK_FASK_CLK_SEL 8
|
||||
#define VF610_CLK_AUDIO_EXT 9
|
||||
#define VF610_CLK_ENET_EXT 10
|
||||
#define VF610_CLK_PLL1_SYS 11
|
||||
#define VF610_CLK_PLL1_PFD1 12
|
||||
#define VF610_CLK_PLL1_PFD2 13
|
||||
#define VF610_CLK_PLL1_PFD3 14
|
||||
#define VF610_CLK_PLL1_PFD4 15
|
||||
#define VF610_CLK_PLL2_BUS 16
|
||||
#define VF610_CLK_PLL2_PFD1 17
|
||||
#define VF610_CLK_PLL2_PFD2 18
|
||||
#define VF610_CLK_PLL2_PFD3 19
|
||||
#define VF610_CLK_PLL2_PFD4 20
|
||||
#define VF610_CLK_PLL3_USB_OTG 21
|
||||
#define VF610_CLK_PLL3_PFD1 22
|
||||
#define VF610_CLK_PLL3_PFD2 23
|
||||
#define VF610_CLK_PLL3_PFD3 24
|
||||
#define VF610_CLK_PLL3_PFD4 25
|
||||
#define VF610_CLK_PLL4_AUDIO 26
|
||||
#define VF610_CLK_PLL5_ENET 27
|
||||
#define VF610_CLK_PLL6_VIDEO 28
|
||||
#define VF610_CLK_PLL3_MAIN_DIV 29
|
||||
#define VF610_CLK_PLL4_MAIN_DIV 30
|
||||
#define VF610_CLK_PLL6_MAIN_DIV 31
|
||||
#define VF610_CLK_PLL1_PFD_SEL 32
|
||||
#define VF610_CLK_PLL2_PFD_SEL 33
|
||||
#define VF610_CLK_SYS_SEL 34
|
||||
#define VF610_CLK_DDR_SEL 35
|
||||
#define VF610_CLK_SYS_BUS 36
|
||||
#define VF610_CLK_PLATFORM_BUS 37
|
||||
#define VF610_CLK_IPG_BUS 38
|
||||
#define VF610_CLK_UART0 39
|
||||
#define VF610_CLK_UART1 40
|
||||
#define VF610_CLK_UART2 41
|
||||
#define VF610_CLK_UART3 42
|
||||
#define VF610_CLK_UART4 43
|
||||
#define VF610_CLK_UART5 44
|
||||
#define VF610_CLK_PIT 45
|
||||
#define VF610_CLK_I2C0 46
|
||||
#define VF610_CLK_I2C1 47
|
||||
#define VF610_CLK_I2C2 48
|
||||
#define VF610_CLK_I2C3 49
|
||||
#define VF610_CLK_FTM0_EXT_SEL 50
|
||||
#define VF610_CLK_FTM0_FIX_SEL 51
|
||||
#define VF610_CLK_FTM0_EXT_FIX_EN 52
|
||||
#define VF610_CLK_FTM1_EXT_SEL 53
|
||||
#define VF610_CLK_FTM1_FIX_SEL 54
|
||||
#define VF610_CLK_FTM1_EXT_FIX_EN 55
|
||||
#define VF610_CLK_FTM2_EXT_SEL 56
|
||||
#define VF610_CLK_FTM2_FIX_SEL 57
|
||||
#define VF610_CLK_FTM2_EXT_FIX_EN 58
|
||||
#define VF610_CLK_FTM3_EXT_SEL 59
|
||||
#define VF610_CLK_FTM3_FIX_SEL 60
|
||||
#define VF610_CLK_FTM3_EXT_FIX_EN 61
|
||||
#define VF610_CLK_FTM0 62
|
||||
#define VF610_CLK_FTM1 63
|
||||
#define VF610_CLK_FTM2 64
|
||||
#define VF610_CLK_FTM3 65
|
||||
#define VF610_CLK_ENET_50M 66
|
||||
#define VF610_CLK_ENET_25M 67
|
||||
#define VF610_CLK_ENET_SEL 68
|
||||
#define VF610_CLK_ENET 69
|
||||
#define VF610_CLK_ENET_TS_SEL 70
|
||||
#define VF610_CLK_ENET_TS 71
|
||||
#define VF610_CLK_DSPI0 72
|
||||
#define VF610_CLK_DSPI1 73
|
||||
#define VF610_CLK_DSPI2 74
|
||||
#define VF610_CLK_DSPI3 75
|
||||
#define VF610_CLK_WDT 76
|
||||
#define VF610_CLK_ESDHC0_SEL 77
|
||||
#define VF610_CLK_ESDHC0_EN 78
|
||||
#define VF610_CLK_ESDHC0_DIV 79
|
||||
#define VF610_CLK_ESDHC0 80
|
||||
#define VF610_CLK_ESDHC1_SEL 81
|
||||
#define VF610_CLK_ESDHC1_EN 82
|
||||
#define VF610_CLK_ESDHC1_DIV 83
|
||||
#define VF610_CLK_ESDHC1 84
|
||||
#define VF610_CLK_DCU0_SEL 85
|
||||
#define VF610_CLK_DCU0_EN 86
|
||||
#define VF610_CLK_DCU0_DIV 87
|
||||
#define VF610_CLK_DCU0 88
|
||||
#define VF610_CLK_DCU1_SEL 89
|
||||
#define VF610_CLK_DCU1_EN 90
|
||||
#define VF610_CLK_DCU1_DIV 91
|
||||
#define VF610_CLK_DCU1 92
|
||||
#define VF610_CLK_ESAI_SEL 93
|
||||
#define VF610_CLK_ESAI_EN 94
|
||||
#define VF610_CLK_ESAI_DIV 95
|
||||
#define VF610_CLK_ESAI 96
|
||||
#define VF610_CLK_SAI0_SEL 97
|
||||
#define VF610_CLK_SAI0_EN 98
|
||||
#define VF610_CLK_SAI0_DIV 99
|
||||
#define VF610_CLK_SAI0 100
|
||||
#define VF610_CLK_SAI1_SEL 101
|
||||
#define VF610_CLK_SAI1_EN 102
|
||||
#define VF610_CLK_SAI1_DIV 103
|
||||
#define VF610_CLK_SAI1 104
|
||||
#define VF610_CLK_SAI2_SEL 105
|
||||
#define VF610_CLK_SAI2_EN 106
|
||||
#define VF610_CLK_SAI2_DIV 107
|
||||
#define VF610_CLK_SAI2 108
|
||||
#define VF610_CLK_SAI3_SEL 109
|
||||
#define VF610_CLK_SAI3_EN 110
|
||||
#define VF610_CLK_SAI3_DIV 111
|
||||
#define VF610_CLK_SAI3 112
|
||||
#define VF610_CLK_USBC0 113
|
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#define VF610_CLK_USBC1 114
|
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#define VF610_CLK_QSPI0_SEL 115
|
||||
#define VF610_CLK_QSPI0_EN 116
|
||||
#define VF610_CLK_QSPI0_X4_DIV 117
|
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#define VF610_CLK_QSPI0_X2_DIV 118
|
||||
#define VF610_CLK_QSPI0_X1_DIV 119
|
||||
#define VF610_CLK_QSPI1_SEL 120
|
||||
#define VF610_CLK_QSPI1_EN 121
|
||||
#define VF610_CLK_QSPI1_X4_DIV 122
|
||||
#define VF610_CLK_QSPI1_X2_DIV 123
|
||||
#define VF610_CLK_QSPI1_X1_DIV 124
|
||||
#define VF610_CLK_QSPI0 125
|
||||
#define VF610_CLK_QSPI1 126
|
||||
#define VF610_CLK_NFC_SEL 127
|
||||
#define VF610_CLK_NFC_EN 128
|
||||
#define VF610_CLK_NFC_PRE_DIV 129
|
||||
#define VF610_CLK_NFC_FRAC_DIV 130
|
||||
#define VF610_CLK_NFC_INV 131
|
||||
#define VF610_CLK_NFC 132
|
||||
#define VF610_CLK_VADC_SEL 133
|
||||
#define VF610_CLK_VADC_EN 134
|
||||
#define VF610_CLK_VADC_DIV 135
|
||||
#define VF610_CLK_VADC_DIV_HALF 136
|
||||
#define VF610_CLK_VADC 137
|
||||
#define VF610_CLK_ADC0 138
|
||||
#define VF610_CLK_ADC1 139
|
||||
#define VF610_CLK_DAC0 140
|
||||
#define VF610_CLK_DAC1 141
|
||||
#define VF610_CLK_FLEXCAN0 142
|
||||
#define VF610_CLK_FLEXCAN1 143
|
||||
#define VF610_CLK_ASRC 144
|
||||
#define VF610_CLK_GPU_SEL 145
|
||||
#define VF610_CLK_GPU_EN 146
|
||||
#define VF610_CLK_GPU2D 147
|
||||
#define VF610_CLK_ENET0 148
|
||||
#define VF610_CLK_ENET1 149
|
||||
#define VF610_CLK_DMAMUX0 150
|
||||
#define VF610_CLK_DMAMUX1 151
|
||||
#define VF610_CLK_DMAMUX2 152
|
||||
#define VF610_CLK_DMAMUX3 153
|
||||
#define VF610_CLK_FLEXCAN0_EN 154
|
||||
#define VF610_CLK_FLEXCAN1_EN 155
|
||||
#define VF610_CLK_PLL7_USB_HOST 156
|
||||
#define VF610_CLK_USBPHY0 157
|
||||
#define VF610_CLK_USBPHY1 158
|
||||
#define VF610_CLK_LVDS1_IN 159
|
||||
#define VF610_CLK_ANACLK1 160
|
||||
#define VF610_CLK_PLL1_BYPASS_SRC 161
|
||||
#define VF610_CLK_PLL2_BYPASS_SRC 162
|
||||
#define VF610_CLK_PLL3_BYPASS_SRC 163
|
||||
#define VF610_CLK_PLL4_BYPASS_SRC 164
|
||||
#define VF610_CLK_PLL5_BYPASS_SRC 165
|
||||
#define VF610_CLK_PLL6_BYPASS_SRC 166
|
||||
#define VF610_CLK_PLL7_BYPASS_SRC 167
|
||||
#define VF610_CLK_PLL1 168
|
||||
#define VF610_CLK_PLL2 169
|
||||
#define VF610_CLK_PLL3 170
|
||||
#define VF610_CLK_PLL4 171
|
||||
#define VF610_CLK_PLL5 172
|
||||
#define VF610_CLK_PLL6 173
|
||||
#define VF610_CLK_PLL7 174
|
||||
#define VF610_PLL1_BYPASS 175
|
||||
#define VF610_PLL2_BYPASS 176
|
||||
#define VF610_PLL3_BYPASS 177
|
||||
#define VF610_PLL4_BYPASS 178
|
||||
#define VF610_PLL5_BYPASS 179
|
||||
#define VF610_PLL6_BYPASS 180
|
||||
#define VF610_PLL7_BYPASS 181
|
||||
#define VF610_CLK_SNVS 182
|
||||
#define VF610_CLK_DAP 183
|
||||
#define VF610_CLK_OCOTP 184
|
||||
#define VF610_CLK_DDRMC 185
|
||||
#define VF610_CLK_WKPU 186
|
||||
#define VF610_CLK_TCON0 187
|
||||
#define VF610_CLK_TCON1 188
|
||||
#define VF610_CLK_CAAM 189
|
||||
#define VF610_CLK_CRC 190
|
||||
#define VF610_CLK_END 191
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
Reference in New Issue
Block a user