From fb33eaa3a26cdc37826390b6db223509230ae8e2 Mon Sep 17 00:00:00 2001 From: Brad Kim Date: Fri, 13 Nov 2020 20:47:51 +0900 Subject: [PATCH 1/6] riscv: fix the wrong swap value register Not s2 register, t1 register is correct Fortunately, it works because t1 register has a garbage value Signed-off-by: Brad Kim Reviewed-by: Lukas Auer Reviewed-by: Leo Liang --- arch/riscv/cpu/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bbc737ed9a2..8589509e012 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -123,7 +123,7 @@ call_board_init_f_0: * wait for initialization to complete. */ la t0, hart_lottery - li s2, 1 + li t1, 1 amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init #else From c353f2b845bbbb7b39ecb3f0aafac889cc25a328 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 2 Dec 2020 14:36:26 +0100 Subject: [PATCH 2/6] riscv: reset after crash If an exception occurs on ARM or x86, we call panic() which will try to reset the board. Do the same on RISC-V. To avoid -Werror=format-zero-length move a '\n' to the string passed to panic. We don't need a message here as depending on CONFIG_PANIC_HANG we will either see ### ERROR ### Please RESET the board ### or resetting ... as next message. Reviewed-by: Rick Chen Signed-off-by: Heinrich Schuchardt --- arch/riscv/lib/interrupts.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 35de98e8ce6..fb3ce118c17 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -27,7 +27,7 @@ static void show_efi_loaded_images(uintptr_t epc) static void show_regs(struct pt_regs *regs) { #ifdef CONFIG_SHOW_REGS - printf("SP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", + printf("\nSP: " REG_FMT " GP: " REG_FMT " TP: " REG_FMT "\n", regs->sp, regs->gp, regs->tp); printf("T0: " REG_FMT " T1: " REG_FMT " T2: " REG_FMT "\n", regs->t0, regs->t1, regs->t2); @@ -45,7 +45,7 @@ static void show_regs(struct pt_regs *regs) regs->s7, regs->s8, regs->s9); printf("S10: " REG_FMT " S11: " REG_FMT " T3: " REG_FMT "\n", regs->s10, regs->s11, regs->t3); - printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n\n", + printf("T4: " REG_FMT " T5: " REG_FMT " T6: " REG_FMT "\n", regs->t4, regs->t5, regs->t6); #endif } @@ -80,12 +80,12 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) epc, regs->ra, tval); /* Print relocation adjustments, but only if gd is initialized */ if (gd && gd->flags & GD_FLG_RELOC) - printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", + printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n", epc - gd->reloc_off, regs->ra - gd->reloc_off); show_regs(regs); show_efi_loaded_images(epc); - hang(); + panic("\n"); } int interrupt_init(void) From b620363feb50ad9ec0623581567beb317e0d52d7 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 1 Dec 2020 17:30:26 +0100 Subject: [PATCH 3/6] riscv: qemu: enable distro boot from scsi Booting via distro boot fails for: qemu-system-riscv64 -drive if=none,file=sct-riscv64.img,format=raw,id=mydisk \ -device ich9-ahci,id=ahci -device ide-hd,drive=mydisk,bus=ahci.0 Enable distro booting from an attached SCSI disk. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- include/configs/qemu-riscv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index aed9a4ae990..a2f33587c24 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -35,6 +35,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ + func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include From 84c3db2ea3b0e1eedb7557e4721b8880a14dcb69 Mon Sep 17 00:00:00 2001 From: Atish Patra Date: Tue, 13 Oct 2020 12:23:31 -0700 Subject: [PATCH 4/6] riscv: Fix efi header for RV32 RV32 should use PE32 format instead of PE32+ as the efi header format. This requires following changes 1. A different header magic value 2. An additional parameter known as BaseOfData. Currently, it is set to zero in absence of any usage. Signed-off-by: Atish Patra Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/crt0_riscv_efi.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 87fe1e56f90..4aaa49ad077 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -15,11 +15,13 @@ #define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV64 +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC #else #define SIZE_LONG 4 #define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV32 +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR32_MAGIC #endif @@ -48,7 +50,7 @@ coff_header: IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ IMAGE_FILE_DEBUG_STRIPPED) optional_header: - .short IMAGE_NT_OPTIONAL_HDR64_MAGIC /* PE32+ format */ + .short PE_MAGIC /* PE32+ format */ .byte 0x02 /* MajorLinkerVersion */ .byte 0x14 /* MinorLinkerVersion */ .long _edata - _start /* SizeOfCode */ @@ -56,6 +58,9 @@ optional_header: .long 0 /* SizeOfUninitializedData */ .long _start - ImageBase /* AddressOfEntryPoint */ .long _start - ImageBase /* BaseOfCode */ +#if __riscv_xlen == 32 + .long 0 /* BaseOfData */ +#endif extra_header_fields: .quad 0 /* ImageBase */ From 9ea6952a9ab75d09d8d8958ef7e425d3879b85e3 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Thu, 12 Nov 2020 10:09:52 +0800 Subject: [PATCH 5/6] riscv: Fix efi header size for RV32 This patch depends on Atish's patch. (https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/) Modify the size of the Optional Header "Windows-Specific Fields" to fit with the specification. (https://docs.microsoft.com/en-us/windows/win32/debug/pe-format) Signed-off-by: Leo Yu-Chi Liang Cc: rick@andestech.com Cc: alankao@andestech.com Cc: atish.patra@wdc.com Cc: xypron.glpk@gmx.de Cc: bmeng.cn@gmail.com --- arch/riscv/lib/crt0_riscv_efi.S | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 4aaa49ad077..48ff89553b9 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -15,13 +15,13 @@ #define SAVE_LONG(reg, idx) sd reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) ld reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV64 -#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR64_MAGIC #else #define SIZE_LONG 4 #define SAVE_LONG(reg, idx) sw reg, (idx*SIZE_LONG)(sp) #define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp) #define PE_MACHINE IMAGE_FILE_MACHINE_RISCV32 -#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR32_MAGIC +#define PE_MAGIC IMAGE_NT_OPTIONAL_HDR32_MAGIC #endif @@ -50,7 +50,7 @@ coff_header: IMAGE_FILE_LOCAL_SYMS_STRIPPED | \ IMAGE_FILE_DEBUG_STRIPPED) optional_header: - .short PE_MAGIC /* PE32+ format */ + .short PE_MAGIC /* PE32(+) format */ .byte 0x02 /* MajorLinkerVersion */ .byte 0x14 /* MinorLinkerVersion */ .long _edata - _start /* SizeOfCode */ @@ -63,7 +63,11 @@ optional_header: #endif extra_header_fields: +#if __riscv_xlen == 32 + .long 0 /* ImageBase */ +#else .quad 0 /* ImageBase */ +#endif .long 0x20 /* SectionAlignment */ .long 0x8 /* FileAlignment */ .short 0 /* MajorOperatingSystemVersion */ @@ -83,10 +87,17 @@ extra_header_fields: .long 0 /* CheckSum */ .short IMAGE_SUBSYSTEM_EFI_APPLICATION /* Subsystem */ .short 0 /* DllCharacteristics */ +#if __riscv_xlen == 32 + .long 0 /* SizeOfStackReserve */ + .long 0 /* SizeOfStackCommit */ + .long 0 /* SizeOfHeapReserve */ + .long 0 /* SizeOfHeapCommit */ +#else .quad 0 /* SizeOfStackReserve */ .quad 0 /* SizeOfStackCommit */ .quad 0 /* SizeOfHeapReserve */ .quad 0 /* SizeOfHeapCommit */ +#endif .long 0 /* LoaderFlags */ .long 0x6 /* NumberOfRvaAndSizes */ From 9afaeec6ef8bbc6cf936d2a9c3d28caffca5bf7e Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Mon, 16 Nov 2020 17:07:41 +0800 Subject: [PATCH 6/6] riscv: Complete efi header for RV32/64 This patch depends on Atish's patch. (https://patchwork.ozlabs.org/project/uboot/patch/20201013192331.3236458-1-atish.patra@wdc.com/) Add fields to complete Optional Header "Data Directories" specified in the document. (https://docs.microsoft.com/en-us/windows/win32/debug/pe-format) Signed-off-by: Leo Yu-Chi Liang Cc: rick@andestech.com Cc: alankao@andestech.com Cc: atish.patra@wdc.com Cc: xypron.glpk@gmx.de Cc: bmeng.cn@gmail.com Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/lib/crt0_riscv_efi.S | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S index 48ff89553b9..e7c4d99c21c 100644 --- a/arch/riscv/lib/crt0_riscv_efi.S +++ b/arch/riscv/lib/crt0_riscv_efi.S @@ -107,6 +107,16 @@ extra_header_fields: .quad 0 /* ExceptionTable */ .quad 0 /* CertificationTable */ .quad 0 /* BaseRelocationTable */ + .quad 0 /* Debug */ + .quad 0 /* Architecture */ + .quad 0 /* Global Ptr */ + .quad 0 /* TLS Table */ + .quad 0 /* Load Config Table */ + .quad 0 /* Bound Import */ + .quad 0 /* IAT */ + .quad 0 /* Delay Import Descriptor */ + .quad 0 /* CLR Runtime Header */ + .quad 0 /* Reserved */ /* Section table */ section_table: