global: Migrate CONFIG_PL011_CLOCK to CFG

Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-12-04 10:13:30 -05:00
parent 830fd095a3
commit f410d0ac8a
15 changed files with 19 additions and 19 deletions

View File

@@ -16,7 +16,7 @@
#define V2M_BASE 0x80000000
#define CONFIG_PL011_CLOCK 50000000
#define CFG_PL011_CLOCK 50000000
/* Physical Memory Map */
#define PHYS_SDRAM_1 (V2M_BASE)

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@@ -8,7 +8,7 @@
#define CFG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_PL011_CLOCK 150000000
#define CFG_PL011_CLOCK 150000000
/*
* Miscellaneous configurable options

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@@ -39,7 +39,7 @@
/* Serial Port */
#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CFG_SYS_SERIAL0 0x21c0000
#define CFG_SYS_SERIAL1 0x21d0000
#define CFG_SYS_SERIAL2 0x21e0000

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@@ -77,7 +77,7 @@
* DUART Serial Driver.
* Conflicts with AUART driver which can be set by board.
*/
#define CONFIG_PL011_CLOCK 24000000
#define CFG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
/* Default baudrate can be overridden by board! */

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@@ -76,7 +76,7 @@
/*-----------------------------------------------------------------------
* serial console configuration
*/
#define CONFIG_PL011_CLOCK 50000000
#define CFG_PL011_CLOCK 50000000
#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \
(void *)PHY_BASEADDR_UART1, \
(void *)PHY_BASEADDR_UART2, \

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@@ -31,7 +31,7 @@
/* Serial (pl011) */
#define UART_CLK (62500000)
#define CONFIG_PL011_CLOCK UART_CLK
#define CFG_PL011_CLOCK UART_CLK
#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
/* Support MTD */

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@@ -17,7 +17,7 @@
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
#define CFG_PL011_CLOCK 24000000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE (0x801000000000)

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@@ -14,7 +14,7 @@
#define UART0_BASE 0x7ff80000
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 7372800
#define CFG_PL011_CLOCK 7372800
/* Miscellaneous configurable options */

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@@ -86,9 +86,9 @@
/* PL011 Serial Configuration */
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
#define CONFIG_PL011_CLOCK 7372800
#define CFG_PL011_CLOCK 7372800
#else
#define CONFIG_PL011_CLOCK 24000000
#define CFG_PL011_CLOCK 24000000
#endif
/* Physical Memory Map */

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@@ -116,7 +116,7 @@
#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
/* PL011 Serial Configuration */
#define CONFIG_PL011_CLOCK 24000000
#define CFG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
(void *)CFG_SYS_SERIAL1}