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global: Migrate CONFIG_PL011_CLOCK to CFG
Perform a simple rename of CONFIG_PL011_CLOCK to CFG_PL011_CLOCK Signed-off-by: Tom Rini <trini@konsulko.com>
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@@ -16,7 +16,7 @@
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#define V2M_BASE 0x80000000
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#define CONFIG_PL011_CLOCK 50000000
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#define CFG_PL011_CLOCK 50000000
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 (V2M_BASE)
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@@ -8,7 +8,7 @@
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#define CFG_SYS_BOOTMAPSZ (16 << 20)
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#define CONFIG_PL011_CLOCK 150000000
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#define CFG_PL011_CLOCK 150000000
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/*
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* Miscellaneous configurable options
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@@ -39,7 +39,7 @@
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/* Serial Port */
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#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
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#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
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#define CFG_SYS_SERIAL0 0x21c0000
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#define CFG_SYS_SERIAL1 0x21d0000
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#define CFG_SYS_SERIAL2 0x21e0000
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@@ -77,7 +77,7 @@
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* DUART Serial Driver.
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* Conflicts with AUART driver which can be set by board.
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*/
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#define CONFIG_PL011_CLOCK 24000000
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#define CFG_PL011_CLOCK 24000000
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#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
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/* Default baudrate can be overridden by board! */
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@@ -76,7 +76,7 @@
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/*-----------------------------------------------------------------------
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* serial console configuration
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*/
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#define CONFIG_PL011_CLOCK 50000000
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#define CFG_PL011_CLOCK 50000000
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#define CONFIG_PL01x_PORTS {(void *)PHY_BASEADDR_UART0, \
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(void *)PHY_BASEADDR_UART1, \
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(void *)PHY_BASEADDR_UART2, \
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@@ -31,7 +31,7 @@
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/* Serial (pl011) */
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#define UART_CLK (62500000)
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#define CONFIG_PL011_CLOCK UART_CLK
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#define CFG_PL011_CLOCK UART_CLK
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#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
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/* Support MTD */
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@@ -17,7 +17,7 @@
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_CLOCK 24000000
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#define CFG_PL011_CLOCK 24000000
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE (0x801000000000)
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@@ -14,7 +14,7 @@
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#define UART0_BASE 0x7ff80000
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_CLOCK 7372800
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#define CFG_PL011_CLOCK 7372800
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/* Miscellaneous configurable options */
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@@ -86,9 +86,9 @@
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/* PL011 Serial Configuration */
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#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
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#define CONFIG_PL011_CLOCK 7372800
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#define CFG_PL011_CLOCK 7372800
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#else
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#define CONFIG_PL011_CLOCK 24000000
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#define CFG_PL011_CLOCK 24000000
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#endif
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/* Physical Memory Map */
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@@ -116,7 +116,7 @@
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#define CFG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
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/* PL011 Serial Configuration */
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#define CONFIG_PL011_CLOCK 24000000
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#define CFG_PL011_CLOCK 24000000
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#define CONFIG_PL01x_PORTS {(void *)CFG_SYS_SERIAL0, \
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(void *)CFG_SYS_SERIAL1}
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