Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm

CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236

- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support

drivers/clk/clk_scmi.c

@@ -336,8 +336,8 @@ static int scmi_clk_probe(struct udevice *dev)
 static int __scmi_clk_set_parent(struct clk *clk, struct clk *parent)
 {
 	struct scmi_clk_parent_set_in in = {
-		.clock_id = clk->id,
-		.parent_clk = parent->id,
+		.clock_id = clk_get_id(clk),
+		.parent_clk = clk_get_id(parent),
 	};
 	struct scmi_clk_parent_set_out out;
 	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,

drivers/clk/stm32/clk-stm32h7.c

@@ -549,8 +549,8 @@ static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
 	divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
 	divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
 
-	fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
-	fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
+	fracn1 = readl(&regs->pll1fracr) & RCC_PLL1FRACR_FRACN1_MASK;
+	fracn1 = (fracn1 >> RCC_PLL1FRACR_FRACN1_SHIFT) + 1;
 
 	vco = (pllsrc / divm1) * divn1;
 	rate = (pllsrc * fracn1) / (divm1 * 8192);

drivers/pwm/pwm-stm32.c

@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/arch/timers.h>
 #include <dm/device_compat.h>
+#include <linux/bitfield.h>
 #include <linux/time.h>
 
 #define CCMR_CHANNEL_SHIFT	8
@@ -157,7 +158,14 @@ static void stm32_pwm_detect_complementary(struct udevice *dev)
 {
 	struct stm32_timers_plat *plat = dev_get_plat(dev_get_parent(dev));
 	struct stm32_pwm_priv *priv = dev_get_priv(dev);
-	u32 ccer;
+	u32 ccer, val;
+
+	if (plat->ipidr) {
+		/* Simply read from HWCFGR the number of complementary outputs (MP25). */
+		val = readl(plat->base + TIM_HWCFGR1);
+		priv->have_complementary_output = !!FIELD_GET(TIM_HWCFGR1_NB_OF_DT, val);
+		return;
+	}
 
 	/*
 	 * If complementary bit doesn't exist writing 1 will have no
@@ -192,6 +200,7 @@ static const struct pwm_ops stm32_pwm_ops = {
 
 static const struct udevice_id stm32_pwm_ids[] = {
 	{ .compatible = "st,stm32-pwm" },
+	{ .compatible = "st,stm32mp25-pwm" },
 	{ }
 };
 

drivers/reset/stm32/Kconfig

@@ -16,7 +16,7 @@ config RESET_STM32MP1
 
 config RESET_STM32MP25
 	bool "Enable the STM32MP25 reset"
-	depends on STM32MP25X
+	depends on STM32MP23X || STM32MP25X
 	default y
 	help
 	  Support for reset controllers on STMicroelectronics STM32MP2 family SoCs.

drivers/reset/stm32/stm32-reset-core.c

@@ -6,7 +6,7 @@
 
 #include <dm.h>
 #include <reset-uclass.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
 #include <stm32_rcc.h>
 #include <dm/device_compat.h>
 #include <linux/iopoll.h>

drivers/reset/stm32/stm32-reset-mp1.c

@@ -5,7 +5,7 @@
  */
 
 #include <dm.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
 
 /* Reset clear offset for STM32MP RCC */
 #define RCC_CLR_OFFSET			0x4

drivers/reset/stm32/stm32-reset-mp25.c

@@ -5,7 +5,7 @@
  */
 
 #include <dm.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
 #include <stm32mp25_rcc.h>
 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
 

drivers/reset/stm32/stm32-reset.c

@@ -5,7 +5,7 @@
  */
 
 #include <dm.h>
-#include <stm32-reset-core.h>
+#include "stm32-reset-core.h"
 
 /* Timeout for deassert */
 #define STM32_DEASSERT_TIMEOUT_US	10000
@@ -19,7 +19,7 @@ static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *rese
 
 	ptr_line->offset = bank;
 	ptr_line->bit_idx = offset;
-	ptr_line->set_clr = true;
+	ptr_line->set_clr = false;
 
 	return ptr_line;
 }