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Merge branch 'for-1.3.2'

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This commit is contained in:
Stefan Roese
2008-02-14 11:46:07 +01:00
parent fe891ecf4d b7f6193e76
commit f90e69c634
9 changed files with 22 additions and 22 deletions
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6
cpu/ppc4xx/denali_spd_ddr2.c
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@@ -3,7 +3,7 @@
* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
* DDR2 controller, specifically the 440EPx/GRx.
*
* (C) Copyright 2007
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org.
*
* Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
@@ -77,10 +77,10 @@
* memory.
*
* If at some time this restriction doesn't apply anymore, just define
* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
* CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly.
*/
#if defined(CFG_ENABLE_SDRAM_CACHE)
#if defined(CONFIG_4xx_DCACHE)
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */

4
cpu/ppc4xx/ndfc.c
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@@ -121,8 +121,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
/* The NDFC uses Smart Media (SMC) bytes order
*/
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[0] = p[1];
ecc_code[1] = p[2];
ecc_code[2] = p[3];
return 0;

4
cpu/ppc4xx/start.S
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@@ -110,6 +110,10 @@
# endif
#endif /* CFG_INIT_DCACHE_CS */
#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
#endif
#define function_prolog(func_name) .text; \
.align 2; \
.globl func_name; \