Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

Convert CONFIG_SYS_FSL_QMAN_V3 et al to Kconfig

Browse Source 
This converts the following to Kconfig:
   CONFIG_FSL_NGPIXIS
   CONFIG_SYS_FSL_QMAN_V3
   CONFIG_SYS_FSL_RAID_ENGINE
   CONFIG_SYS_FSL_RMU
   CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
   CONFIG_SYS_FSL_SRIO_LIODN
   CONFIG_SYS_FSL_TBCLK_DIV
   CONFIG_SYS_FSL_USB1_PHY_ENABLE
   CONFIG_SYS_FSL_USB2_PHY_ENABLE
   CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
   CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-07-31 21:08:29 -04:00
parent 4143a23794
commit ff4e87c030
12 changed files with 82 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@@ -78,6 +78,7 @@ config TARGET_P3041DS
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select FSL_NGPIXIS
imply CMD_SATA
imply PANIC_HANG
@@ -86,6 +87,7 @@ config TARGET_P4080DS
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select FSL_NGPIXIS
imply CMD_SATA
imply PANIC_HANG
@@ -94,6 +96,8 @@ config TARGET_P5040DS
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select FSL_NGPIXIS
select SYS_FSL_RAID_ENGINE
imply CMD_SATA
imply PANIC_HANG
@@ -262,6 +266,8 @@ config ARCH_B4420
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
@@ -293,6 +299,9 @@ config ARCH_B4860
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_EEPROM
@@ -405,6 +414,7 @@ config ARCH_MPC8548
select SYS_FSL_HAS_DDR2
select SYS_FSL_HAS_DDR1
select SYS_FSL_HAS_SEC
select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
@@ -440,6 +450,7 @@ config ARCH_P1010
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_USB1_PHY_ENABLE
select SYS_PPC_E500_USE_DEBUG_TLB
select FSL_IFC
imply CMD_EEPROM
@@ -535,6 +546,7 @@ config ARCH_P1024
select FSL_PCIE_RESET
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_2
select SYS_PPC_E500_USE_DEBUG_TLB
@@ -610,6 +622,8 @@ config ARCH_P2041
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_USB1_PHY_ENABLE
select SYS_FSL_USB2_PHY_ENABLE
select FSL_ELBC
imply CMD_NAND
@@ -640,6 +654,8 @@ config ARCH_P3041
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_USB1_PHY_ENABLE
select SYS_FSL_USB2_PHY_ENABLE
select FSL_ELBC
imply CMD_NAND
imply CMD_SATA
@@ -681,6 +697,7 @@ config ARCH_P4080
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS1
select SYS_FSL_RMU
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select FSL_ELBC
@@ -711,6 +728,8 @@ config ARCH_P5040
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_USB1_PHY_ENABLE
select SYS_FSL_USB2_PHY_ENABLE
select SYS_PPC64
select FSL_ELBC
imply CMD_SATA
@@ -742,6 +761,9 @@ config ARCH_T1024
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_EEPROM
imply CMD_NAND
@@ -770,6 +792,9 @@ config ARCH_T1040
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
@@ -797,6 +822,9 @@ config ARCH_T1042
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SINGLE_SOURCE_CLK
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
@@ -826,6 +854,9 @@ config ARCH_T2080
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
@@ -859,6 +890,9 @@ config ARCH_T4240
select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
@@ -1147,6 +1181,12 @@ config FSL_PCIE_DISABLE_ASPM
config FSL_PCIE_RESET
bool
config SYS_FSL_RAID_ENGINE
bool
config SYS_FSL_RMU
bool
config SYS_FSL_QORIQ_CHASSIS1
bool
@@ -1312,6 +1352,9 @@ config FSL_CORENET
bool
select SYS_FSL_CPC
config FSL_NGPIXIS
bool
config SYS_CPC_REINIT_F
bool
help
@@ -1347,6 +1390,33 @@ config SYS_FSL_PCIE_COMPAT
Defines the string to utilize when trying to match PCIe device tree
nodes for the given platform.
config SYS_FSL_SINGLE_SOURCE_CLK
bool
config SYS_FSL_SRIO_LIODN
bool
config SYS_FSL_TBCLK_DIV
int
default 32 if ARCH_P2041 || ARCH_P3041
default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
ARCH_T1024 || ARCH_T2080
default 8
help
Defines the core time base clock divider ratio compared to the system
clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
be 16 or 32. The ratio varies from SoC to Soc.
config SYS_FSL_USB1_PHY_ENABLE
bool
config SYS_FSL_USB2_PHY_ENABLE
bool
config SYS_FSL_USB_DUAL_PHY_ENABLE
bool
config SYS_MPC85XX_NO_RESETVEC
bool "Discard resetvec section and move bootpg section up"
depends on MPC85xx

3
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@@ -334,9 +334,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
/*
* Get timebase clock frequency
*/
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
__weak unsigned long get_tbclk(void)
{
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;

4
arch/powerpc/cpu/mpc85xx/spl_minimal.c
View File

@@ -31,10 +31,6 @@ ulong cpu_init_f(void)
return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
void udelay(unsigned long usec)
{
u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);