Branch contains bringup of Acer Iconia Tab A500 (codename picasso), a
Tegra 2 Android device with decent Linux kernel support. Ondevice tests
and U-Boot test suit all passed.
The device tree for rk3036 combined is now
available in the /dts/upstream directory.
Use imply OF_UPSTREAM to migrate all rk3036 boards.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Most Rockchip SoCs use 0x0 as DRAM base address, however some SoCs use
0x60000000 and RK3576 use 0x40000000 as DRAM base address.
CFG_SYS_SDRAM_BASE is defined with correct address for each SoC and
U-Boot proper use this to set correct gd->ram_base in setup_dest_addr().
SPL never assign any value to gd->ram_base and instead use the default,
0x0. Set correct gd->ram_base in dram_init() to ensure its correctness
in SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
U-Boot only works correctly when it uses RAM below the 4G address
boundary on Rockchip SoCs. Limit usable gd->ram_top to max 4G.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Allow the first bank to extend beyond 4 GiB when the blob of space for
peripheral is located before start of DRAM, e.g. when start of DRAM
is 0x40000000 and continue beyond the 4 GiB mark.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
In the GRF header file, some instances of UART2 pinmux are prefixed with
"GRF_UART2DBG" while others have "GRF_UART2DGB".
Since UART2 is the default console UART and used for debugging, it is
more likely the name should be UART2DBG.
Fix the ones that are wrong.
Fixes: a2c08df381 ("pinctrl: add driver for rk3399")
Fixes: fa72de1045 ("rockchip: arm64: rk3399: move grf register definitions to grf_rk3399.h")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
These power rails must be on very early for the U-Boos TPL banner to be
show over debug UART.
This reverts commit 4576e65a5d.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
These power rails must be on very early for the U-Boos SPL banner to be
show over debug UART.
This reverts commit af518a1dfe.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Acer Iconia A500 is a tablet computer designed, developed and
marketed by Acer Inc. It is powered by 1 GHz Nvidia Tegra 2 processor
and 1GB DDR2 RAM. The A500 is sold with 64 GB, although both 16 GB
and 32 GB models are available.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Add empty weak assembler function armv8_switch_to_el2_prep() which is
jumped to just before U-Boot determines which EL it is running in and
decides which path to take to boot the Linux kernel.
This weak function is meant to be used by architecture specific code
to implement jump to a firmware blob, which then returns right past
this weak function and continues execution of U-Boot code which then
boots the Linux kernel. One example of such use case is when U-Boot
jump tp TFA BL31, which switches from EL3 to EL2 and then returns to
U-Boot code newly running in EL2 and starts the Linux kernel.
The weak function is called with caches already disabled and DM shut
down. Any preparatory work or even loading of more data must be done
in board_prep_linux(), this hook is meant only for the final jump to
the firmware and return to U-Boot before booting Linux.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
u-boot-dfu-20250211:
CI:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/24556
Android:
- Handle boot images with missing DTB
Usb gadget:
- Fix nullptr in g_dnl when serial# is unset
- Add missing schedule() in f_mass_storage gadget
- Add support for STih407 in dwc3-generic
- Fix usb clocks on STih407
- Migrate STih407 to DM_USB_GADGET
On STi platforms, all clocks are enabled by BOOTROM, so CONFIG_CLK is
not set as no clock driver for STI exists.
As ehci-generic and ohci-generic drivers are used on platforms where
CONFIG_CLK is set, clk_get_bulk() returns-ENOSYS in case of
stih410-b2260.
To avoid this error, add fixed clocks for ehci and ohci nodes for
stih410-b2260 to fix the following errors:
Bus usb@9a03c00: ohci_generic usb@9a03c00: Failed to get clocks (ret=-19)
Port not available.
Bus usb@9a03e00: ehci_generic usb@9a03e00: Failed to get clocks (ret=-19)
Port not available.
Bus usb@9a83c00: ohci_generic usb@9a83c00: Failed to get clocks (ret=-19)
Port not available.
Bus usb@9a83e00: ehci_generic usb@9a83e00: Failed to get clocks (ret=-19)
Port not available.
scanning bus dwc3@9900000 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20250130163547.512990-2-patrice.chotard@foss.st.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Judith Mendez <jm@ti.com> says:
This patch series enables ESM reset configuration in board_init_f
for am62x and am62px devices.
This is necessary in order for error events to reset the system.
This patches are tested using watchdog to reset the system via ESM.
Link: https://lore.kernel.org/r/20250129234403.574766-1-jm@ti.com
On AM62A and AM62P devices, it is possible to route Main ESM error
events to MCU ESM. MCU ESM high error output can trigger the reset
logic to reset the device. So, for these devices we have Main ESM and
MCU ESM nodes in the device tree. Add functions to probe these nodes
if CONFIG_ESM_K3 is enabled.
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
This patch enables switch auto-detction for mt7981 as some new mt7981
boards will use AN8855 ethernet switch.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add bootph-all properties to I2C0 nodes to ensure the bus and EEPROM
are accessible across all stages. This enables reading the SoM
configuration at any point during the boot process.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
The change from pinctrl to pio was missing in mt7986-u-boot.dtsi and will
cause build failure. Now fix it.
Fixes: f1775996ba (mediatek: mt7986: move gpio-controller up and rename pinctrl to pio)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Heiko Schocher <hs@denx.de> says:
In linux we have the option to create the name of a led
optionally through the following properties:
- function
- color
- function-enumerator
This series adds support for parsing this properties if there
is no label property.
Link: https://lore.kernel.org/r/20250128135246.74838-1-hs@denx.de
[trini: Document name parameter in led.h]
in linux we have the option to create the name of a led
optionally through the following properties:
- function
- color
- function-enumerator
This patch adds support for parsing this properties if there
is no label property.
The led name is created in led_post_bind() and we need some
storage place for it. Currently this patch prevents to use
malloc() instead it stores the name in new member :
char name[LED_MAX_NAME_SIZE];
of struct led_uc_plat. While at it append led tests for the
new feature.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Kconfig should not display the STATIC_MACH_TYPE option when
SUPPORT_PASSING_ATAGS is not selected. For example, when using most
platforms with menuconfig, it shows the STATIC_MACH_TYPE option causing
confusion. As we know, this should not occur when SUPPORT_PASSING_ATAGS
is not selected
[trini: Reword commit message]
Signed-off-by: Liya Huang <1425075683@qq.com>
ARMv7-M architecture uses NVIC instead of GIC.
NVIC is an interrupt controller specially designed for
ARM Cortex-M series processors.
Signed-off-by: Liya Huang <1425075683@qq.com>
CONFIG_XILINX_OF_BOARD_DTB_ADDR holds DTB address which U-Boot is checking.
Currently address in binman match default value but macro can be used
directly.
Also sync node name (s/hash-1/hash/) and sync location to have the same
order load/hash/image.
All binman DTSes are compiled that's why also guard
CONFIG_XILINX_OF_BOARD_DTB_ADDR which depends on OF_BOARD || OF_SEPARATE
which is a problem for mini configurations which are using OF_EMBED.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a22c9671b965b222bfd419f5bfaee012929f3d88.1738659214.git.michal.simek@amd.com
Add ethernet aliases to CC (Carrier card) description to create a
connection which is used by fdt_fixup_ethernet() for updating
local-mac-address in DT.
On Kria SOM MAC address is read from i2c eeprom at start and based on it
environment variables are created. Without creating aliases U-Boot is not
able to inject local-mac-address DT property and OS won't get the same MAC
address unless another i2c read is happening in OS.
Also aliases are using string not phandle that's why full path has to be
provided but that shouldn't be a big issue because location of ethernet
controller is fixed.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6d360e71a0530d201578e27a6997dbd472772e39.1737466907.git.michal.simek@amd.com
Output images are generated via Binman only if SPL is enabled, as
there is no consumer for them otherwise. An #ifdef check ensures that
when SPL is enabled, Binman generates the U-Boot ITB. If SPL is disabled,
ITB generation is skipped since the ITB format is supported only by SPL.
Without SPL, generating such an image is unnecessary, as it would not be
used
The second reason is that when a DTB is passed, the current logic cannot
handle it without an additional step in U-Boot to parse an appended FIT
image and enable board-specific code to select the correct DTB config.
The MULTI_DTB_FIT configuration should be used if support for multiple
DTBs is required, but SPL is not being used.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/7cba738ae36dacf7d1b0cfbaf13e0c9b3a0df225.1737462296.git.michal.simek@amd.com
Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Christian Marangi <ansuelsmth@gmail.com> says:
This is the last batch of part to push actual support of
OF_UPSTREAM for the mediatek SoC.
The plan is to make the current downstream DTS on part with
upstream implementation so we can permit a gradual transition to
it while we don't cause any regression to any user.
This is to have the same node downstream and upstream.
Mediatek is working hard upstream to also push all the remaining
nodes.
All patch are the final changes after the pinctrl patch
merged previously.
All patch pass CI tests
Link: https://github.com/u-boot/u-boot/pull/731
Link: https://lore.kernel.org/r/20250127134046.26345-1-ansuelsmth@gmail.com
Add USB PHY nodes for MT7981. These are needed for USB support and also
for PCIe support as the u3 PHY can also be used for PHY.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.
Update any DTS that reference the pinctrl to follow the new naming and
structure.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.
Update any DTS that reference the pinctrl to follow the new naming and
structure.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
Move gpio-controller up to pinctrl node and rename label to "pio" to
match the label used in upstream kernel linux.
Update any DTS that reference the pinctrl to follow the new naming and
structure.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
JH7110 SoC requires no specific handling before entering Linux kernel.
Let's drop the specific implementation to avoid duplication.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The current implementation is equivalent to the fallback one, so
this shouldn't change any behaviour but cleans the code up only.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's
provide a weak symbol as fallback to reduce duplicated code.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The following diagram illustrates the boot flow for OP-TEE OS
initialization on RISC-V.
(1)-----------+
| U-Boot SPL |
+------------+
|
v
(2)-------------------------------------------------------------+
| OpenSBI (fw_dynamic.bin) |
| (4)------------------------+ |
| | optee dispatcher driver | |
+-----------------+-------^---------|-------+------------------+
M-mode | | |
---------+--[trusted domain]---+----.----+--[untrusted domain]-------
S-mode | (coldboot domain) | | |
v | | v
(3)---------------------------+ |(5)----------------------------+
| OP-TEE OS (tee.bin) | | | U-Boot (u-boot-nodtb.bin) |
+----------------------------+ | +-----------------------------+
| |
| v
|(6)----------------------------+
| | Linux |
| +-----------------------------+
This patch enables the inclusion of the OP-TEE binary within the
U-Boot ITB, allowing it to be loaded to a platform defined address
by U-Boot SPL.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Allow specifying load address of OP-TEE binary. It is
recommended that the specified address aligns with the
base address of an PMP-protected NAPOT region and matches
the CFG_TDDRAM_START configuration in OP-TEE.
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
If CONFIG_AVAILABLE_HARTS=y, variable available_harts_lock is created in
the data section which will not be writable while executing from flash.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
