Commit Graph

27497 Commits

Author SHA1 Message Date
Tom Rini
8bc3542384 Merge patch series "pxe: Precursor series for supporting read_all() in extlinux / PXE"
Simon Glass <sjg@chromium.org> says:

This series includes some patches related to allowing read_all() to be
used with the extlinux / PXE bootmeths.

These patches were split out from the stb4 series, since it will need to
have additional patches for LWIP, to avoid breaking PXE booting when
LWIP is used.

Link: https://lore.kernel.org/r/20250306002533.2380866-1-sjg@chromium.org
2025-03-18 13:12:51 -06:00
Simon Glass
e2e87b8401 boot: pxe: Refactor label_run_boot() to avoid cmdline
Adjust the remaining call in this function to use the bootm API. This
will allow PXE to work without the command line.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
098407e673 boot: arm: riscv: sandbox: Add a format for the booti file
Arm invented a new format for arm64 and something similar is also used
with RISC-V. Add this to the list of supported formats and provide a way
for the format to be detected on both architectures.

Update the genimg_get_format() function to support this.

Fix up switch() statements which don't currently mention this format.
Booti does not support a ramdisk, so this can be ignored.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
c73da92304 x86: Drop the unnecessary base_ptr argument to zboot_dump()
This value is include the bootm_info, so drop the unnecessary parameter.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
1592ff27d5 bootstd: Correct display of kernel version
The address of the bzImage is not recorded in the bootflow, so we cannot
actually locate the version at present. Handle this case, to avoid
showing invalid data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
4e36b1739b x86: Move the bootm state for zimage into cmd/
Rather than holding the state in the implementation code, move it to the
command code. The state is now passed to the implementation functions
and can there (with future work) be pass in from bootstd, without going
through the commands.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
00cfb598e7 x86: Rename state to bmi
Use the common name for the struct, in preparation for passing it around
between functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
75e85df796 x86: Move x86 zboot state into struct bootm_info
This structure is supposed to handle any type of booting
programmatically, i.e. without needing a command to be executed. Move
the x86-specific members into it and use it instead of
struct zboot_state. Provide a macro so access is possible without adding
lots of #ifdefs to the code.

This will allow the struct to be used for all four types of booting
(bootm, bootz, booti and zboot).

Call bootm_init() to init the state, to match other boot methods.

Note that some rationalisation could be performed on this. But this
is tricky since addresses are stored as strings in several places. Also
some strings combine multiple arguments into one. So to keep this task
somewhat manageable, we content ourselves with just getting everything
into the same struct

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
2de073527b x86: Drop duplicate definition of zimage_dump()
This is now defined in bootm.h so drop the duplicate in the x86 code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Simon Glass
95641f4bf9 x86: Rename zboot_run() to zboot_run_args()
Rename this function so we can (later) create a zboot_run() function
which looks the same as bootm_run()

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Tom Rini
d92c29f89d Merge tag 'u-boot-amlogic-20250318' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next
- odroid-n2: Update docs for signing
- support Amlogic chip_id v1 and v2
2025-03-18 11:03:28 -06:00
Tom Rini
c342f27711 Merge patch series "*** Various Improvements for phyCORE-AM62/A SoMs ***"
Wadim Egorov <w.egorov@phytec.de> says:

This patch series syncs the phyCORE-AM62Ax feature-wise with our other
K3-based SoMs by adding SoM overlay handling and capsule updates. It
also introduces support for USBDFU boot and includes various minor fixes.

Link: https://lore.kernel.org/r/20250305045838.3614661-1-w.egorov@phytec.de
2025-03-18 09:04:06 -06:00
Evgeny Bachinin
dedea0d18d arch: arm: meson: support Amlogic chip_id v1 and v2
Patch introduces:
* chip_id API - useful for various things, but used now for
  device_id (did) generation as mentioned in [1] on our private board
  code. Our device_id is calculated by means of permutations of
  chip_id value.
* new SoCs (a1, s4, etc) are usually coming with the support of chip_id
  v2 right away, whereas secure monitors on old SoCs (like axg, g12b,
  g12a, etc) may support only chip_id v1. Chip_id API handles both
  cases
* meson_sm_get_serial() is described via chip_id API.

Links:
[1] https://lore.kernel.org/linux-arm-kernel/202311242104.RjBPI3uI-lkp@intel.com/T/#m630fbeea6a6e7d531290b5c0af205af4fb979757

Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
Co-developed-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-3-b98f8b6880b8@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18 15:27:25 +01:00
Evgeny Bachinin
e6d57a5a48 arm: meson: sm: get rid of SM_CHIP_ID_SIZE
SM_CHIP_ID_SIZE is used nowhere. Moreover, it specifies wrong
chip_id size: Amlogic chip_id v1 and v2 is always 16 bytes long.

Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-2-b98f8b6880b8@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18 15:27:25 +01:00
Evgeny Bachinin
4ea3c0ac21 arm: meson: unify type being used for socinfo
socinfo_ API uses u32 type, hence let's use it everywhere
for consistency.

Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-1-b98f8b6880b8@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-03-18 15:27:25 +01:00
Wadim Egorov
71582e7fa8 arm: dts: k3-am62a-phycore-som-binman: Add SoM overlays
Include SoM dt-overlays that handle variants of our SoMs into
u-boot's FIT image.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-03-18 08:12:53 -06:00
Wadim Egorov
61b907e937 arch: arm: dts: k3-am625-phyboard-lyra: Add missing boot phase tag
Add the bootph-all tag to usb0_phy_ctrl node to ensure it is
properly initialized during the boot process. This fixes the
following issue:

  dwc3-am62 dwc3-usb@f900000: unable to get ti,syscon-phy-pll-refclk regmap

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-03-18 08:12:53 -06:00
Wadim Egorov
fcf09a76e2 arch: arm: dts: k3-am62a7-phyboard-lyra: Add missing boot phase tag
Add the bootph-all tag to usb0_phy_ctrl node to ensure it is
properly initialized during the boot process. This fixes the
following issue:

  dwc3-am62 dwc3-usb@f900000: unable to get ti,syscon-phy-pll-refclk regmap

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-03-18 08:12:53 -06:00
Wadim Egorov
fc70ff633e arm: dts: k3-am62a-phycore-som-binman: Provide capsule nodes
Fill in phycore-am62ax capsule GUID properties of the base
binman capsule nodes.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-03-18 08:12:52 -06:00
Robert Nelson
b27c94958b board: beagle: Add support for BeagleY-AI
Basic board support for BeagleY-AI. Information on this
board can be found at https://beagleboard.org/beagley-ai

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
2025-03-18 07:23:29 -06:00
Tom Rini
6a5917fba1 Merge branch 'next' of git://source.denx.de/u-boot-usb into next
- Add USB support on Starfive JH7110
2025-03-17 10:18:59 -06:00
Tom Rini
4101b56d0b Merge branch 'nand-next' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/25178

This merge request add support for cadence raw nand driver for agilex
board and add a fix to meson driver.
2025-03-17 10:18:18 -06:00
Minda Chen
05aa34cef9 spl: starfive: visionfive2: Disable USB overcurrent pin by default.
For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled in spl stage.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: E Shattow <lucent@gmail.com>
2025-03-17 01:55:19 +01:00
Dinesh Maniyam
efb9cae1f1 arm: dts: agilex5: Enabled cdns-nand dts setting
Enable cdns-nand dts setting for the socfpga_agilex5
family device.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
2025-03-15 10:35:00 +01:00
Jim Liu
ef254ccf37 arm: dts: npcm7xx: correct the timer node
Correct the timer node of dts

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2025-03-14 12:26:55 -06:00
Tom Rini
973c366ce6 Merge tag 'mmu-next-14032025' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
Up to now we configure the entire memory space for U-Boot as RWX.
For modern architectures and security requirements, it's better to
map the memory properly.
This pull request adds basics support for mapping the U-Boot binary with
proper (RO, RW, RW^X) memory permissions on aarch64 right after we
relocate U-Boot in the top of DRAM.
It's worrth noting that the linker script annotations are only added for
the aarch64 architecture. We can, in the future, try to unify the linker --
at least for the architectures that have enough in common and expand this
2025-03-14 09:31:36 -06:00
Ilias Apalodimas
ec1c6cfb1c treewide: Add a function to change page permissions
For armv8 we are adding proper page permissions for the relocated U-Boot
binary. Add a weak function that can be used across architectures to change
the page permissions

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905X-CC
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-14 13:37:54 +02:00
Ilias Apalodimas
ff0a979fc3 arm64: mmu_change_region_attr() add an option not to break PTEs
The ARM ARM (Rev L.a) on section 8.17.1 describes the cases where
break-before-make is required when changing live page tables.
Since we can use a function to tweak block and page permissions,
where BBM is not required split the existing mmu_change_region_attr()
into two functions and create one that doesn't require BBM. Subsequent
patches will use the new function to map the U-Boot binary with proper
page permissions.
While at it add function descriptions in their header files.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-14 13:37:54 +02:00
Ilias Apalodimas
1c7d0c411c arm: Prepare linker scripts for memory permissions
Upcoming patches are switching the memory mappings to RW, RO, RX
after the U-Boot binary and its data are relocated. Add
annotations in the linker scripts to and mark text, data, rodata
sections and align them to a page boundary.

It's worth noting that .efi_runtime memory permissions are left
untouched for now. There's two problems with EFI currently.

The first problem is that we bundle data, rodata and text in a single
.efi_runtime section which also must be close to .text for now.
As a result we also dont change the permissions for anything contained
in CPUDIR/start.o. In order to fix that we have to decoule .text_rest,
.text and .efi_runtime and have the runtime services on their own
section with proper memory permission annotations (efi_rodata etc).

The efi runtime regions (.efi_runtime_rel) can be relocated by the OS when
the latter is calling SetVirtualAddressMap. Which means we have to
configure those pages as RX for U-Boot but convert them to RWX just before
ExitBootServices. It also needs extra code in efi_tuntime relocation
code since R_AARCH64_NONE are emitted as well if we page align the
section.

Due to the above ignore EFI for now and fix it later once we have the
rest in place.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905X-CC
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-14 13:30:12 +02:00
Ilias Apalodimas
e34ecf9d5e meminfo: add memory details for armv8
Upcoming patches are mapping memory with RO, RW^X etc permsissions.
Fix the meminfo command to display them properly

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-14 13:30:12 +02:00
Tom Rini
bbfabe2901 Merge tag 'u-boot-imx-next-20250313' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/25142

- Support Toradex i.MX6 Apalis/Colibri v1.2 SoM.
- Guard tee.bin inclusion on imx9,
- Remove unneeded regulator entry on DH i.MX6 DHCOM DRC02 devicetree.
- Add i.MX mailbox driver
- Convert ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE to Kconfig.
- Cope with existing optee node on imx8m.
2025-03-13 16:45:19 -06:00
Marek Vasut
15d6518c94 ARM: dts: imx: Drop bogus regulator extras on DH i.MX6 DHCOM DRC02
The regulator extras should be placed in the USB H1 regulator node,
the /regulator-usb-h1-vbus. They are already present there in the
upstream DT, so delete this bogus node entirely.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-13 15:22:48 -06:00
Bryan Brattlof
096aa229a9 mach-k3: common_fdt: create a reserved memory node
Some device trees may not have a reserved-memory node. Rather than
exiting early we should create a new reserved-memory node along with
the memory carveout for the firmware we (U-Boot) have placed.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
2025-03-13 14:22:57 -06:00
Marek Vasut
a1cd1ac79a ARM: dts: imx: Drop bogus regulator extras on DH i.MX6 DHCOM DRC02
The regulator extras should be placed in the USB H1 regulator node,
the /regulator-usb-h1-vbus. They are already present there in the
upstream DT, so delete this bogus node entirely.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-13 15:15:50 -03:00
Vincent Stehlé
048fabc21b imx8m: soc: cope with existing optee node
On i.MX8M SoCs, the /firmware/optee Devicetree node is created just before
booting the OS when OP-TEE is found running. If the node already exists,
this results in an error, which prevents the OS to boot:

  Could not create optee node.
  ERROR: system-specific fdt fixup failed: FDT_ERR_EXISTS
   - must RESET the board to recover.

  failed to process device tree

On the i.MX8M systems where CONFIG_OF_SYSTEM_SETUP is defined, the
ft_add_optee_node() function is called before booting the OS. It will
create the OP-TEE Devicetree node and populate it with reserved memory
informations gathered at runtime.

On on most i.MX8M systems the Devicetree is built with an optee node if
CONFIG_OPTEE is defined. This node is indeed necessary for commands and
drivers communicating with OP-TEE, even before attempting OS boot.

The aforementioned issue can happen on the Compulab IOT-GATE-iMX8, which is
the only in-tree i.MX8M system where both CONFIG_OPTEE and
CONFIG_OF_SYSTEM_SETUP are defined (see the imx8mm-cl-iot-gate*
defconfigs).

Deal with an existing optee node gracefully at runtime to fix this issue.

Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tim Harvey <tharvey@gateworks.com>
2025-03-13 15:15:50 -03:00
Fabio Estevam
9028da7675 imx9: container.cfg: Guard tee.bin inclusion
Guard the inclusion of tee.bin with the CONFIG_OPTEE symbol to fix the
following build warning:

  CHECK    u-boot-container.cfgout
WARNING './tee.bin' not found, resulting binary may be not-functional
  BINMAN  .binman_stamp
  OFCHK   .config

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-03-13 15:15:50 -03:00
Tom Rini
569dceef2e mmc: fsl_esdhc: Migrate ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE to Kconfig
The flag for enabling the ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE quirk can be
handled easily enough in Kconfig. This lets us remove a function but not
obviously correct usage of the IS_ENABLED() macro.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-03-13 15:15:50 -03:00
Tom Rini
3e73373c37 Merge patch series "xPL-stack cleanup"
Simon Glass <sjg@chromium.org> says:

This series was split from the VBE part H series. It adjusts the logic
for selecting the top of the stack so that it is more consistent across
xPL phases.

Link: https://lore.kernel.org/r/20250228122042.1277079-1-sjg@chromium.org
2025-03-13 10:36:11 -06:00
Simon Glass
ffa98c08e8 spl: Use CONFIG_VAL() to obtain the SPL stack
Now that we have the same option for SPL and TPL, simplify the logic for
determining the initial stack.

Note that this changes behaviour as current SPL_STACK is a fallback for
TPL. However, that was likely unintended and can be handled with Kconfig
defaults if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suggested-by: Tom Rini <trini@konsulko.com>
2025-03-13 10:36:10 -06:00
Simon Glass
d6a53f523a spl: Add an SPL_HAVE_INIT_STACK option
At present there is a hex value SPL_STACK which both determines whether
SPL has its own initial stack and the hex value of that stack.

Split off the former into SPL_HAVE_INIT_STACK with SPL_STACK depending
on that and only providing the latter.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Resync defconfig files]
2025-03-13 10:36:09 -06:00
Simon Glass
e7741f1124 tpl: Rename TPL_NEEDS_SEPARATE_STACK to TPL_HAVE_INIT_STACK
The most common word for features that make a platform work is to use
'HAVE_xxx'. Rename this option to match.

Update the help to use the word 'phase' rather than 'stage', since
that is the current terminology. Also clarify that, absent this setting,
the stack pointer generally comes from the value used by U-Boot proper,
rather than SPL.

Move the option just above TPL_STACK which depends on it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-13 10:35:22 -06:00
Tom Rini
54e5e8b340 Merge patch series "arm: mach-sc5xx: Remove manual bss_clear"
This series from Greg Malysa <malysagreg@gmail.com> provides two more
fixes for the mach-sc5xx platforms.

Link: https://lore.kernel.org/r/20250228185837.25741-1-malysagreg@gmail.com
2025-03-13 09:52:36 -06:00
Greg Malysa
74f4170a87 arm: mach-sc5xx: Remove inappropriate board-specific functions
The sc5xx machine code includes implementations of board_init and
board_early_init_f which should not be included in the base soc support
code, as they should be implemented by a board where necessary.

This removes the default empty implementations of both from mach-sc5xx.

Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-03-13 09:52:33 -06:00
Greg Malysa
3ce975ab88 arm: mach-sc5xx: Remove manual bss_clear
The arm library includes an implementation of bss_clear that is already
called from crt0.S. This re-clearing of BSS should not be performed in
the machine code and should therefore be removed.

Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-03-13 09:52:33 -06:00
Tom Rini
2b487bf99f Merge patch series "Update DDR Configurations"
Santhosh Kumar K <s-k6@ti.com> says:

This series is to update the DDR configurations of AM64x EVM, AM62x SK,
AM62x LP SK, AM62Ax SK and AM62Px SK boards according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Test logs: https://gist.github.com/santhosh21/43723900f3615e4cf98da57ed9618cf9

Link: https://lore.kernel.org/r/20250226063923.2266288-1-s-k6@ti.com
2025-03-13 09:51:46 -06:00
Santhosh Kumar K
226f16e406 arm: dts: k3-am62p: Update DDR Configurations
Update the DDR Configurations for AM62Px SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
2025-03-13 09:50:14 -06:00
Santhosh Kumar K
1df8c8bce6 arm: dts: k3-am62a: Update DDR Configurations
Update the DDR Configurations for AM62Ax SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
2025-03-13 09:50:14 -06:00
Santhosh Kumar K
1132a455f4 arm: dts: k3-am62-lp: Update DDR Configurations
Update the DDR Configurations for AM62x LP SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
2025-03-13 09:50:14 -06:00
Santhosh Kumar K
af3d03c28b arm: dts: k3-am62x: Update DDR Configurations
Update the DDR Configurations for AM62x SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
2025-03-13 09:50:14 -06:00
Santhosh Kumar K
a11f351ed4 arm: dts: k3-am64: Update DDR Configurations
Update the DDR Configurations for AM64x EVM according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
2025-03-13 09:50:14 -06:00