When MMC_SDHCI_SDMA=y or MMC_SDHCI_ADMA=y and PIO mode is used
dma_unmap_single() is called on an unmapped address, 0x0. This may
result in a Synchronous Abort:
## Checking hash(es) for Image atf-1 ... sha256+ OK
CMD_SEND:16
ARG 0x00000200
MMC_RSP_R1,5,6,7 0x00000900
CMD_SEND:18
ARG 0x00004005
"Synchronous Abort" handler, esr 0x96000147
elr: 00000000400015bc lr : 0000000040012b4c
x 0: 0000000000008000 x 1: 0000000000092600
x 2: 0000000000000040 x 3: 000000000000003f
x 4: 0000000000000030 x 5: 0000000000000001
x 6: 0000000000000001 x 7: 0000000000000000
x 8: 000000000000000a x 9: 0000000000000090
x10: 0000000043dffc68 x11: 0000000043c00440
x12: 0000000043c00440 x13: ffffffffbfe00000
x14: 000000000000031c x15: 0000000240000000
x16: 000000004001145c x17: 0000000000000032
x18: 0000000043dffef0 x19: 0000000043c00000
x20: 0000000043dffbc8 x21: 0000000000000000
x22: 00000000000f3d95 x23: 0000000000000002
x24: 0000000000000493 x25: 0000000000092600
x26: 0000000000000001 x27: 0000000000000001
x28: 0000000000000008 x29: 0000000043dffab0
Code: d2800082 9ac32042 d1000443 8a230000 (d5087620)
Resetting CPU ...
resetting ...
Fix this by only dma_unmap_single() when DMA mode is used and
sdhci_prepare_dma() has been called to map host->start_addr.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Per JESD84-B51 6.6.9 Erase:
The host can erase a contiguous range of Erase Groups. Starting the erase
process is a three steps sequence. First the host defines the start address
of the range using the ERASE_GROUP_START (CMD35) command, next it defines
the last address of the range using the ERASE_GROUP_END (CMD36) command and
finally it starts the erase process by issuing the ERASE (CMD38) command
with argument bits set to zero. See Table 11 for the arguments supported by
CMD38. The address field in the erase commands is an Erase Group address,
in byte units for densities up to 2GB, and in sector units for densities
greater than 2GB. The Device will ignore all LSB's below the Erase Group
size, effectively rounding the address down to the Erase Group boundary.
So choose 2GB bytes as check condition.
If the erase size is larger that 2GB, use 2GB to avoid breaking non high
capacity cards. If erase size is less than 2GB and larger than a grp, use
'grpcnt * mmc->erase_grp_size' to cover all the sectors, else use
the number of sectors.
With test erasing 20GB eMMC
board: Evk_8ulp Evk_8mm Evk_8mn Evk_8mp Mek_8qxpc0 Mek_8qm
kingston sandisk
before: 37.683s 112.738s 129.365s 28.238s 112.605s 500.470s 490.708s
after: 0.093s 0.111s 0.951s 0.080s 0.121s 6.960s 6.915s
Tested-by: Faqiang Zhu <faqiang.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
In case mmc_complete_init() returns error, exit from mmc_init()
without possibly calling cyclic_register(), which at that point
would be undesired.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Simplify 90cc07fd78 ("mmc: Poll CD in case cyclic framework is enabled")
according to suggestions by Rasmus. The struct cyclic_info is zero-size in
case CONFIG_CYCLIC is not enabled and does not add any size to struct mmc,
so it can unconditionally be part of that structure. This allows clean up
of all the other conditionals in mmc.c which can now be unconditionally
present, as they also add no extra space.
Suggested-by: Rasmus Villemoes <ravi@prevas.dk>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The option MMC_SDHCI_ADMA_FORCE_32BIT is only tested or used when
MMC_SDHCI_ADMA or SPL_MMC_SDHCI_ADMA is enabled. And for
MMC_SDHCI_ADMA_64BIT the same is true except we also require
MMC_SDHCI_ADMA_FORCE_32BIT to be disabled.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
UFS devices uses the block and scsi frameworks. Enable UFS erase
support by adding erase support to SCSI.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Allow invoking fit_check_sig without the key parameter, allowing to
validate only checksums and hashes for unsigned images.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Skip signature verification in case no public key was given in order to
allow using fit_check_sign also to validate uImage.FIT images without
signatures. Guarded by USE_HOSTCC macro the behavior on target is
unchanged.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
As current design, only Manager CPU called armv8_setup_psci() before
jump to next stage(such as Linux Kernel), Subordinate CPUs also need
setup psci vector to handle trap request which comes from higher EL
level.
Signed-off-by: Xu Zhang <423756212@qq.com>
[trini: Guard with !CONFIG_XPL_BUILD check]
Add support for the LCD interfaces (LCDIF1/2). When probed, these
interfaces request numerous clocks and power domains, attach the bridge
and look for a panel in order to retrieve its capabilities and
properties.
There is a similar existing driver in the upper folder for other i.MX
targets, I discovered this driver a bit late. It is not targeting the
i.MX8MP and I have no idea how different can the LCDIF be on this SoC,
but I did not manage to get it work, especially because it is not fully
compliant with the device-model, especially on the clocks/power
management side which is all ad-hoc. This is normal though, it was
contributed more than ten years ago.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Add support for the LVDS Display Bridge (LDB) found on i.MX8MP.
When attached, the bridge driver looks for panels connected to one of
its two outputs and adapts its own configuration to use them. There is
currently no support for merged/split displays.
Note regarding the clock configuration:
The LDB output clock should be absolutely identical to the LCDIF output
clock so both blocks can talk to each other synchronously. However, the
LDB clock has an internal divisor of 7 (respectively 3.5 in dual
configuration) which means the LDB input clock must be explicitly set
once we know the configuration.
This driver was tested on i.MX8MP using a single panel connected to the
LVDS2 interface.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
The IPUv3 is one IP part of the imx world, there are others, and
selecting the whole imx/ folder based on such a specific Kconfig symbol
is sub-optimal. Let's always enter the imx/ folder, and then selectively
compile parts of the folder based on the configuration.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Add support for the i.MX8 MEDIAMIX domain which is driving the power
over the whole display/rendering pipeline.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
These are all the clocks needed to get an LCD panel working, going
through one of the LCDIF and the LDB. The media AXI and APB clocks are
also described.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reparenting a clock C with a new parent P means that C will only
continue clocking if P is already clocking when the mux is updated. In
case the parent is currently disabled, failures (stalls) are likely to
happen.
This is exactly what happens on i.MX8 when enabling the video
pipeline. We tell LCDIF clocks to use the VIDEO PLL as input, while the
VIDEO PLL is currently off. This all happens as part of the
assigned-clocks handling procedure, where the reparenting happens before
the enable() calls. Enabling the parents as part of the reparenting
procedure seems sane and also matches the logic applied in other parts
of the CCM.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
It is very surprising that such an uclass, specifically designed to
handle resources that may be shared by different devices, is not keeping
the count of the number of times a power domain has been
enabled/disabled to avoid shutting it down unexpectedly or disabling it
several times.
Doing this causes troubles on eg. i.MX8MP because disabling power
domains can be done in recursive loops were the same power domain
disabled up to 4 times in a row. PGCs seem to have tight FSM internal
timings to respect and it is easy to produce a race condition that puts
the power domains in an unstable state, leading to ADB400 errors and
later crashes in Linux.
CI tests using power domains are slightly updated to make sure the count
of on/off calls is even and the results match what we *now* expect.
As we do not want to break existing users while stile getting
interesting error codes, the implementation is split between:
- a low-level helper reporting error codes if the requested transition
could not be operated,
- a higher-level helper ignoring the "non error" codes, like EALREADY and
EBUSY.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This is a new DM core helper. There is now a graph endpoint
representation in the sandbox test DTS, so we can just use it to verify
the helper proper behavior.
Suggested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
There are already several helpers to find a udevice based on its
position in a device tree, like getting a child or a node pointed by a
phandle, but there was no support for graph endpoints, which are very
common in display pipelines.
Add a new helper, named uclass_get_device_by_endpoint() which enters the
child graph reprensentation, looks for a specific port, then follows the
remote endpoint, and finally retrieves the first parent of the given
uclass_id.
This is a very handy and straightforward way to get a bridge or a panel
handle.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
`.priv_data_size` does not exist. I believe the actual structure member
was supposed to be `.priv_auto`.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Naming between the parameter list, the prototype and the main comment do
not match. Fix the comment which seems the be the one that is incorrect.
Fixes: 9057077cf4 ("core: ofnode: add of_graph parsing helpers")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
In console_setfile(), there is some #ifdef'ed code, updating monitor
functions for a U-Boot proper build. This is called inside a switch/case
statement, but the closing "break;" is inside the #ifdef section.
This doesn't look right: we should not fall through to the error case
for an SPL/TPL build.
Move the "break" to be always effective, solving a compiler warning about
an untagged implicit fallthrough.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This data was generated using the ksswtool-autogen project with the
followig commit:
eed7492 ("soc: am62ax: Add cpsw_3guss_main_0 id to the dev list")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Don't initialize Ethernet2 in SPL. We cannot boot from that source anyways
and it throws an error during boot.
This will remove following error message during network boot:
Error: ethernet@8000000port@2 No valid MAC address found.ethernet@8000000port@1
Waiting for PHY auto negotiation to complete....... done
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Add support for ethernet boot in the A53 SPL. Increase the SPL Size
limit and update SPL_STACK_R_ADDR.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Provide a defconfig for booting the phycore-am62x via Ethernet.
We need a separate defconfig because the AM62x has not enough internal
SRAM to support all boot sources.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Add bootph-all tag to phy_gmii_sel node. This is needed for booting via
Ethernet. While at it, drop main_pktdma reg redefinitions which are already
provided by the top-level SoC device tree file.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
Caleb Connolly <caleb.connolly@linaro.org> says:
SCSI devices like UFS may maintain their own cache to speed up writes,
however this is lost on board reset (and may be lost on device removal
or reset by OS drivers).
Currently this can be worked around by "waiting for a while" after
writing data to disk, but of course this is not an acceptable solution.
Ideally U-Boot would have a mechanism to flush caches during board
reset, but until that logic is hooked up let's be sure that all writes
are actually propagated to the storage device so that we don't lose data
on board reset.
The same logic was already implemented just for the AHCI backend, this
duplicated logic has been removed and support for the SYNC_CACHE command
is added to AHCI.
This is particularly noticeable during capsule updates, since the update
file is deleted and the board is reset immediately afterwards which
resulted in the same capsule update being applied over and over again.
This specifically fixes Qualcomm SDM845 devices with UFS 2.1, but likely
all UFS devices that use a cache.
Link: https://lore.kernel.org/r/20250326-scsi-sync-on-write-v2-0-12ab05bd464b@linaro.org
The SCSI layer now issues a SYNC_CACHE command after every write to
ensure there is no data loss due to a board reset after write.
Implement support for this command and remove the same logic from the
ATA write path to be consistent with other SCSI backends.
Ranges are not supported and the whole cache will be flushed in all
cases.
This was done per iteration in ata_scsiop_read_write(), but it's not
clear why this was the case, calling it once for the entire write ought
to achieve the same result.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
We don't have a mechanism to safely shutdown block devices prior to a
baord reset or driver removal. Prevent data loss by synchronizing the
SCSI cache after every write.
In particular this solves the issue of capsule updates looping on some
devices because the board resets immediately after deleting the capsule
file and this write wouldn't be flushed in time.
This may impact NAND wear, but should be negligible given the usecases
for disk write in U-Boot.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
This clears the 6th byte of cmd twice rather than setting the 9th byte
to 0. Fix it.
The only other command that sets the 9th byte is the 64-bit read, so
this likely never caused issues in practise.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Since introduction of OF_UPSTREAM flag, U-Boot's dtc must be able
to compile Kernel's device tree.
Since kernel commit 7de129f5389b ("ARM: dts: stm32: stm32mp151a-prtt1l:
Fix QSPI configuration"), label relative path references has been
introduced. These label relative path references is not supported
by current U-Boot dtc version 1.5.0: (see mailing list discussion [1]).
In order to support such label relative patch references
adds following commit from upstream DTC tree:
commit 651410e54cb9 ("util: introduce xstrndup helper")
commit ec7986e682cf ("dtc: introduce label relative path references")
[1] https://lore.kernel.org/all/20250115144428.GZ3476@bill-the-cat/T/
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The symbol "ENV_IS_EMBEDDED" is an environment internal define and not a
real CONFIG symbol. The IS_ENABLED() macro is still valid to use here,
so update the check.
Signed-off-by: Tom Rini <trini@konsulko.com>
The cflags and ldflags of preload_check_sign depend on the openssl
package thus pkg-config is needed to get the location where openssl
is installed.
This fix a potential build failure when openssl is not from the
distro and installed in a varied place.
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>
When using non-trivial values for parameters for this test it
will cause a spurious failure as the test passes a decimal value
to the mtest command which will interpret it as hexadecimal and
result in failure as below.
test/py/tests/test_memtest.py:66: in test_memtest_ddr
assert expected_response in response
E AssertionError: assert 'Tested 16 iteration(s) with 0 errors.' in 'Refusing to do empty test\r\nmtest - simple RAM read/write test\r\n\r\nUsage:\r\nmtest [start [end [pattern [iterations]]]]'
----------------------------- Captured stdout call -----------------------------
U-Boot> mtest 134217728 0x8001000 90 0x10
Refusing to do empty test
mtest - simple RAM read/write test
Usage:
mtest [start [end [pattern [iterations]]]]
The fix is to ensure that all the parameters to the mtest command are
passed as hexadecimal values.
Fixes: 22efc1cf27 ("test/py: memtest: Add tests for mtest command")
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Love Kumar <love.kumar@amd.com>
If a series is sent without a cover letter, there is no indication of
the base commit. Add support for this, since single patches of small
series may not always have a cover letter.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is helpful to know which commit patches are based on, even if that
commit might not be available to readers. Add a tag for this in the
cover letter.
Also add the local-branch name since that may be useful to the writer.
Signed-off-by: Simon Glass <sjg@chromium.org>
