i.MX95 uses System Manager(sm) API to start/stop logical machine or cpu.
There are two modes:
M7 in a dedicated logical machine, use LMM API
M7 and A55 in same logical machine, use CPU API
Extend the driver to using LMM and CPU protocol to manage the M7 core:
- Detect using LMM or CPU API in probe using API scmi_imx_lmm_info().
- Compare linux LM ID(got using scmi_imx_lmm_info) and M7 LM ID(the ID
is fixed as 1 in SM firmware if M7 is in a separate LM),
if Linux LM ID is not same as M7 LM ID(linux and M7 in same LM), use
LMM protocol to start/stop. Whether using CPU or LMM protocol to
start/stop, the M7 status detection could use CPU protocol to detect
started or not. So in imx_rproc_is_running, use scmi_imx_cpu_started to
check the status of M7.
- For above case (2), Use scmi_imx_lmm_power_boot to detect whether
the M7 LM is under control of A55 LM.
- For above case , after using SCMI_IMX_LMM_POWER_ON to check
permission, scmi_imx_lmm_shutdown API should be called to shutdown
the M7 LM.
- Add a new ops imx_rproc_ops_sm.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add a new flag ATT_ECC which indicates the memory region needs ECC
initialization. If the flag is set, clearing the whole memory region to
initialize ECC. If ECC is not initialized, remote core will crash if
directly access the area.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The i.MX91 SoC reuses the ENET FEC from i.MX93. Add all required driver
checks to make it work also on the i.MX91 based platforms.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
The Kconfig menu "TrueType Fonts" should only be shown if TrueType is
enabled.
Put all TrueType dependent customization within one if statement.
Remove `depends TRUETYPE` clauses.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
George McCollister <george.mccollister@konsulko.com> says:
This patch series brings over several changes from Linux that are required
to get PCIe working on the j722s and also enables PCIe in
j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.
The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1
(using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes
to the three drivers needed to be ported from Linux to enable the REFCLK
output which is used with this SoC. These changes should be tested on other
platforms using these drivers by those with the hardware available to make
sure no problems were introduced.
The PCIe controller in this SoC relies on the code performing the PCI scan
not scanning devices which cannot exist. In Linux this is implemented as
only_one_child() in probe.c. If this mechanism is not used, PCI config reads
for subsequent functions will return information for device 0 resulting in
U-Boot detecting 32 devices when only 1 is present. This change should be
tested on other platforms with PCI to ensure the same PCI devices are
enumerated before and after the patch is applied.
I would like to thank Opto 22 for sponsoring the initial development and
anyone that is able to contribute to testing of patches.
Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com
cmn_refclk_<p/m> lines in Torrent SERDES are used for connecting an
external reference clock. cmn_refclk_<p/m> can also be configured to
output the reference clock. Model this derived reference clock as a
"clock" so that platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in local SERDES
and remote device. Add support here to drive refclk out.
Based on: https://lore.kernel.org/all/20210310120840.16447-7-kishon@ti.com/
Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
cmn_refclk_<p/m> lines in Torrent SERDES are used for an connecting
external reference clock. cmn_refclk_<p/m> can also be configured to
output the reference clock. In order to drive the refclk out from the
SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of
WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM
can enable it.
Based on: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com
Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
Use the same mechanism as the Linux kernel to skip unnecessary (and in
the case of the J722S, errant) scanning of direct children of root
ports, downstream ports or bridges.
Based on Linux PCI code in the following files as of b927546677c8:
drivers/pci/probe.c
drivers/pci/pci.h
include/linux/pci.h
Signed-off-by: George McCollister <george.mccollister@konsulko.com>
Tested-by: Bryan Brattlof <bb@ti.com>
mtdpart internally enumerate partitions starting from zero, but partition
driver API enumerate partitions starting from 1, so wrong partition will
be queried. This is wrong.
Unnecessary debug message also was removed.
Fixes: c29a6daec1 ("disk: support MTD partitions")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
The H6/H616 boot ROM doesn't expect a SPL scrambled the same way as
older SoCs.
It doesn't use a specific seeds table, it expects a maximized ECC
(BCH-80), a specific BBM (FF000301) and doesn't work if empty pages are
skipped (it needs its specific BBM, even in the padding).
So, add a --soc=h6 option to support H6/616 with:
- more ECC strengths
- specific BBM
- default_scrambler_seeds[] with all values
- no empty pages skip
In Kconfig, select BCH-80 by default for SUNXI_SPL_ECC_STRENGTH to make
BROM happy.
And in scripts/Makefile.xpl, use --soc=h6 option when building for a
SUN50I_GEN_H6 SoC.
Tested on Whatsminer H616 board, booting from NAND.
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Co-developed-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The MACRO NFC_PAGE_SHIFT(x) already deals with removing 10 from
nand->page_shift, so it shouldn't be done twice.
Fixes: 4ccae81cda ("mtd: nand: Add the sunxi NAND controller driver")
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Fix a cast to pointer from integer warning on ARM64
On 64bits platform, the casts done in {read,write}l() give that kind of
warnings:
drivers/mtd/nand/raw/sunxi_nand_spl.c: In function ‘check_value_inner’:
./arch/arm/include/asm/io.h:110:43: warning: cast to pointer from \
integer of different size [-Wint-to-pointer-cast]
110 | #define __raw_readl(a) (*(volatile unsigned int *)(a))
| ^
[...]
drivers/mtd/nand/raw/sunxi_nand_spl.c:81:27: note: in expansion of \
macro ‘readl’
81 | int val = readl(offset) & expected_bits;
Introduce {read,write}l_nfc inline function to do the right cast and
push the base address (SUNXI_NFC_BASE) into those functions, making the
code more readable.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce H6/H616 NAND controller support for SPL
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
For SPL, most of the work was setting the clocks, adding the new
capability structure for H616 and supporting the new USER_DATA_LEN
registers.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce H6/H616 NAND controller support for U-Boot
The H616 NAND controller has the same base as A10/A23, with some
differences:
- MDMA is based on chained buffers
- its ECC supports up to 80bit per 1024bytes
- some registers layouts are a bit different, mainly due do the stronger
ECC.
- it uses USER_DATA_LEN registers along USER_DATA registers.
- it needs a specific clock for ECC and MBUS.
Introduce the basic support, with ECC and scrambling, but without
DMA/MDMA.
Tested on Whatsminer H616 board (with and without scrambling, ECC)
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Add MBUS Master Clock Gating Register for H6 and H616
For H6/H616, the NAND controller needs the MBUS NAND clock along with
CLK_NAND0/1 and CLK_BUS_NAND.
The bit locations are from H6/H616 User Manuals.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Use generic macros for ECC_MODE and RANDOM_SEED
As H6/H616 registers are different, use more generic macros than hard
coded values specific to A10-like SoC.
No functional changes.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Increase max_oobsize to take into account bigger OOB on 2KiB pages
Some NAND chip (e.g. Kioxia TC58NVG1S3HTA00) have a 2KiB page size +
128 bytes OOB.
In order to detect them, the max_oobsize has to be increased from 64 to
128 bytes.
Tested on Kioxia TC58NVG1S3HTA00 NAND chip on Whatsminer H616 board.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Use defines instead of hardcoded values for NFC_ECC_{ERR_MSK,PAT_FOUND}
SPL is using hard coded values for ECC error detection and empty chunk
detection.
The H6/H616 registers for that have changed, the pattern found is no
more in the NFC_REG_ECC_ST register.
So, don't presume anymore that pattern_found is in NFC_REG_ECC_ST, and
read the pattern_found register to get this information.
Apart from an additional register reading, no functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce NDFC Spare Area Register offset in SoC capabilities
The H6/H616 spare area register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.
No functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
NFC_RANDOM_{EN,DIRECTION} registers offset moved in H616
Let's make it a SoC capability.
NFC_RANDOM_DIRECTION also moved, but it's unused, just remove it.
No functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce per SoC capabilities in sunxi_nand_spl.c
Prepare for the H616 support that has quite a lot of differences in
registers offset and capabilities.
Start with the 512 bytes ECC capability.
No functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce NDFC Pattern ID Register in capability structure
The H6/H616 pattern ID register is not at the same offset as the
A10/A23 one, so move its offset into sunxi_nfc_caps.
No functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce has_ecc_block_512 capability
The H616 controller can't handle 512 bytes ECC block size. The
NFC_ECC_BLOCK_512 bit disappeared in H6, and NDFC_RANDOM_EN took its
place.
So, add has_ecc_block_512 capability to only set this bit on SoC having
it.
On the way, let's drop NFC_ECC_BLOCK_SIZE_MSK which was just a mask for
the very same bit.
No functional change.
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Move ECC_PAT_FOUND register in SoC capabilities structure
This register offset moved in H616, it's now its own register (@0x3c,
bits 0-31), not shared with NFC_ECC_ST any more (was @0x38 bits 16-31).
Push that specificity in caps structure.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Introduce per SoC capabilities in sunxi_nand.c
This prepares for the H616 support that has quite a lot differences in
registers offset and capabilities.
Start with the ECC strength table.
No functional change.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Merge common register definitions from sunxi_nand{,_spl}.c
The Allwinner NAND controller registers where in both files, so let's
just merge all that in a header, it will be easier for maintenance.
NB: the defines are also harmonized with Linux driver
No functional change
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The sunxi_ccm_reg is legacy, drop its usage from nand related code
For that, CCU_NAND0_CLK_CFG and CCU_AHB_GATE1 are added to the clock
files when missing.
And clock code in sunxi_nand{,_spl}.c and board.c are changed to use the
new scheme.
Moreover, drop AHB_DIV_1 in favor of the more readable CCM_NAND_CTRL_M/N
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Remove unneeded definitions NFC_CMD_R* in sunxi_nand_spl.c
No need to define NFC_CMD_RNDOUTSTART, NFC_CMD_RNDOUT and
NFC_CMD_READSTART here since they are already in linux/mtd/rawnand.h
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Harmonize registers definition in sunxi_nand{,_spl}.c files
This is a first step to then include the same file from both
sunxi_nand{,_spl}.c files
Unused defines are also removed
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Fix pointer from interget warning when compiling for ARM64
When compiling for arm64, we get this error:
error: passing argument 2 of ‘__memcpy_fromio’ makes pointer from
integer without a cast [-Wint-conversion]
Moreover the copy should be made with dedicated readl(), like for any
register access on this peripheral, since they are 32bit wide.
So, instead of memcpy_fromio(), just use a readl() loop.
Introduce nand_readlcpy() to implement this loop.
Fixes: 6ddbb1e936 ("spl: nand: sunxi: use PIO instead of DMA")
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Richard Genoud <richard.genoud@bootlin.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Fix the following typos in drivers/mmc/mmc.c:
- "neiter" -> "neither" in __mmc_switch() comment
- "witdh" -> "width" in bus_width() warning message
- "enver" -> "never" in mmc_select_mode_and_width() comment
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Implement DMA support in the MediaTek MMC driver to enhance data
transfer speed.
- Define DMA control and configuration registers
- Implement functions for starting, stopping, and completing DMA
transfers
- Modify data transfer logic to utilize DMA when enabled
- Ensure proper cache management during DMA operations
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: ht.lin <ht.lin@mediatek.com>
Signed-off-by: Julien Masson <jmasson@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Replace separate mask and shift definitions with GENMASK and FIELD_*
macros for better readability and maintainability.
All macros ending in _M have the suffix dropped. The value remains the
same but is now generated with GENMASK. All macros ending in _S are
removed and their uses replaced with FIELD_PREP and FIELD_GET macros.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Kuan-Wei Chiu <visitorckw@gmail.com> says:
Add support for the QEMU 'virt' machine on the m68k architecture. The
QEMU virt machine models a generic system utilizing Goldfish virtual
peripherals and is capable of emulating various classic 68k CPUs.
Currently, U-Boot's m68k architecture support focuses on ColdFire
variants. This series expands support to include the classic M680x0
architecture, implementing the necessary exception vectors, startup
code, and a bootinfo parser compatible with the QEMU interface.
Drivers for Goldfish peripherals (TTY, Timer, RTC) and the QEMU
Virtual System Controller (sysreset) are also added to enable serial
console, timekeeping, and system reset functionality.
The implementation has been verified on QEMU targeting the M68040 CPU,
confirming successful hardware initialization and boot to the U-Boot
command shell. Additionally, the CI configuration was verified locally
using gitlab-ci-local "qemu_m68k_virt test.py", resulting in
PASS qemu_m68k_virt test.py.
Link: https://lore.kernel.org/r/20260107201838.3448806-1-visitorckw@gmail.com
[trini: Re-sort MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
Introduce a new sysreset driver for the QEMU Virtual System Controller.
This device is found on QEMU "virt" machines (such as the m68k virt
target) and provides a mechanism to trigger system reset and power-off
events.
The driver maps U-Boot sysreset types to the corresponding controller
commands:
- SYSRESET_WARM / SYSRESET_COLD -> VIRT_CTRL_CMD_RESET
- SYSRESET_POWER_OFF -> VIRT_CTRL_CMD_HALT
Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Currently, the Goldfish RTC driver exclusively relies on device tree
to retrieve the base address, failing immediately if dev_read_addr()
returns FDT_ADDR_T_NONE. This restriction prevents the driver from
being used on platforms that instantiate devices via U_BOOT_DRVINFO()
instead of device tree, such as the QEMU m68k virt machine.
Add support for platform data to address this limitation. Introduce a
new .of_to_plat hook to handle device tree parsing and populate the
platform data. Update the probe function to rely exclusively on this
platform data, enabling support for both Device Tree and manual
instantiation.
Introduce a new header file include/goldfish_rtc.h to define the
platform data structure.
Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Add support for the Goldfish timer driver. This driver utilizes the
Goldfish RTC hardware to provide a nanosecond-resolution timer. This
virtual device is commonly found in QEMU virtual machines (such as the
m68k virt machine) and Android emulators.
The driver implements the standard U-Boot timer UCLASS interface,
exposing a 64-bit monotonically increasing counter with a 1GHz clock
rate derived from the RTC registers.
Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Tested-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Yao Zi <me@ziyao.cc>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
Add support for the Google Goldfish TTY serial device. This virtual
device is commonly used in QEMU virtual machines (such as the m68k
virt machine) and Android emulators.
The driver implements basic console output and input polling using the
Goldfish MMIO interface.
Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Yao Zi <me@ziyao.cc>
Tested-by: Daniel Palmer <daniel@0x0f.com>
Acked-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <simon.glass@canonical.com>
Acked-by: Angelo Dureghello <angelo@kernel-space.org>
When the cyclic function video_idle() takes too long, a message like the
following is displayed:
cyclic function video_init took too long: 87707us vs 5000us max
The text "video_init" is misleading. Replace it by "video_idle".
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
- spi: stm32: OSPI and QSPI optimization
- Update stm32 clock drivers to restore boot for STM32MP13/STM32MP2
board family
- Add bootph-all in ltdc node in stm32mp257f-ev1-u-boot
- Use CONFIG_STM32MP15X to discern STM32MP15xx on DH STM32MP15xx DHSOM
- Reinstate missing SPL configs for DH STM32MP15xx DHSOM
- stm32mp2 boards: read boot index from backup register
- video: simple_panel: add support for "rocktech,rk043fn48h" display
- Add .of_to_plat callback in stm32_ltdc driver
