Commit Graph

25990 Commits

Author SHA1 Message Date
Udit Kumar
13654f5426 remoteproc: k3-dsp: Flush D cache after loading firmware
Memory region used by remote cores was set to non-cached region but
commit 7c9c6e1925 ("arm: mach-k3: Merge initial memory maps") makes
all memory region as cached, unified across K3 devices.

This causes inconsistency while booting remote cores on devices, due to
cache incoherency between remote core and boot code.

So to make this operation coherent, cache the address and len while
loading ELF program headers to memory and flush that region in the next
cycle of load.

Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
2025-02-21 11:36:37 -06:00
Weijie Gao
c36945065f arm: mediatek: remove CONFIG_MT8512
Defining CONFIG_MT8512 is unnecessary as now board for mediatek
target can be changed in config.
Use CONFIG_TARGET_MT8512 to replace CONFIG_MT8512.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-21 11:36:37 -06:00
Emanuele Ghidoli
5e4031a5f6 gpio: pca953x: support pcal6408 and pcal6416
Add support to NXP GPIO expanders pcal6408, documented at [1], and
pcal6416, documented at [2].

[1] https://www.nxp.com/docs/en/data-sheet/PCAL6408A.pdf
[2] https://www.nxp.com/docs/en/data-sheet/PCAL6416A.pdf

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2025-02-18 16:32:24 -06:00
Jim Liu
5354774b6b net: designware: Add npcm8xx sgmii pcs support
The PCS exists only in GMAC1 and relates to SGMII interface and
is used to control the SGMII PHY.

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
[trini: Adjust slightly for white space and to move 'start' to within if
        block]
2025-02-18 16:32:24 -06:00
Tom Rini
f36e0d6111 Merge tag 'u-boot-at91-2025.07-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2025.07 cycle:

This feature set includes improvements on the atmel-quadspi driver, a
fix for the nand driver, and improvements on the pinctrl driver to be
able to use the Linux DT (also sync on the DT side as well).
2025-02-18 07:59:59 -06:00
Hironori KIKUCHI
064556910e spi: soft_spi: Add support for SPI_3WIRE
When 3-wire mode is claimed on the bus, use the MOSI (output) pin to
receive data. In this mode, since the transfer can only be either TX
or RX, return -EINVAL if both are required at the same time.

Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
2025-02-14 17:12:49 -06:00
Tom Rini
3f19062d46 Merge patch series "Introduce K3 remoteproc driver for M4 subsystem"
Judith Mendez <jm@ti.com> says:

Some K3 devices like am62x and am64x have a M4 processor in the MCU
voltage domain. This patch series introduces remoteproc M4 driver which
will be used to load firmware into and start the M4 remote core.

This series also adds support for R5F cores on am64x SoCs in patch 2 and
sets up environment to load FW in remote cores in patch 3,4,5.

This patch series also enables remoteproc drivers by default as per what
remoteproc sybsystem is supported per SoC, thus all remoteproc options
are now deleted in configs/* since they are no longer required.

This patch series was tested on am64x EVM, am62x SK, am62ax SK,
am62px SK boards.

Any additional tested by's are welcome since I was not able to
test any additional boards.

Tested by running the following commands in u-boot prompt:

=> setenv dorprocboot 1
=> run boot_rprocs

Link: https://lore.kernel.org/r/20250210202944.1071931-1-jm@ti.com
2025-02-14 13:39:10 -06:00
Judith Mendez
74e1ef648e remoteproc: Enable ARM64 remoteproc driver by default for K3 ARCH
If SYS_K3_SPL_ATF is enabled, for K3 ARCH enable the
remoteproc ARM64 driver by default so that it does not
have to be defined in each board defconfig file.

Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2025-02-14 13:17:34 -06:00
Hari Nagalla
5b96ad41bc remoteproc: k3-r5: Add support for R5F cores on AM64x SoCs
AM64x SoCs have two R5F clusters in the main power domain.
Extend support for R5F remote proc driver on AM64x with compatible
strings.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Andrew Davis <afd@ti.com>
2025-02-14 13:17:26 -06:00
Hari Nagalla
c0e2ce5aee remoteproc: k3-m4: Introduce K3 remote proc driver for M4 subsystem
Some K3 devices like AM64, AM62 devices have a M4 processor in MCU
voltage domain.

Add a remote proc driver to support this subsystem to be able to load
and boot the M4 core.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[Ryan: Fix implicitly include warning]
Signed-off-by: Ryan Eatmon <reatmon@ti.com>
[Judith: Cleanup driver, fix warnings, remove lreset logic]
Signed-off-by: Judith Mendez <jm@ti.com>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Andrew Davis <afd@ti.com>
2025-02-14 13:17:18 -06:00
Tomas Peterka
940135eea5 Kconfig: Move CONFIG_BOOTCOUNT_ALTBOOTCMD to Kconfig
Add CONFIG_BOOTCOUNT_ALTBOOTCMD so the developer is able to add
custom altbootcmd via Kconfig when they enable BOOTCOUNT. With this now
in Kconfig, we need to move it from environment files / config.h files
and in to the defconfig file.

This was done by generating u-boot-initial-env for all platforms before
the Kconfig change, to extract altbootcmd values and then again after to
compare the result.

[trini: Perform migration to defconfigs, reword commit message]
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-02-14 10:19:24 -06:00
Alexander Dahl
344e2f2cd4 mtd: nand: raw: atmel: Fix pulse read timing for certain NAND flashes
From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse time must be at least tREA.

Without this fix we got PMECC errors when reading, after switching to
ONFI timing mode 3 on SAM9X60 SoC with S34ML02G1 raw NAND flash chip.

The approach to set timings used before worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.

The approach to fix the issue was carried over from at91bootstrap, and
has been successfully tested in at91bootstrap, U-Boot and Linux.

Link: https://github.com/linux4sam/at91bootstrap/issues/174
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:49:56 +02:00
Manikandan Muralidharan
2925a046f5 pinctrl: at91: Add support to align with Linux Devicetree
U-Boot pinctrl driver expects a reg property explicitly unlike linux.
To align the DT of U-boot with the Linux, reg property is also arrvied
from child GPIO bank nodes when configured under the pinctrl node.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-02-12 10:31:56 +02:00
Manikandan Muralidharan
8e502c0e2c pinctrl: at91: Bind GPIO driver to the pinctrl DT node
In Linux DT,the pinctrl node acts as parent nodes with all other
gpio banks as child nodes and a single driver in Linux handles both
pinctrl settings and gpio requests.Current U-Boot DT maintains both
pinctrl and gpio nodes as separate nodes and offers two different class
of U-Boot drivers: UCLASS_PINCTRL which handles pin functions and
UCLASS_GPIO which handles gpio requests. In order to align the DT
of U-Boot with the DT of Linux, a hook is been added in the pinctrl
driver to bind the gpio driver with the pinctrl driver so that
when adding gpio nodes as subnodes to pinctrl node (as per the Linux ABI),
the corresponding APIs will be redirected and handled by valid
drivers attached to the pinctrl driver.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-02-12 10:31:56 +02:00
Alexander Dahl
3a25277320 spi: atmel-quadspi: Improve probe debugging
Report spi clk speed and make use of `log_ret()`.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
de2d304d81 spi: atmel-quadspi: Add support for classic SPI mode
The qspi controller on sama5d2 and sam9x60 supports "classic" SPI mode
without spi-mem enhancements and accelerations, very similar to the old
SPI controller on sam9g20 or the modern flexcom controllers of the same
SoC family.

Register interface differs somewhat, especially because only one
hardware controlled CS line is supported.  Some fields are missing, some
are in different registers, but in principal it works similar.  So code
is very much inspired by the old atmel-spi driver.

Tested on sam9x60 with a non-mainline driver to configure an FPGA.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
1acf68f3d4 spi: atmel-quadspi: Allow setting SMM to classic SPI mode
Switching between Serial Memory Mode (SMM) and (classic) SPI mode is a
preparation for implementing .xfer() in the future.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
6c1ec67460 spi: atmel-quadspi: Remove default mode setting at probe time
The Serial Memory Mode (SMM) is enabled with atmel_qspi_set_cfg() on
each invocation of atmel_qspi_exec_op().  Setting SMM through
atmel_qspi_init() at probe time is redundant.

Removing the SMM setting at probe time should therefore 1) be safe to do
and 2) allows for setting it to a different value in a future
implementation of .xfer() which needs to disable SMM.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
5095ae1510 spi: atmel-quadspi: Avoid overwriting MR register settings
Port these commits:

- v6.11-rc5-90-g329ca3eed4a9a ("spi: atmel-quadspi: Avoid overwriting delay register settings")
- v6.12-rc1-1-g162d9b5d2308c ("spi: atmel-quadspi: Fix wrong register value written to MR").
- v6.13-rc2-27-gf663898d047a7 ("spi: atmel-quadspi: Factor out switching to Serial Memory Mode to function")

Cc: Csókás Bence <csokas.bence@prolan.hu>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
6a9e8d6d21 spi: atmel-quadspi: Port collected fixes from Linux v5.10 and v5.15
Port changes from a 4 piece patch series from Linux kernel v5.10, merged
with v5.10-rc1-83-gc732b7567d869 ("Merge series "spi: atmel-quadspi: Fix
AHB memory accesses" from Tudor Ambarus …").

Port the single fix v5.15-rc1-14-g09134c5322df9 ("spi: Fixed division by
zero warning").

Reduces differences between linux and u-boot driver.

Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: Yoshitaka Ikeda <ikeda@nskint.co.jp>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
d3ded566db spi: atmel-quadspi: Depend on SPI_MEM
Most other spi-mem drivers also depend on SPI_MEM.  Fixes this build
error:

    arm-v5te-linux-gnueabi-ld.bfd: drivers/spi/atmel-quadspi.o: in function `atmel_qspi_supports_op':
    /mnt/data/adahl/src/u-boot/drivers/spi/atmel-quadspi.c:460: undefined reference to `spi_mem_default_supports_op'
    make[1]: *** [/mnt/data/adahl/src/u-boot/Makefile:1821: u-boot] Error 1

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-12 10:29:33 +02:00
Alexander Dahl
0a82e3e471 spi: ca_sflash: Remove redundant dependency
This is inside of an 'if DM_SPI' block, and thus always true.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-12 10:29:33 +02:00
Simon Glass
5f6a59e03e test: Keep track of suite duration
Show the time taken by each test suite with 'ut all' and the total time
for all suites.

Take care to remove any sandbox time-offset from the values.

Fix the comment-format on timer_test_add_offset() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-02-11 20:10:58 -06:00
Michal Simek
5b280448bb rtc: emul_rtc: Make emul_rtc_probe() static
emul_rtc_probe() is not called from anywhere else that's why make it
static. Issue is reported by build with W=1.

Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-02-10 10:29:10 -06:00
Michael Chang
8897f91a53 net: designware: support phy io micro voltage setting.
Support phy io micro voltage setting for NPCM8XX rgmii
interface.

Signed-off-by: Michael Chang <zhang971090220@gmail.com>
2025-02-10 10:28:36 -06:00
Weijie Gao
a081512cbd pinctrl: mediatek: support reading register base address by name
This patch add support to read register base address by name if
provided.

Also devfdt_get_addr_* is changed to dev_read_addr_* to support DT
live tree.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-10 10:26:47 -06:00
Weijie Gao
d5d130dd12 pinctrl: mediatek: mt7988: remove _base from reg-names
The reg-names in mt7988.dtsi have no _base suffix. Remove the suffix
will also make it match upstream linux format.

Fixes: 8c2cb748ef (pinctrl: mediatek: mt7988: rename reg-names to upstream linux format)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-10 10:26:47 -06:00
Tom Rini
7a20c89bd0 Merge patch series "led: add function naming option from linux"
Heiko Schocher <hs@denx.de> says:

In linux we have the option to create the name of a led
optionally through the following properties:

- function
- color
- function-enumerator

This series adds support for parsing this properties if there
is no label property.

Link: https://lore.kernel.org/r/20250128135246.74838-1-hs@denx.de
[trini: Document name parameter in led.h]
2025-02-07 11:39:24 -06:00
Heiko Schocher
592b6f394a led: add function naming option from linux
in linux we have the option to create the name of a led
optionally through the following properties:

- function
- color
- function-enumerator

This patch adds support for parsing this properties if there
is no label property.

The led name is created in led_post_bind() and we need some
storage place for it. Currently this patch prevents to use
malloc() instead it stores the name in new member :

        char name[LED_MAX_NAME_SIZE];

of struct led_uc_plat. While at it append led tests for the
new feature.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-07 10:53:39 -06:00
Tom Rini
c2e00482d0 Merge tag 'xilinx-for-v2025.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx changes for v2025.04-rc2

fpga:
- Cleanup help
- Show xilinx only options on Xilinx devices

ospi-versal:
- Fix alignment issue
- Fix cadence_qspi_flash_reset() prototype

zynqmp:
- Define usb_pgood_delay
- Fix bootseq number

versal:
- Fix mini_ospi configuration

versal2:
- Enable OPTEE

xilinx:
- Enable some flashes
- Clean up SYS_MALLOC_F_LEN Kconfig
- Some binman fixes
- DT updates
- Enable mkfwumdata compilation
- Enable meminfo command
- Switch to LWIP and enable HTTPS
2025-02-06 08:09:54 -06:00
Alexander Dahl
135d2926d2 fpga: Avoid ignored-qualifiers warning
Fixes annoying warnings of the following type when built with W=1 (for
each file including fpga.h):

      CC      drivers/fpga/fpga.o
    In file included from /mnt/data/adahl/src/u-boot/include/xilinx.h:7,
                     from /mnt/data/adahl/src/u-boot/drivers/fpga/fpga.c:10:
    /mnt/data/adahl/src/u-boot/include/fpga.h:61:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       61 | const fpga_desc *const fpga_get_desc(int devnum);
          | ^~~~~
    /mnt/data/adahl/src/u-boot/include/fpga.h:81:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       81 | const fpga_desc *const fpga_validate(int devnum, const void *buf,
          | ^~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/fpga.c:36:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       36 | const fpga_desc *const fpga_get_desc(int devnum)
          | ^~~~~
    /mnt/data/adahl/src/u-boot/drivers/fpga/fpga.c:53:1: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
       53 | const fpga_desc *const fpga_validate(int devnum, const void *buf,
          | ^~~~~

Do some type and cast cleanup on that fpga_desc type while at it.

Link: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wignored-qualifiers
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20250121162213.1477506-1-ada@thorsis.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-02-05 16:22:55 +01:00
Venkatesh Yadav Abbarapu
e5c9c4dd06 spi: cadence_qspi: Add missing prototype for cadence_qspi_flash_reset
Add missing prototype to fix the sparse warning,
warning: no previous prototype for 'cadence_qspi_flash_reset'
[-Wmissing-prototypes].

Fixes: 6d234a79e9 ("cadence_qspi: Refactor the flash reset functionality")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250122135334.1201562-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-02-05 16:22:55 +01:00
Padmarao Begari
1621851495 spi: cadence_qspi: Fix OSPI DDR mode alignment issue
If the least significant bit of the address is set to one when
using the DDR protocol for data transfer then the results are
indeterminate for few flash devices. To fix this the least
significant bit of the address is set to zero.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Link: https://lore.kernel.org/r/20250106095120.800753-1-padmarao.begari@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-02-05 16:22:55 +01:00
Marek Vasut
30a8c830e9 net: miiphybb: Update debug() print
Update the debug() print, use __func__ to always print matching
function name, and also print bus name in case there are multiple
busses.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-02-04 23:34:42 +01:00
Marek Vasut
b1001835f1 net: miiphybb: Convert ifdef DEBUG to debug()
Replace ifdeffery with plain debug() function call. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-02-04 23:34:37 +01:00
Marek Vasut
5392ad2fd9 remoteproc: renesas: Synchronize caches across cores
Explicitly flush icache on the CR52 core before jumping to the next
stage software to make sure it does not contain any invalid content.
Explicitly flash and invalidate dcache on the CA76 core both over the
trampoline buffer and over the CR52 firmware, and then trigger full
system synchronization, to make sure the data surely land in DRAM,
from where the CR52 can surely pick them up.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-02-04 23:32:00 +01:00
Tom Rini
bfaed6969c Merge patch series "mediatek: final preparation for OF_UPSTREAM support"
Christian Marangi <ansuelsmth@gmail.com> says:

This is the last batch of part to push actual support of
OF_UPSTREAM for the mediatek SoC.

The plan is to make the current downstream DTS on part with
upstream implementation so we can permit a gradual transition to
it while we don't cause any regression to any user.

This is to have the same node downstream and upstream.
Mediatek is working hard upstream to also push all the remaining
nodes.

All patch are the final changes after the pinctrl patch
merged previously.

All patch pass CI tests

Link: https://github.com/u-boot/u-boot/pull/731
Link: https://lore.kernel.org/r/20250127134046.26345-1-ansuelsmth@gmail.com
2025-02-04 11:57:36 -06:00
Christian Marangi
8b1ea8a4b9 pinctrl: mediatek: mt7981: rename reg-names to upstream linux format
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Simon Glass
00ae9b2ac3 mmc: Allow controlling DM_MMC for VPL builds
VPL may want to use driver model for MMC even if TPL does not. Update
the rule in this driver to support that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-02-03 16:00:42 -06:00
Hal Feng
b6d150b949 pinctrl: starfive: Correct driver declaration for starfive_gpio
Use the driver macros so that the driver appears in the
linker list.

Reported-by: Simon Glass <sjg@chromium.org>
Fixes: 732f01aabf ("pinctrl: starfive: Add StarFive JH7110 driver")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
2025-02-03 11:33:04 +08:00
Weijie Gao
7f95b5d7e6 net: mediatek: fix coding style of AN8855 switch driver
This patch fixed the following coding style suggested by checkpatch.pl:
1. Use tab instead of space
2. Use BIT() instead of <<
3. Use mdelay for long time delay
4. Remove useless parenthesises

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-31 11:29:01 -06:00
Weijie Gao
ea02a07728 pinctrl: mediatek: update mt7981 pinctrl driver based on upstream kernel
Update mt7981 pinctrl driver based on upstream kernel

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-31 11:28:59 -06:00
Neil Armstrong
664a257777 scsi: do not fill the LUN in the second CDB byte
The SCSI specification originally required that the second
Command Data Byte contain the LUN value in its high-order bits,
but this field has been marked as reserved since the SCSI-3 spec
from 1996.

Some vendors uses this byte to pass vendor specific data,
and specifying the LUN can trigger strange behaviors.
For the record, this happened on an UFS device where LUN0 was
working perfectly and reading the other LUNs would get the last
buffer data that was read for LUN0, making this issue very very
hard to debug.

It's sane to assume U-Boot will probably never encounter
an SCSI-2 multi-LUN device, if somehow it happens the enquiry
command would need to get the SCSI level to handle this case.

The Linux fix was added in [1] to fix the exact same issue.

[1] https://lore.kernel.org/all/Pine.LNX.4.44L0.1409021108380.2308-100000@iolanthe.rowland.org/

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-01-31 11:28:55 -06:00
Tom Rini
a582e48533 Merge tag 'u-boot-stm32-20250131' of https://source.denx.de/u-boot/custodians/u-boot-stm
STM32 MPU:
- Remove dt-bindings headers available in dts/upstream
- Fixes for stm32prog
- Enable CONFIG_SYS_64BIT_LBA for STM32MP15/13/25 defconfigs
- Add upport of ck_usbo_48m in pre-reloc stage for STM32MP13
- Clean env_get_location() for STM32MP1
- Fix board_get_usable_ram_top() to fix infinite loop in cache
  management for STM32MP2.
- Fix ck_flexgen_08 frequency for STM32MP2

STM32 MCU:
- Tune CYCLIC_MAX_CPU_TIME_US to avoid cyclic warning for STM32F469-Disco
- Tune CYCLIC_MAX_CPU_TIME_US to avoid cyclic warning for STM32F769-Disco
2025-01-31 08:32:11 -06:00
Patrice Chotard
eb04f32c9b fastboot: Fix warning when CONFIG_SYS_64BIT_LBA is enable
If CONFIG_SYS_64BIT_LBA is enable, following compilation warning is
triggered:

 CC      drivers/fastboot/fb_mmc.o
../drivers/fastboot/fb_mmc.c: In function 'fb_mmc_erase_mmc_hwpart':
../drivers/fastboot/fb_mmc.c:215:35: warning: format '%lu' expects
argument of type 'long unsigned int', but argument 2 has type
'long long unsigned int' [-Wformat=]
  215 |         printf("........ erased %lu bytes from mmc hwpart[%u]\n",
      |                                 ~~^
      |                                   |
      |                                   long unsigned int
      |                                 %llu
  216 |                dev_desc->lba * dev_desc->blksz, dev_desc->hwpart);
      |                ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      |                              |
      |                              long long unsigned int
../drivers/fastboot/fb_mmc.c: In function 'fb_mmc_boot_ops':
../drivers/fastboot/fb_mmc.c:261:42: warning: format '%lu' expects
argument of type 'long unsigned int', but argument 2 has type
'long long unsigned int' [-Wformat=]
  261 |                 printf("........ wrote %lu bytes to EMMC_BOOT%d\n",
      |                                        ~~^
      |                                          |
      |                                          long unsigned int
      |                                        %llu
  262 |                        blkcnt * blksz, hwpart);
      |                        ~~~~~~~~~~~~~~
      |                               |
      |                               long long unsigned int

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2025-01-31 08:57:39 +01:00
Patrick Delaunay
2599223fa7 stm32: remove dt-binding headers that are available upstream
Some dt-binding headers mask the upstream ones which can lead to build
failures, or worse: super weird bugs, if they get out of sync.

Remove these headers so our devicetree and binding headers will both be
in sync with upstream.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2025-01-31 08:46:51 +01:00
Marek Vasut
487b254702 net: phy: Add RGMII RX/TX delay handling to DP83822 PHY
The TI DP83822 does have support for configurable RGMII RX/TX clock
shift, add support for parsing DT properties which describe the RX/TX
clock shift configuration and configuration of the matching bits in
RCSR register.

The shift is only configurable on DP83822, the other PHYs supported
by this PHY driver, namely DP83825/DP83826 variants, do not implement
this functionality and the RCSR bits used to configure the clock shift
are missing from those PHYs.

The shift is configurable separately for RX and TX path. Each path can
either enable the shift or disable the shift using single bit. In case
the shift is disabled, a delay of 0ns is added to the path, otherwise
a delay of 3.5ns is added to the path.

Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12
enables RX internal shift when SET, while RCSR bit 11 enables TX shift
when UNSET.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-30 19:28:33 -06:00
Tom Rini
ac3eeb1542 Merge patch series "Add support for MediaTek MT7987 SoC"
Weijie Gao <weijie.gao@mediatek.com> says:

This patch series add support for MediaTek MT7987 SoC with its reference
boards and related drivers.

This patch series add basic boot support on eMMC/SD/SPI-NOR/SPI-NAND for these
boards. The clock, pinctrl drivers and the SoC initializaton code are also
included.

Link: https://lore.kernel.org/r/cover.1737621362.git.weijie.gao@mediatek.com
2025-01-30 14:35:30 -06:00
Weijie Gao
e5d20906f7 mmc: mediatek: add support for MediaTek MT7987 SoCs
This patch adds eMMC/SD support for MT7987 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-30 14:35:14 -06:00
Weijie Gao
21fb382845 pinctrl: mediatek: add pinctrl driver for MT7987 SoC
This patch adds pinctrl and gpio support for MT7987 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-30 14:35:14 -06:00