Commit Graph

15 Commits

Author SHA1 Message Date
Tom Rini
aff68c8514 Merge tag 'u-boot-socfpga-next-20250930' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.
2025-09-30 16:11:23 -06:00
Wadim Egorov
ac046ad187 board: phytec: phycore_am6xx: Update scriptaddr
After switching our boards to standard boot, we observed that the
kernel hangs when booting with the "script" boot method over the
network.

The original scriptaddr value was copied from ti_common.env and
remained unused for some time. On phycore-am62x and phycore-am62ax,
however, this address conflicts with the current location where
ATF is loaded (CONFIG_K3_ATF_LOAD_ADDR).

Move scriptaddr to 0x89100000, directly after fdtoverlay_addr_r.
The phycore-am64x is not affected by this issue, but we update it
as well to keep all phycore-am6xx boards consistent.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Anshul Dalal <anshuld@ti.com>
2025-09-24 07:50:13 -06:00
Tom Rini
fceb37d802 Merge tag 'v2025.10-rc3' into next
Prepare v2025.10-rc3
2025-08-25 13:28:49 -06:00
Wadim Egorov
03baafe062 board: phytec: phycore_am6xx: Add rauc to bootmeths
Add rauc to bootmeths variable if BOOTMETH_RAUC is enabled.
This is setting a proper default for RAUC enabled systems.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Martin Schwan <m.schwan@phytec.de>
2025-08-25 10:15:16 -06:00
Wadim Egorov
cc6291e3b4 board: phytec: phycore-am62ax: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value.
Users can enable the watchdog to monitor the boot process until userspace
or OS takes over to serve the watchdog.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-08-11 14:53:56 -06:00
Sam Protsenko
70a4d1fa1d treewide: Remove empty board_init() function from all boards
Commit 86acdce2ba ("common: add config for board_init() call")
introduced CONFIG_BOARD_INIT option. This option can be disabled for the
boards where board_init() function is not needed. Remove empty
board_init() calls for all boards where it's possible, and disable
CONFIG_BOARD_INIT in all related defconfigs.

This cleanup was made semi-automatically using these scripts: [1].

No functional change, but the binary size for the modified boards is
reduced a bit.

[1] https://github.com/joe-skb7/uboot-convert-scripts/tree/master/remove-board-init

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mm_beacon
Tested-by: Bryan Brattlof <bb@ti.com>
Acked-by: Peng Fan <peng.fan@nxp.com>  #NXP boards
2025-07-24 13:30:19 -06:00
Wadim Egorov
e423e35d0d board: phytec: phycore_am6xx: Set bootmeths & boot_targets environment
As part of our migration to the standard boot process, configure the
default values for the bootmeths and boot_targets environment variables.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-22 13:51:55 -06:00
Andrew Davis
feb5516523 board: ti: sec-cfg.yaml: Fix OTP write_host_id order
The write_host_id is the last element here and order does matter. This
may have gone unnoticed before as by default all elements are 0, but
if this is updated to a different host, it will not work. Update
the order so write_host_id is the last element in all current secure
board configs.

Reported-by: Prashant Shivhare <p-shivhare@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
2025-05-09 15:10:33 -06:00
Daniel Schultz
fd446b0c84 board: phytec: phycore_am62ax: Update Environment
Add fit_addr_r to the environment to allow us to boot from a FIT image.

Increase the maximum Image size from 23 MB to 26 MB by moving the
initramfs start address up. This gives us a bigger ranger to
provide kernel images which are not stripped down too much.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2025-05-07 07:59:03 -06:00
Tom Rini
cb7555e930 Merge patch series "*** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs ***"
Wadim Egorov <w.egorov@phytec.de> says:

Add general ethernet boot support for AM62Ax SoC.
Some of the work is based on TI's downstream u-boot patches found in
[1], patches touching code in mach-k3 and *.yaml board config files.

Also, provide defconfigs and device tree changes for phyCORE-AM62x and
phyCORE-AM62Ax to support booting via ethernet.

[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem

Link: https://lore.kernel.org/r/20250325035824.2304200-1-w.egorov@phytec.de
2025-04-10 15:04:09 -06:00
Wadim Egorov
e41c21acce configs: Add phycore_am62ax_r5_ethboot_defconfig
Provide a defconfig for booting the phycore-am62ax via Ethernet.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-04-10 15:03:32 -06:00
Nathan Morrisson
5327b62c12 board: phytec: phycore_am62ax: Share ethernet resources with boot r5 core
During the U-Boot SPL R5 boot stage the code is running on the MAIN R5
core, which means a host ID of 36 is used for DM/TIFS communication,
see [1]. In order to enable Ethernet boot update the DMA resources used
to be shared with the MAIN R5 core instead of the MCU R5 core.

[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62ax/hosts.html

Based on patch 19 from https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem

Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-04-10 15:03:32 -06:00
Wadim Egorov
d78bc6ea9f board: phytec: phycore_am62ax: Add Network/SPI/DFU env variables
Include the boot logic to boot via Network, from a OSPI/QSPI
NOR flash or via USB DFU.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-03-18 08:12:53 -06:00
Wadim Egorov
adf4d5e9e8 configs: Add phycore_am62ax_r5_usbdfu_defconfig
This config includes the phycore_am62ax_r5_defconfig file as well as
the am62x_r5_usbdfu.config fragment. We need another defconfig
because the AM62Ax has not enough internal SRAM to support all boot
sources. The normal phycore_am62ax_r5_defconfig should allow to boot
from MMC and OSPI while this new defconfig allows to boot from USB.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
2025-03-18 08:12:53 -06:00
Garrett Giordano
d13e67c24d board: phytec: am62a7: Add PHYTEC phyCORE-AM62A7 SoM
Add support for PHYTEC phyCORE-AM62A7 SoM.

Supported features:
  - 2GB LPDDR4 RAM
  - eMMC
  - External SD
  - Ethernet
  - debug UART

Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
2024-12-13 17:30:01 -06:00