'apt-get update -y' may be required to make sure that the list of
packages is up-to-date and that the subsequent 'apt-get install'
operations can find the requested packages.
Fixes the following CI error:
Fetch: zstd
- trying method: binary download
- sudo apt-get install -y zstd
Exception: Error 100 running 'sudo apt-get install -y zstd': E: Unable to locate package zstd
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Bryan Brattlof <bb@ti.com>
The statement that prints the ELF object type value assumes that "%lx"
(long unsigned int, hexadecimal) is suitable for printing a uint64_t
typed value. While this may seem to work for some machines, ie. amd64,
it isn't ideal on a 32-bit system, such as x86 where uint64_t is likely
to be equivalent to a long long unsigned int, as indicated by:
../tools/mips-relocs.c:275:34:
warning: format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'uint64_t'
{aka 'long long unsigned int'} [-Wformat=]
275 | printf("type 0x%lx\n", ehdr_field(e_type));
| ~~^
| |
| long unsigned int
| %llx
As the ehdr_field function-like macro expands to a uint64_t value,
it is better to use the PRIx64 macro in place of "%lx" to ensure that
the correct format string introducer is specified for the actual type
hiding behind uint64_t.
A similar issue is also present in the report of .rel section overflow,
where "%lx" is used to print a few size_t typed values, and would be
better served by "%zx" instead.
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
Fixes: 9630146411 ("MIPS: make size of relocation table fixed but configurable")
Fixes: 703ec9ddf9 ("MIPS: Stop building position independent code")
Cc: Paul Burton <paulburton@kernel.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Masahiro Yamada <masahiroy@kernel.org>
The xorl macro lacked surrounding parens which meant that it could have
unexpected results when used in expressions. Fix this by adding the
surrounding parens to make its use predictable.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Using strcpy to copy a 4 character string into a 4 byte field in a
structure will overflow that field as it writes the terminating \0 into
the following field. Correct this by using memcpy instead.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
In boot_from_devices the variable loader is not NULL checked after
assignment and before first use but later code does check it for NULL.
Add a NULL check before first use.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Since SYS_MALLOC_F_LEN increasing to 0x2100000 on STM32MP13, the
pre-console buffer is overlapped by stack (0xC0400000 + 0x2100000),
so the this buffer must be moved just before the bootstage to avoid issue.
After this patch the pre-relocation memory mapping for STM32MP13x is:
C3000000 = Bootstage CONFIG_BOOTSTAGE_STASH_ADDR
C2FFF000 = PreConsole CONFIG_PRE_CON_BUF_ADDR
with size CONFIG_PRE_CON_BUF_SZ = 4096
C0400000 = start for stack with CONFIG_CUSTOM_SYS_INIT_SP_ADDR
including CONFIG_SYS_MALLOC_F_LEN
C0000000 = Load Address of U-Boot with CONFIG_TEXT_BASE
Fixes: 93c962c7af7e ("configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Update defconfig to make use of U-Boot SPL to initialize DH STM32MP13xx
DHCOM DHSBC SoM and board. This is largely a move of SPL enablement from
DH STM32MP15xx DHSOM defconfigs into generic DH STM32MP1xx defconfig .
Support for SPI NOR chips which are not used on STM32MP13xx DHCOR are
moved into STM32MP15xx DHSOM defconfigs. Changes to STM32MP13xx DHCOR
defconfig then enable SPL support, CCF in SPL to configure clock, pin
configuration support in SPL, and OpTee OS start support in U-Boot.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add SPL specific DT additions to DH STM32MP13xx DHCOR DHSBC . These
include I2C3 configuration which is required to access the PMIC,
PMIC regulator and QSPI NOR bootph-all properties to allow SPL to
configure PMIC buck regulators and load from QSPI NOR respectively,
etzpc bus switch to simple-bus to prevent interference from TFABOOT
specific configuration, and RCC configuration to define clock tree
configuration used by this platform.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add DT additions required by U-Boot SPL to bring up the hardware.
This includes binman node to generate STM32 Image v2.0 which can be
booted by the BootROM, clock entries used by the SPL clock driver
during clock tree initialization, and syscon-reboot node so U-Boot
can reset the system without having to rely on PSCI call.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Factor out common parts of STM32MP15xx DRAM controller configuration DT
description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
describes STM32MP13xx DRAM controller configuration in DT.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add default STM32MP13xx debug UART initialization. This is similar
to STM32MP15xx debug UART initialization, except the RCC registers
are at different offsets and the UART pinmux pins are different.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
to the STM32MP15xx PMIC initialization, except the VTT rail is not
enabled. Fill in the STM32MP13xx support.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add hardware initialization for the STM32MP13xx in SPL. This is
similar to STM32MP15xx except the code has to enable MCE to bring
DRAM controller up later.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Introduce Kconfig options used by SPL on STM32MP13xx and isolate
the Kconfig options only used in case TFA BL2 is used as a SPL
behind CONFIG_TFABOOT dependency.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Commit aa7bdc1af5 ("clk: scmi: manage properly the clk identifier with
CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
real SCMI CLK ID, otherwise wrong ID is used when set clk parent.
Fixes: aa7bdc1af5 ("clk: scmi: manage properly the clk identifier with
CCF")
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
be included using "stm32-reset-core.h" and not <stm32-reset-core.h> ,
otherwise the build fails. Fix it.
Fixes: 0994a627c2 ("reset: stm32mp25: add stm32mp25 reset driver")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Enable the following configs:
- CONFIG_MFD_STM32_TIMERS: enables support for the STM32 multifunction
timer
- CONFIG_DM_PWM: enables support for pulse-width modulation devices
- CONFIG_CMD_PWM: enables 'pwm' command to control PWM channels
- CONFIG_PWM_STM32: enables support for the STM32 PWM devices
Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add support for STM32MP25 SoC.
IPIDR register is used to check the hardware configuration register
when available to gather the number of complementary outputs.
Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add support for STM32MP25 SoC.
Identification and hardware configuration registers allow to read the
timer version and capabilities (counter width, ...).
So, rework the probe to avoid touching ARR register by simply read the
counter width when available. This may avoid messing with a possibly
running timer.
Also add useful bit fields to stm32-timers header file.
Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Second set of u-boot-at91 features for the 2025.10 cycle:
This feature set includes the addition of new sama7d65 SoC and a new
board named sama7d65-curiosity.
A dependency exposed by "make allyesconfig" is that the logic around
this symbol was not quite correct. It needs to depend on ARCH_MVEBU and
ARM64 and then select CLK_MVEBU.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Enable bootstd.
Update defconfigs to the latest u-boot requirements.
Enable SYS_THUMB_BUILD and LTO and to reduce binary size.
Enable NET_RANDOM_ETHADDR.
Disable JFFS2 support.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
mac_read_from_eeprom() always display debug infos, and this messes up the
display of the "Net:" section details:
Before:
Net: EEPROM: TlvInfo v1 len=172
eth0: ethernet@11c20000
After:
Net: eth0: ethernet@11c20000
Fix by moving unconditional "EEPROM: " header into each message and
changing debug message to use log_debug().
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
In a private fork, it's not unreasonable to commit various binary
files associated to one's project, and thus put a suitable
.gitattributes file next to it to force git to treat that file as
binary. In my case, I have a .xslx spreadsheet used for computing
suitable RAM timing tables, which I wanted to put in
board/<vendor>/<project>. Git duly warned me that it would do LF/CRLF
mangling, so I also added a .gitattributes file next to it with
*.xlsx binary
but upon adding that file, git told me that I'd have to use -f because
it's a dot-file that is by default ignored.
Add .gitattributes to the list of dot-files that should not be
ignored.
While in here, sort the list and update the comment, as there are also
files which git itself does not make use of in the list, cf. linux
commit f46e65da48b2 (".gitignore: exclude .get_maintainer.ignore and
.gitattributes").
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
Reviewed-by: Tom Rini <trini@konsulko.com>
In do_bootvx the environment variable 'bootdev' is fetched and copied
into a buffer without confirming that it will not overflow that buffer.
Use strlcpy to ensure that the buffer will not be overflowed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
These patches add support for the new Allwinner A523/A527/T527 SoC (all
same die), alongside with defconfigs for three boards using one of those
SoCs.
The patches are the usual combination of refactoring (of the SPL clock
code this time), tweaks to existing drivers to support peripherals in
their A523 versions, and new drivers for pincontrol and clocks. A big
chunk is of course the DRAM controller init routines, many thanks to
Jernej and Mikhail for providing this code, after a big reverse
engineering effort.
Since the DTs for the three supported boards have been merged into the
kernel repo recently, this is concluded by cherry-picks of those
patches, and the defconfig files to finally enable booting those boards.
The patches have been sitting around for a while, and folks are already
using them, so it's now time to get them into the tree.
Gitlab CI passed, and I booted that briefly on those three boards, plus
on some other SoCs to spot potential regressions.
So far developers seem to use three popular boards:
- Avaota A1: dev board with USB 3.0, dual Ethernet, small display
- X96QPro+: TV box with Gigabit Ethernet, USB 3.0, eMMC
- Radxa A5E: small dev board with USB3/M.2 2230 (muxed), dual Ethernet
Add the defconfig files for those boards, containing the DRAM parameters
and the usual Kconfig options.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The Avaota A1 router board is an Open Source hardware board, designed
by YuzukiHD. Pine64 produces some boards and sells them. It uses the
Allwinner A527 or T527 SoC, and comes with the following features:
- Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU
- 1GiB/2GiB/4GiB LPDDR4 DRAM
- AXP717 + AXP323 PMIC
- Raspberry-Pi-2 compatible GPIO header
- 1 USB 2.0 type A host port, 1 USB 3.0 type A host post
- 1 USB 2.0 type C port (OTG + serial debug)
- MicroSD slot
- eMMC between 16 and 128 GiB
- on-board 16MiB bootable SPI NOR flash
- two 1Gbps Ethernet ports (via RTL8211F PHYs)
- HDMI port
- DP port
- camera and LCD connectors
- 3.5mm headphone jack
- (yet) unsupported WiFi/BT chip
- 1.3" LC display, connected via SPI
- 12 V barrel plug for power supply
Add the devicetree file describing the currently supported features.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-12-andre.przywara@arm.com
[wens@csie.org: Squash in SD card detect pull resistor fix]
Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: dbe54efa32afe5b82763c015cbe9e64c4d4e117a ]
(cherry picked from commit ebcb8469ef4336c05c6b9f409714a23cfc891fff)
The Radxa A5E is a development board using the Allwinner A527 SoC, which
is using the same die as the A523 SoC, just exposing the pins of more
peripherals (like HDMI or the 2nd MAC). The board features:
- Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU
- 1GiB/2GiB/4GiB LPDDR4 DRAM
- AXP717 + AXP323 PMICs
- Raspberry-Pi-2 compatible 40pin GPIO header
- 1 USB 2.0 type C port (OTG), also power supply
- 1 USB 3.0 type A host port (multiplexed with M.2 slot)
- 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed
with USB 3.0 port)
- MicroSD slot
- optional eMMC, 8, 16 or 32GB available
- optional on-board 16MiB bootable SPI NOR flash
- two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs)
- PoE header for optional supply circuit on one Ethernet port
- WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800)
- HDMI port
- camera and LCD connectors
- power supply via USB-C connector (but no PD) or GPIO header pins
This .dts describes the devices as far as we support them at the moment.
The PMIC rails have been assigned as per the schematics.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-14-andre.przywara@arm.com
[wens@csie.org: Squash in SD card detect pull resistor fix]
Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com
[wens@csie.org: Rename dts file to sun55i-a527-cubie-a5e.dts]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: c2520cd032ae8ca3fdaf77b3f3aa687c8cb7843f ]
(cherry picked from commit 91ad117321c0901094c1d6467df90f5f6757569a)
The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to
be a package variant of the A523 family, at least it uses the same SoC
ID and is compatible as far as we can assess.
It comes with the following specs:
- Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU
- 2 or 4GiB DDR3L DRAM
- 32, 64, or 128 GiB eMMC flash
- AXP717 + AXP323 PMICs
- Gigabit Ethernet (using MAXIO PHY)
- HDMI port
- 2 * USB 2.0 ports
- 1 * USB 3.0 port
- microSD card slot
- TOSLINK digital audio output
- 3.5mm A/V port
- infrared sensor
- 7-segment display
- 5V barrel plug power supply
- power button
The PCB provides holes for soldering a UART header or cable, this is
connected to the debug UART0. There is another set of UART pins
available. The board also features a FEL button (accessible through the
3.5mm socket) and a reset button (only accessible when case is open).
This .dts just describes the basic peripherals as far as we support them
at the moment. The PMIC rail assignments are reverse engineered as far
as possible, by dumping them from a running Android system, and correlating
them to other boards using the same SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-13-andre.przywara@arm.com
[wens@csie.org: Squash in SD card detect pull resistor fix]
Link: https://patch.msgid.link/20250425003422.3465-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: 4ee87d875071390b4e24ce46dbdd792216d61651 ]
(cherry picked from commit 693da0a03149b77a3e2bc11cfd314df8cc2fab40)
The Allwinner A523, and its siblings A527 and T527, which share the same
die, are a new family of SoCs introduced in 2023. They features eight
Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and
USB 3.0 controller.
Add the basic SoC devicetree .dtsi for the chip, describing the
fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl.
Also some other peripherals are fully compatible with previous IP, so
add the USB and MMC nodes as well.
The other peripherals will be added in the future, once we understand
their compatibility and DT requirements.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20250307005712.16828-9-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[ upstream commit: 35ac96f796649346c9b0440413dc6c5138249b3e ]
(cherry picked from commit 247a3572abcfd7a0d48e12f8f810f1cbae5ce4f4)
Add the basic Kconfig options, addresses and other values for the
existing Kconfig settings for the new Allwinner A523/T527/H728 SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
