Commit Graph

866 Commits

Author SHA1 Message Date
Svyatoslav Ryhel
e9245a360a pinctrl: tegra: detect unknown/invalid pin/func configurations
Applies same logic to general Tegra pincontrol driver as is done to Tegra20
by commit:

a35bf832d7 ("pinctrl: tegra20: detect unknown/invalid pin/func
configurations")

Suggested-by: Artur Kowalski <arturkow2000@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-04-12 09:48:01 +03:00
Artur Kowalski
a35bf832d7 pinctrl: tegra20: detect unknown/invalid pin/func configurations
Tegra20 driver doesn't know about some pin configurations and even about
some pins. In case when pin configuration is unknown the pin would be
muxed to whatever is under function 0, in case when pin itself is
unknown, it could cause out-of-bounds array access in pinmux_set_func
and pinmux_set_pullupdown.

Signed-off-by: Artur Kowalski <arturkow2000@gmail.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-04-12 09:47:42 +03:00
Tom Rini
407d68638f Merge patch series "Switch to using $(PHASE_) in Makefiles"
Tom Rini <trini@konsulko.com> says:

This series switches to always using $(PHASE_) in Makefiles when
building rather than $(PHASE_) or $(XPL_). It also starts on documenting
this part of the build, but as a follow-up we need to rename
doc/develop/spl.rst and expand on explaining things a bit.

Link: https://lore.kernel.org/r/20250401225851.1125678-1-trini@konsulko.com
2025-04-11 12:16:49 -06:00
Tom Rini
302b41d539 Kbuild: Always use $(PHASE_)
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-04-11 12:16:44 -06:00
Caleb Connolly
91ba4976c0 pinctrl: qcom: handle reserved ranges
Some Qualcomm boards feature reserved ranges of pins which are protected
by firmware. Attempting to read or write any registers associated with
these pins results the board resetting.

Add support for parsing these ranges from devicetree and ensure that the
pinctrl and GPIO drivers don't try to interact with these pins.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250410-topic-sm8x50-pinctrl-reserved-ranges-v2-1-654488392b9a@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-04-11 15:30:21 +02:00
Alexey Minnekhanov
b4420a0c9e drivers: pinctrl: Add Qualcomm SDM630/660 TLMM driver
Add support for TLMM pin controller block (Top Level Mode
Multiplexer) on SDM630/660 SoCs, with support for special pins.

Correct pin configuration is required for working debug UART
and eMMC/SD cards.

SDM630 and SDM660 TLMM blocks are the same.

Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250331155531.3638165-1-alexeymin@postmarketos.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-04-11 15:25:51 +02:00
Varadarajan Narayanan
5effb1e625 pinctrl: qcom: add driver for SA8775P SoC
Add pinctrl and GPIO driver for SA8775P. Driver code is based on the
similar U-Boot and Linux drivers.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250324080504.2385747-1-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-04-10 15:43:09 +02:00
Tom Rini
9b4b86f90c Kconfig: Fix "warning: style: quotes recommended" warnings
We have three warnings about needing to use quotes around some strings
in Kconfig files today. In two of these cases we can just add the
missing strings. In the case of INTEL_PINCTRL_PADCFG_PADTOL the symbol
is never referenced and should be dropped.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-04-01 08:46:18 -06:00
Tom Rini
02d95aaee0 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sunxi into next
Assorted fixes, refactorings and additions that are ready, and shave
off some load from upcoming series'.

Improves MMC performance on D1/T113 (missed clock divider), enables
eMMC access on the H616 family (never worked, many thanks to Jernej for
the fix!), DRAM detection fixes for the H616 (now reportedly stable).

Some patches for the upcoming Allwinner A133 SoC support: a few
refactorings, plus the DM clock and pinctrl driver. The DRAM init
routines work, but need some more polishing, that also holds back the
actual enablement patch, which will hopefully follow for v2025.07 still.

Also some preparatory patches for the Allwinner A523 SoC support, for
now just to improve the FEL save/restore code. There will be more patches
coming up for this, ideally also in the coming cycle still.

Gitlab CI passed, and I booted that briefly on some boards.
2025-03-27 08:10:06 -06:00
Andre Przywara
17c1add327 pinctrl: sunxi: add Allwinner A100/A133 pinctrl description
The Allwinner A100 SoC has been around for a while, and has now seemingly
been replaced with its close sibling A133.

Add the required mapping between the pinmux group strings and their
respective mux value, as far as used by U-Boot proper. Linux has some
basic (clock and pinctrl) support for a while, so we can build on the
names already used there.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2025-03-27 00:26:35 +00:00
Tom Rini
4adbf64ff8 Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next
- More Tegra video improvements
2025-03-26 14:07:37 -06:00
Svyatoslav Ryhel
59bc308221 pinctrl: tegra: adjust default values of pins
The current default pin and drive values were more of temporary
placeholders. They have to be replaced with accurate default values as
specified in the TRM and header file.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-03-19 10:59:24 +02:00
Caleb Connolly
69aab56740 pinctrl/qcom: fix kconfig option names
A copy-paste error is starting to get out of hand... Fix all these so
they don't look like clock drivers in menuconfig.

Link: https://lore.kernel.org/r/20250317132519.46080-1-caleb.connolly@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-03-17 15:12:26 +00:00
Caleb Connolly
51ec7fdb64 pinctrl: qcom: add sc7280 pinctrl driver
Introduce a pinctrl driver for SC7280/QCM6490, this is used by the RB3
Gen 2, FairPhone 5 and other devices.

Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20250122-pinctrl-sc7280-v1-1-8bdba72e6366@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-03-17 13:38:18 +00:00
Varadarajan Narayanan
1b734e0190 pinctrl: qcom: Add ipq9574 pinctrl driver
Add pinctrl driver for the TLMM block found in the ipq9574 SoC.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-6-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-03-17 13:38:17 +00:00
Varadarajan Narayanan
6ec61fd462 pinctrl: qcom: Handle get_function_mux failure
Presently, get_function_mux returns an unsigned int and cannot
differentiate between failure and correct function value. Change its
return type to int and check for failure in the caller.

Additionally, updated drivers/pinctrl/qcom/pinctrl-*.c to accommodate the
above return type change. Only compile test done.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-5-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-03-17 13:38:17 +00:00
Tom Rini
81ef65099e Merge patch series "drivers: Driver support for ADI SC5xx SoCs"
Greg Malysa <malysagreg@gmail.com> says:

This series adds all of the supported peripheral drivers for the sc5xx
series of SoCs from Analog Devices and other drivers that are used by
the evaluation kits, such as a GPIO expander used by the EZLITE carrier
boards. This series passes gitlab CI tests.

Link: https://lore.kernel.org/r/20250226173150.13198-1-malysagreg@gmail.com
2025-03-12 10:25:13 -06:00
Greg Malysa
79ccd6c7dc pinctrl: Add support for ADI SC5XX-family pinctrl
This adds support for pin configuration on the Analog Devices SC5XX SoC
family. This commit is largely a port of the Linux driver, which has not
yet been submitted upstream.

Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Co-developed-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
Signed-off-by: Greg Malysa <malysagreg@gmail.com>
2025-03-12 10:24:58 -06:00
Tom Rini
0731697f9d Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next 2025-03-12 07:56:16 -06:00
Marek Vasut
0e5f1b8f05 pinctrl: renesas: Drop special RZN1 entry from Makefile
The RZN1 symbol name is CONFIG_RZN1, there is no CONFIG_ARCH_RZN1.
Since RZN1 enables CONFIG_ARCH_RENESAS as well, remove the special
RZN1 entry from Makefile, the RZN1 pinctrl driver will still be
pulled in via CONFIG_ARCH_RENESAS.

Fixes: e4aea57fa7 ("pinctrl: renesas: add R906G032 driver")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-03-11 23:05:57 +01:00
Tom Rini
1b42f57ec8 Merge tag 'v2025.04-rc4' into next
This uses Heinrich's merge of lib/efi_loader/efi_net.c which results in
no changes.
2025-03-10 20:18:51 -06:00
Caleb Connolly
554562f7b5 pinctrl: qcom: sm8250: fix pin count
The pin count wasn't updated when the special pins were added, as a
result it was never possible to configure the special pins on SM8250
boards.

Fix the pin count and allow the special pins to be configured. This
fixes sdcard support on the RB5.

Fixes: 58fa520424 ("pinctr: qcom: sm8250: add special pins pins configuration data")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-02-26 13:48:27 +00:00
Svyatoslav Ryhel
a237a20993 pinctrl: tegra: add Tegra K1 support
Tegra 124 is fully compatible with existing Tegra pincontrol
driver, but it needs a specific MIPI PAD control pinconfig.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-26 13:08:19 +02:00
Tom Rini
3ecda19009 Merge tag 'v2025.04-rc3' into next
Prepare v2025.04-rc3
2025-02-24 17:15:14 -06:00
Jonas Karlman
d5a3fb9ef8 pinctrl: rockchip: rk3328: Fix pinmux for GPIO2-B and GPIO3-B pins
The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
recalculated so it remain unchanged. Add missing GPIO3-B1 to GPIO3-B7
pinmux data to rk3328_mux_recalced_data as mux register offset for these
pins does not follow rockchip convention.

This matches changes in following Linux commits:
- e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
- 5ef6914e0bf5 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins")
- 128f71fe014f ("pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins")

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-02-19 23:24:48 +08:00
Svyatoslav Ryhel
efb7964cc1 pinctrl: tegra20: adjust pin type detection
Pin detection on t20 depends on node name. With recent changes
in node naming, let's remove '_' to be safe about both '_' or
'-' use.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-02-12 10:35:17 +02:00
Manikandan Muralidharan
2925a046f5 pinctrl: at91: Add support to align with Linux Devicetree
U-Boot pinctrl driver expects a reg property explicitly unlike linux.
To align the DT of U-boot with the Linux, reg property is also arrvied
from child GPIO bank nodes when configured under the pinctrl node.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-02-12 10:31:56 +02:00
Manikandan Muralidharan
8e502c0e2c pinctrl: at91: Bind GPIO driver to the pinctrl DT node
In Linux DT,the pinctrl node acts as parent nodes with all other
gpio banks as child nodes and a single driver in Linux handles both
pinctrl settings and gpio requests.Current U-Boot DT maintains both
pinctrl and gpio nodes as separate nodes and offers two different class
of U-Boot drivers: UCLASS_PINCTRL which handles pin functions and
UCLASS_GPIO which handles gpio requests. In order to align the DT
of U-Boot with the DT of Linux, a hook is been added in the pinctrl
driver to bind the gpio driver with the pinctrl driver so that
when adding gpio nodes as subnodes to pinctrl node (as per the Linux ABI),
the corresponding APIs will be redirected and handled by valid
drivers attached to the pinctrl driver.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
2025-02-12 10:31:56 +02:00
Weijie Gao
a081512cbd pinctrl: mediatek: support reading register base address by name
This patch add support to read register base address by name if
provided.

Also devfdt_get_addr_* is changed to dev_read_addr_* to support DT
live tree.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-10 10:26:47 -06:00
Weijie Gao
d5d130dd12 pinctrl: mediatek: mt7988: remove _base from reg-names
The reg-names in mt7988.dtsi have no _base suffix. Remove the suffix
will also make it match upstream linux format.

Fixes: 8c2cb748ef (pinctrl: mediatek: mt7988: rename reg-names to upstream linux format)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-10 10:26:47 -06:00
Tom Rini
bfaed6969c Merge patch series "mediatek: final preparation for OF_UPSTREAM support"
Christian Marangi <ansuelsmth@gmail.com> says:

This is the last batch of part to push actual support of
OF_UPSTREAM for the mediatek SoC.

The plan is to make the current downstream DTS on part with
upstream implementation so we can permit a gradual transition to
it while we don't cause any regression to any user.

This is to have the same node downstream and upstream.
Mediatek is working hard upstream to also push all the remaining
nodes.

All patch are the final changes after the pinctrl patch
merged previously.

All patch pass CI tests

Link: https://github.com/u-boot/u-boot/pull/731
Link: https://lore.kernel.org/r/20250127134046.26345-1-ansuelsmth@gmail.com
2025-02-04 11:57:36 -06:00
Christian Marangi
8b1ea8a4b9 pinctrl: mediatek: mt7981: rename reg-names to upstream linux format
Rename reg-names to upstream linux format. Upstream linux drop the
"_base". To make use of upstream DTSI, align to the upstream naming.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Tested-by: Weijie Gao <weijie.gao@mediatek.com>
2025-02-04 10:20:36 -06:00
Hal Feng
b6d150b949 pinctrl: starfive: Correct driver declaration for starfive_gpio
Use the driver macros so that the driver appears in the
linker list.

Reported-by: Simon Glass <sjg@chromium.org>
Fixes: 732f01aabf ("pinctrl: starfive: Add StarFive JH7110 driver")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
2025-02-03 11:33:04 +08:00
Weijie Gao
ea02a07728 pinctrl: mediatek: update mt7981 pinctrl driver based on upstream kernel
Update mt7981 pinctrl driver based on upstream kernel

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-31 11:28:59 -06:00
Tom Rini
ac3eeb1542 Merge patch series "Add support for MediaTek MT7987 SoC"
Weijie Gao <weijie.gao@mediatek.com> says:

This patch series add support for MediaTek MT7987 SoC with its reference
boards and related drivers.

This patch series add basic boot support on eMMC/SD/SPI-NOR/SPI-NAND for these
boards. The clock, pinctrl drivers and the SoC initializaton code are also
included.

Link: https://lore.kernel.org/r/cover.1737621362.git.weijie.gao@mediatek.com
2025-01-30 14:35:30 -06:00
Weijie Gao
21fb382845 pinctrl: mediatek: add pinctrl driver for MT7987 SoC
This patch adds pinctrl and gpio support for MT7987 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2025-01-30 14:35:14 -06:00
Marek Vasut
07358b7ac6 pinctrl: imx: Split MMIO accessors into pinctrl-imx-mmio.c
Split MMIO accessors into pinctrl-imx-mmio.c and build this
file only if Kconfig symbol PINCTRL_IMX_MMIO is selected.
Select PINCTRL_IMX_MMIO Kconfig symbol for all but pinctrl-imx8.c
driver, which does not use the MMIO accessors. This reduces the
amount of code compiled on platforms which do not use the code.

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
90890e9086 pinctrl: imx: Fold imx_pinctrl_set_state_scu() from pinctrl-imx8.c
The only user of the SCU pinctrl code is pinctrl-imx8.c , fold
the entire pinctrl-scu.c code into pinctrl-imx8.c and remove the
matching Kconfig symbols and Makefile entries. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
fe40330471 pinctrl: imx: Split imx_pinctrl_set_state_scu() from imx_pinctrl_set_state_mmio()
Call imx_pinctrl_set_state_common() from imx_pinctrl_scu_conf_pins(),
rename imx_pinctrl_scu_conf_pins() to imx_pinctrl_set_state_scu().
Get rid of the unnecessary ifdeffery in pinctrl-imx.h in the process.
Remove all SCU support from pinctrl-imx.c imx_pinctrl_set_state_mmio()
which makes that function a pure MMIO pinctrl configuration accessor.
Update pinctrl-imx8.c to call imx_pinctrl_set_state_scu directly.

No functional change.

This patch is best viewed with git show -w due to indent change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
40c477c71c pinctrl: imx: Split imx_pinctrl_set_state() into common and mmio parts
Split imx_pinctrl_set_state() into imx_pinctrl_set_state_common() and
imx_pinctrl_set_state_mmio(). The former does the common configuration
parsing, the later does call imx_pinctrl_set_state_common() and then
does pin configuration using either SCU or MMIO accesses. The SCU part
is going to be moved out in follow up patches.

This is a preparatory patch for follow up pinctrl drivers which
do not use the MMIO accessors, but some other means, like SCU or
otherwise. Those will call the common imx_pinctrl_set_state_common()
function wrapped into some other imx_pinctrl_set_state_*() function,
in a way similar to imx_pinctrl_set_state_mmio() does so for MMIO
accesses.

Update all imx_pinctrl_set_state_mmio() call sites to call
imx_pinctrl_set_state_mmio() instead.

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
ecd087dffe pinctrl: imx: Rename imx_pinctrl_remove() to imx_pinctrl_remove_mmio()
The current implementation of imx_pinctrl_remove() is specific
to the MMIO accessor implementation, rename the function to
imx_pinctrl_remove_mmio() to make this obvious. No functional
change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
7ddd6d3c21 pinctrl: imx: Split imx_pinctrl_probe() into common and mmio parts
Split imx_pinctrl_probe() into imx_pinctrl_probe_common() and
imx_pinctrl_probe_mmio(). The former does the common setup, the
later does the common setup and MMIO access configuration. The
common setup can be used as-is for SCU based systems, update
the pinctrl-imx8 to call only the common setup, update all the
other pinctrl drivers to call imx_pinctrl_probe_mmio().

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
def8012d5b pinctrl: imx: Inline struct imx_pinctrl_soc_info access into probe
The probe function is identical across all the pinctrl drivers.
Inline the imx_pinctrl_soc_info access into imx_pinctrl_probe()
and drop all the duplicate probe functions. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
106cc434e0 pinctrl: imx: Drop .remove callback for SCU variant
The return callback for SCU variant of the pinctrl drivers does
nothing but returns 0. Remove the return callback from the SCU
driver itself, that has the same effect. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
a8f628040d pinctrl: imx: Rename imx_pinctrl_ops to match drivers
Rename the structure instances to match driver names, so they
can be easily looked up e.g. in objdump and readelf outputs.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Marek Vasut
a27409be4d pinctrl: imx: Push imx_pinctrl_ops into drivers and staticize
Move imx_pinctrl_ops into drivers and staticize. This is preparatory
patch for follow up pinctrl drivers which will not use this variant
of imx_pinctrl_ops content. This should not change size, as most of
the deployments compiled in one pinctrl driver anyway. No functional
change.

Signed-off-by: Marek Vasut <marex@denx.de>
2025-01-25 09:06:32 -03:00
Neil Armstrong
767a1e57fa pinctrl: qcom: x1e80100: add pcie[3456ab]_clk functions
Add the missing PCIe clk_req function for the x1e80100 TLMM.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-pinctrl-v1-3-4df323d90397@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22 16:35:39 +01:00
Neil Armstrong
7acf090d27 pinctrl: qcom: sm8650: add pcie[01]_clk_req_n function
Add the missing PCIe clk_req functions for the SM8650 TLMM.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-pinctrl-v1-2-4df323d90397@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22 16:35:39 +01:00
Neil Armstrong
7ca1b3f0d9 pinctrl: qcom: sm8550: add pcie1_clk_req_n function
Add the missing PCIe clk_req function for the SM8550 TLMM.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-pinctrl-v1-1-4df323d90397@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22 16:35:39 +01:00
Neil Armstrong
51a142363d pinctrl: qcom: Add X1E80100 pinctrl driver
Add pinctrl driver for the TLMM block found in the X1E80100 SoC.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # Yoga Slim 7x
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20241115-topic-x1e80100-pinctrl-v1-1-35f984226e47@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-01-22 16:35:02 +01:00