3 Commits

Author	SHA1	Message	Date
Ye Li	01aa4cd8ba	imx8ulp: ddr: Fix DDR frequency request issue ... After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>	2022-02-05 13:38:39 +01:00
Jacky Bai	b80ec768a3	imx8ulp:ddr: saving the dram config timing data into sram ... On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>	2022-02-05 13:38:39 +01:00
Ye Li	7a6577fed4	ddr: Add DDR driver for iMX8ULP ... Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>	2021-08-09 14:46:51 +02:00