Commit Graph

666 Commits

Author SHA1 Message Date
Tom Rini
0dd455e064 Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv into next
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/25323

- board: k1: Add reset driver
- board: starfive: Simplify binman config
- Some modifications on DTS and configs
2025-03-25 08:57:00 -06:00
Huan Zhou
9c40d92305 Add reset config options for k1
Add RESET_SPACEMIT_K1 option in config.

Signed-off-by: Huan Zhou <me@per1cycle.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-03-25 16:34:50 +08:00
Huan Zhou
d5b621d8b5 riscv: dts: k1: add reset controller node in device tree
Add reset-controller in k1 device tree.

Signed-off-by: Huan Zhou <me@per1cycle.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-03-25 16:31:44 +08:00
Heinrich Schuchardt
29dbfbeba4 riscv: dts: starfive: remove duplicate itb entries
As binman already creates nodes based on CONFIG_OF_LIST we don't need to
add extra nodes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> # StarFIve VisionFive 2
Reviewed-by: E Shattow <e@freeshell.de>
2025-03-25 16:25:45 +08:00
Heinrich Schuchardt
b8903f550b riscv: dts: no default configuration for MULTI_DTB_FIT
JH7110 boards are currently the only use case for multi DTB FIT images
on RISC-V.

Booting JH7110 systems with a VisionFive 2 device-tree used to kind of
work without causing harm to the hardware. But there is no guarantee
that this will hold true in future. So we should not rely on it.

Before the current patch series booting failed on unsupported boards due
to the lack of a device-tree in the binman generated default configuration
when reaching main U-Boot.

By not setting a default configuration booting will now fail on
unsupported boards already in SPL. This allows SPL to
continue with the next boot source for a possible recovery.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: E Shattow <e@freeshell.de>
2025-03-25 16:25:31 +08:00
Heinrich Schuchardt
70000885ee riscv: dts: add OF_LIST handling to binman.dtsi
Binman can automatically generate device-tree and configuration entries in
the FIT image based on CONFIG_MULTI_DTB_FIT if the binman node includes the
right sub-nodes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: E Shattow <e@freeshell.de>
2025-03-25 16:25:26 +08:00
Yao Zi
a44f389263 riscv: dts: cv18xx: Drop unused dummy clocks
Introduced in commit 5a4e0625ac ("riscv: dts: sophgo: Add ethernet
node"), eth_{csrclk,ptpclk} were used as placeholders for ethernet
controller. As the real clock controller has been added, drop them to
clean the devicetree up.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-03-25 16:00:23 +08:00
Junhui Liu
f1ba590136 riscv: dts: spacemit: Update UART compatible for k1
Update UART compatible in k1 dts to "intel,xscale-uart", introduced in
commit 2d84e1519c ("serial: ns16550: Add Intel XScale support")
recently, aligning dts with the upstream kernel.

Tested-by: Huan Zhou <me@per1cycle.org>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
2025-03-25 16:00:01 +08:00
Tom Rini
647cb87b5a Merge tag 'v2025.04-rc5' into next
Prepare v2025.04-rc5
2025-03-24 20:10:55 -06:00
Tom Rini
8bc3542384 Merge patch series "pxe: Precursor series for supporting read_all() in extlinux / PXE"
Simon Glass <sjg@chromium.org> says:

This series includes some patches related to allowing read_all() to be
used with the extlinux / PXE bootmeths.

These patches were split out from the stb4 series, since it will need to
have additional patches for LWIP, to avoid breaking PXE booting when
LWIP is used.

Link: https://lore.kernel.org/r/20250306002533.2380866-1-sjg@chromium.org
2025-03-18 13:12:51 -06:00
Simon Glass
098407e673 boot: arm: riscv: sandbox: Add a format for the booti file
Arm invented a new format for arm64 and something similar is also used
with RISC-V. Add this to the list of supported formats and provide a way
for the format to be detected on both architectures.

Update the genimg_get_format() function to support this.

Fix up switch() statements which don't currently mention this format.
Booti does not support a ramdisk, so this can be ignored.

Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-18 13:12:15 -06:00
Sam Edwards
214a87757a arm: riscv: efi: Export _start symbol from crt0_*_efi stubs
While the _start label is only intended for use locally to populate the
(hand-written) PE header, the linker script includes ENTRY(_start) which
designates it as the entry point in the output ELF, resulting in linker
warnings under some linkers (e.g. LLVM's lld) due to _start not being a
globally-visible symbol. Since  ELF is only an intermediary build
format, and the aforementioned PE header correctly points to _start, the
ENTRY(_start) directive could easily be removed to silence this warning.

However, since some developers who are debugging EFI by analyzing the
intermediary ELF may appreciate having correct entry-point information,
this patch instead promotes the _start labels to global symbols,
silencing the linker warning and making the intermediary ELF reflect the
true entry point.

This patch doesn't affect the final output binaries in any way.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2025-03-17 09:22:03 +01:00
Minda Chen
05aa34cef9 spl: starfive: visionfive2: Disable USB overcurrent pin by default.
For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled in spl stage.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: E Shattow <lucent@gmail.com>
2025-03-17 01:55:19 +01:00
Ilias Apalodimas
ec1c6cfb1c treewide: Add a function to change page permissions
For armv8 we are adding proper page permissions for the relocated U-Boot
binary. Add a weak function that can be used across architectures to change
the page permissions

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905X-CC
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-14 13:37:54 +02:00
Tom Rini
3e73373c37 Merge patch series "xPL-stack cleanup"
Simon Glass <sjg@chromium.org> says:

This series was split from the VBE part H series. It adjusts the logic
for selecting the top of the stack so that it is more consistent across
xPL phases.

Link: https://lore.kernel.org/r/20250228122042.1277079-1-sjg@chromium.org
2025-03-13 10:36:11 -06:00
Simon Glass
ffa98c08e8 spl: Use CONFIG_VAL() to obtain the SPL stack
Now that we have the same option for SPL and TPL, simplify the logic for
determining the initial stack.

Note that this changes behaviour as current SPL_STACK is a fallback for
TPL. However, that was likely unintended and can be handled with Kconfig
defaults if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Suggested-by: Tom Rini <trini@konsulko.com>
2025-03-13 10:36:10 -06:00
Simon Glass
d6a53f523a spl: Add an SPL_HAVE_INIT_STACK option
At present there is a hex value SPL_STACK which both determines whether
SPL has its own initial stack and the hex value of that stack.

Split off the former into SPL_HAVE_INIT_STACK with SPL_STACK depending
on that and only providing the latter.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Resync defconfig files]
2025-03-13 10:36:09 -06:00
Tom Rini
124b75644c Merge tag 'u-boot-dfu-next-20250310' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next
u-boot-dfu-next-20250310

CI:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/25060

Usb gadget:
- Remove legacy CONFIG_USB_DEVICE
- Remove legacy usbtty driver
2025-03-10 10:13:03 -06:00
Tom Rini
7f061aba9a usb: gadget: Remove final remnants of CONFIG_USB_DEVICE
The lone user of the legacy USB device framework have been removed for
some time. Remove the final parts of the code that were missed.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20250227205101.4127604-1-trini@konsulko.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2025-03-10 09:22:35 +01:00
Heinrich Schuchardt
7082c9e656 common: clean up setjmp.h
Separate setjmp.h into an architecture independent part and an architecture
specific part. This simplifies moving from using struct jmp_buf_data
directly to using type jmp_buf in our code which is the C compliant way.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-03-10 07:41:16 +01:00
Yao Zi
faf237d1b4 riscv: cpu: jh7110: fallback to generic cleanup_before_linux()
JH7110 SoC requires no specific handling before entering Linux kernel.
Let's drop the specific implementation to avoid duplication.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:06 +08:00
Yao Zi
334980f4cf riscv: cpu: generic: fallback to generic cleanup_before_linux()
The current implementation is equivalent to the fallback one, so
this shouldn't change any behaviour but cleans the code up only.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:06 +08:00
Yao Zi
f88e3b7739 riscv: add a generic implementation for cleanup_before_linux()
Most RISC-V SoCs have similar cleanup_before_linux() functions. Let's
provide a weak symbol as fallback to reduce duplicated code.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:06 +08:00
Yu-Chien Peter Lin
47d90f6bd3 riscv: dts: binman.dtsi: Include OP-TEE OS image
The following diagram illustrates the boot flow for OP-TEE OS
initialization on RISC-V.

    (1)-----------+
     | U-Boot SPL |
     +------------+
         |
         v
    (2)-------------------------------------------------------------+
     | OpenSBI (fw_dynamic.bin)                                     |
     |                (4)------------------------+                  |
     |                 | optee dispatcher driver |                  |
     +-----------------+-------^---------|-------+------------------+
M-mode   |                     |         |
---------+--[trusted domain]---+----.----+--[untrusted domain]-------
S-mode   |  (coldboot domain)  |    |    |
         v                     |    |    v
    (3)---------------------------+ |(5)----------------------------+
     | OP-TEE OS (tee.bin)        | | | U-Boot (u-boot-nodtb.bin)   |
     +----------------------------+ | +-----------------------------+
                                    |    |
                                    |    v
                                    |(6)----------------------------+
                                    | | Linux                       |
                                    | +-----------------------------+

This patch enables the inclusion of the OP-TEE binary within the
U-Boot ITB, allowing it to be loaded to a platform defined address
by U-Boot SPL.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:00 +08:00
Yu-Chien Peter Lin
99654e1b96 riscv: Add CONFIG_SPL_OPTEE_LOAD_ADDR
Allow specifying load address of OP-TEE binary. It is
recommended that the specified address aligns with the
base address of an PMP-protected NAPOT region and matches
the CFG_TDDRAM_START configuration in OP-TEE.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 15:26:00 +08:00
Heinrich Schuchardt
490be9de22 riscv: AVAILABLE_HARTS is not compatible with XIP
If CONFIG_AVAILABLE_HARTS=y, variable available_harts_lock is created in
the data section which will not be writable while executing from flash.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 11:33:04 +08:00
Huan Zhou
3691fbccfc riscv: spacemit: k1: probe dram size during boot phase.
Implement functionality to probe and calculate the DRAM size
during the boot phase for the RISC-V spacemit K1 platform.

Tested-by: Marcel Ziswiler <marcel@ziswiler.com> # BPI-F3 16G
Signed-off-by: Huan Zhou <me@per1cycle.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-02-03 11:33:04 +08:00
Heinrich Schuchardt
216459d2cf efi_loader: correct SizeOfCode, SizeOfInitializedData
The fields SizeOfCode, SizeOfInitializedData, and SizeOfUninitializedData
are define in the PE-COFF specification [1].

* SizeOfCode must match the size of all .text sections.
* SizeOfInitializedData must match the size of all .data sections.
* SizeOfUninitializedData must match the size of all .bss sections.

We only have one .text and one .data section. SizeOfCode and
SizeOfInitializedData have to be calculated as the difference between
the end and the start of the respective section.

As we don't have any .bss sections in the generated EFI binaries.
SizeOfUninitializedData must remain 0.

[1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-01-17 20:31:26 +01:00
Heinrich Schuchardt
6a628c1503 efi_loader: use INCLUDE in EFI linker scripts
Except for the architecture specific lines ARM and RISC-V can use the same
linker script. Move the common lines to an include.

Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-01-17 20:31:26 +01:00
Junhui Liu
78d9ce3e36 riscv: cpu: k230: Add support for Canaan Kendryte K230 SoC
Add Canaan K230 SoC with sysreset support, running without cache
enabled.

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-01-16 15:55:27 +08:00
Junhui Liu
a1135b7526 riscv: dts: canaan: Add basic device tree for K230 CanMV board
Add initial dts for K230-CanMV powered by Canaan Kendryte K230 SoC,
which has two RISC-V C908 cores, a big core with vector 1.0 extension
and a small core without vector extension.

This patch is basically comes from Linux Kernel [1] and it assumes
u-boot is running on the big core. Additionally, bootctl and reboot nodes
are added to support sysreset [2] and an clk_dummy node is added to
satisfy dependencies for usb [3].

Currently, u-boot is booted by the vendor's u-boot-spl. To meet the
requirements [4][5] of vendor's u-boot-spl for u-boot, a binman node with
mkimage child node is added here, which will compress u-boot.bin with
gzip and generate an image named "uboot" in the file u-boot-gz.img.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/?h=k230-basic
[2] https://github.com/kendryte/k230_sdk/blob/v1.8/src/big/rt-smart/kernel/bsp/maix3/board/interdrv/sysctl/sysctl_boot/sysctl_boot.c#L67
[3] https://lore.kernel.org/linux-riscv/tencent_AD84B436C2F31108B66B4739D6E306C5E80A@qq.com/
[4] https://github.com/kendryte/k230_sdk/blob/v1.8/src/little/uboot/board/canaan/common/k230_img.c#L306
[5] https://github.com/kendryte/k230_sdk/blob/v1.8/src/little/uboot/board/canaan/common/k230_img.c#L125

Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-01-16 15:55:27 +08:00
Mayuresh Chitale
4492c8db60 riscv: Fallback to riscv,isa
Update the cpu probing to fallback to "riscv,isa" property if
"riscv,isa-extensions" is not available and modify the riscv CMO code
to use the block size that was probed during cpu setup.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-01-16 15:34:18 +08:00
Mayuresh Chitale
ab15e20ea9 riscv: Enhance extension probing
Enhance the existing extension probing mechanism by adding support for
more extensions and probing using the "riscv,isa" property. This patch
is ported from the latest upstream linux.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-01-16 15:34:18 +08:00
E Shattow
9c4d760637 riscv: dts: starfive: split out visionfive2 target specific configuration
Split out StarFive VisionFive2 multi-board target specific configuration
into starfive-visionfive2-binman.dtsi in preparation for removal of
jh7110-u-boot and jh7110-common-u-boot in part or whole as sent upstream.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-01-16 15:34:05 +08:00
Tom Rini
f4e8711965 Merge patch series "Select CONFIG_64BIT for sandbox64 and x86_64"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Picking up a series from Dan Carpenter and applying requested
changes for v2.

I had previously set CONFIG_64BIT for arm64.  This patchset does the
same thing for sandbox and x86_64.  (Mips and riscv were already
doing it).  This CONFIG option is used in the Makefile to determine
if it's a 32 or 64 bit system for the CHECKER.

Makefile
  1052  # the checker needs the correct machine size
  1053  CHECKFLAGS += $(if $(CONFIG_64BIT),-m64,-m32)

Link: https://lore.kernel.org/r/20241216180736.1933807-1-andrew.goodbody@linaro.org
2024-12-31 10:58:36 -06:00
Andrew Goodbody
99145eec2d x86: select CONFIG_64BIT for X86_64
Select CONFIG_64BIT so that we pass the -m64 option (instead of -m32) to
static analysis tools.
Introduce CONFIG_SPL_64BIT and select it for architectures other than
x86 with 64 bit builds. Do not select it for x86 builds as x86 uses
a 32 bit SPL.
Ensure that when limits are set they use CONFIG_64BIT for U-Boot
proper and CONFIG_SPL_64BIT for SPL. This is to allow for the 32 bit
SPL build used by x86.

Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2024-12-31 10:58:30 -06:00
Kongyang Liu
1cd239f444 riscv: spacemit: bananapi_f3: initial support added
Add basic support for SpacemiT's Banana Pi F3 board.
Update the k1.dtsi align with mainline.
Note that the device tree files follow the mainline Linux source[1].

Links: https://patches.linaro.org/project/linux-serial/patch/20240730-k1-01-basic-dt-v5-8-98263aae83be@gentoo.org/ [1]

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Signed-off-by: Huan Zhou <pericycle.cc@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Marcel Ziswiler <marcel@ziswiler.com>
2024-12-18 13:19:16 +08:00
Maksim Kiselev
dced3ec324 riscv: dts: t-head: Add sdhci and emmc nodes
Add SDHCI and EMMC controlles nodes on TH-1520 SoC. And enable them for
Lichee module 4A.

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
2024-12-18 13:19:16 +08:00
Hal Feng
2c1cb8837b riscv: cpu: jh7110: Sort the list of imply statements
The imply statements should be sorted in the sequence
of appearance in .config.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:16 +08:00
Hal Feng
c9489a9d32 riscv: dts: jh7110: Support multiple DTBs in a Fit image
Support multiple DTBs for JH7110 based boards, so they can
select the correct DT at runtime.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:15 +08:00
Hal Feng
1b52a220d3 riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards
To support the other JH7110 based boards, add u-boot
device tree for them.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: H Bell <dmoo_dv@protonmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:15 +08:00
Hal Feng
6bbe95ef72 riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi
To support JH7110 based boards besides v1.3B,
add a common dtsi and add common code to it.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:15 +08:00
Hal Feng
503fc85481 riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT
Add u-boot features to the U-Boot device tree.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Reviewed-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:15 +08:00
Hal Feng
84d3911a01 dts: starfive: Switch to using upstream DT
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to
the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi
to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b
device tree as the default device tree.

Drop redundant DT files from arch/riscv/dts/ and redundant clock and
reset definitions from include/dt-bindings/.

Since the old clock definitions is a little different from those in
upstream Linux, update the clock definitions in clock drivers
accordingly.

Tested-by: Anand Moon <linux.amoon@gmail.com>
Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2024-12-18 13:19:15 +08:00
Thomas Bonnefille
04bcc87f0d board: add support for LicheeRV Nano
The LicheeRV Nano is a small SBC using the Sophgo SG2002 RISCV SoC.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
2024-12-18 13:19:15 +08:00
Thomas Bonnefille
4897de90c3 riscv: dts: sophgo: add device tree for LicheeRV Nano
Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
2024-12-18 13:19:15 +08:00
Janne Grunau
dabaa4ae32 dm: Add dm_remove_devices_active() for ordered device removal
This replaces dm_remove_devices_flags() calls in all boot
implementations to ensure non vital devices are consistently removed
first. All boot implementation except arch/arm/lib/bootm.c currently
just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result
in crashes when dependencies between devices exists. The driver model's
design document describes DM_FLAG_VITAL as "indicates that the device is
'vital' to the operation of other devices". Device removal at boot
should follow this.

Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL |
DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which
does this.

Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI
boot. The xhci-pci (driver which depends on the IOMMU to work) removes
its mapping on removal. This explodes when the IOMMU device was removed
first.

dm_remove_devices_flags() is kept since it is used for testing of
device_remove() calls in dm.

Signed-off-by: Janne Grunau <j@jannau.net>
2024-11-24 15:41:28 -06:00
Michal Simek
d5f5e77818 riscv: Introduce configuration for 64bit version Microblaze V
The commit 7576ab2fac ("riscv: Add support for AMD/Xilinx MicroBlaze V")
added support for 32bit version. 64bit version is also available that's why
wire it up too.
DT is providing description for generic QEMU target.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-11-06 19:42:54 +08:00
Conor Dooley
239e470509 riscv: dts: mpfs: migrate to OF_UPSTREAM
The U-Boot copy of the mpfs devicetree has, in general, been neglected
somewhat in comparison to the one in Linux. Moving to OF_UPSTREAM to
keep both in sync should serve to eliminate that discrepancy.

Additionally, moving to OF_UPSTREAM will let U-Boot automatically pick
up the devicetree rework that is in progress at [1].

Link: https://lore.kernel.org/all/20241002-private-unequal-33cfa6101338@spud/ [1]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2024-10-29 19:58:22 +08:00
Anton Blanchard
8e1acda14e riscv: resume needs to be a global
If we take an exception before u-boot is relocated, there's a good
chance we will end up in an endless loop of exceptions because resume is
invalid until after relocation.

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2024-10-29 19:58:14 +08:00