Since pinmux driver now is available for Tegra 2, these parts may
be removed from here and defined either in device tree or in
the device board files.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Some customers prefer to minimize the use of external oscillators,
especially when using the FPGA first configuration mode.
By enabling the configuration of the HPS internal oscillator as
the boot_clk source instead of the default external oscillator,
(HPS_OSC_CLK) in non-secure boot scenarios, this allows them
to eliminate the need for an additional oscillator device and
a dedicated HPS pin, simplifying board layout and routing.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
For eMMC v4 and newer that is smaller than 2 GiB, the JEDEC JESD84-B51
section 6.2.4 Configure partitions indicates that EXT_CSD SEC_COUNT
should not be used to determine device size, and instead device size
should be calculated from C_SIZE and C_SIZE_MULT.
This is not exactly accurate, the 2 GiB limit is not a hard line,
there are eMMC devices which are smaller than 2 GiB and still
require device size to be determined from EXT_CSD SEC_COUNT. The
hard line is instead OCR HCS bit, which indicates whether the device
is byte or sector addressed, the former applies to most devices
below 2 GiB, and the later applies mostly to devices above 2 GiB.
However, there are a couple of devices which are smaller than 2 GiB
and still set the OCR HCS bit to indicate they are sector addressed,
and therefore the size calculation for those devices should also
use EXT_CSD SEC_COUNT . Use mmc->high_capacity flag to discern the
devices instead of arbitrary 2 GiB limit. The mmc->high_capacity flag
reflects the OCR HCS bit state.
Fixes: 639b7827d1 ("mmc: fix the condition for MMC version 4")
Signed-off-by: Marek Vasut <marex@denx.de>
Memory region used by remote cores was set to non-cached region but
commit 7c9c6e1925 ("arm: mach-k3: Merge initial memory maps") makes
all memory region as cached, unified across K3 devices.
This causes inconsistency while booting remote cores on devices, due to
cache incoherency between remote core and boot code.
So to make this operation coherent, cache the address and len while
loading ELF program headers to memory and flush that region in the next
cycle of load.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Defining CONFIG_MT8512 is unnecessary as now board for mediatek
target can be changed in config.
Use CONFIG_TARGET_MT8512 to replace CONFIG_MT8512.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
When rgmii-rxid/txid/id phy-mode is used the MAC should not add RX
and/or TX delay. Currently RX/TX delay is configured as enabled using
zero as delay value for the rgmii-rxid/txid/id modes.
Change to disable RX and/or TX delay and using zero as delay value.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
recalculated so it remain unchanged. Add missing GPIO3-B1 to GPIO3-B7
pinmux data to rk3328_mux_recalced_data as mux register offset for these
pins does not follow rockchip convention.
This matches changes in following Linux commits:
- e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
- 5ef6914e0bf5 ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins")
- 128f71fe014f ("pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The PCS exists only in GMAC1 and relates to SGMII interface and
is used to control the SGMII PHY.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
[trini: Adjust slightly for white space and to move 'start' to within if
block]
As per TRM[0] Section 8.7.1 "TPS6594-Q1 Registers", LDOx_Vout
bit 6-1, define the NVM voltage settings.
Along side table 8-4 of above TRM, shows voltage to value mapping.
Driver wrongly using bits 5-1 to calculate voltage, and to convert
voltage to value driver was using buck's calculation.
So fix those calculation.
[0]: https://www.ti.com/lit/ds/symlink/tps6594-q1.pdf
Fixes: 5d7dbd22cf ("power: regulator: tps65941: use function callbacks for conversion ops")
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
The struct contains an iomem pointer that we later remap and update.
Remove const from the struct definition.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
First set of u-boot-at91 features for the 2025.07 cycle:
This feature set includes improvements on the atmel-quadspi driver, a
fix for the nand driver, and improvements on the pinctrl driver to be
able to use the Linux DT (also sync on the DT side as well).
When 3-wire mode is claimed on the bus, use the MOSI (output) pin to
receive data. In this mode, since the transfer can only be either TX
or RX, return -EINVAL if both are required at the same time.
Signed-off-by: Hironori KIKUCHI <kikuchan98@gmail.com>
Judith Mendez <jm@ti.com> says:
Some K3 devices like am62x and am64x have a M4 processor in the MCU
voltage domain. This patch series introduces remoteproc M4 driver which
will be used to load firmware into and start the M4 remote core.
This series also adds support for R5F cores on am64x SoCs in patch 2 and
sets up environment to load FW in remote cores in patch 3,4,5.
This patch series also enables remoteproc drivers by default as per what
remoteproc sybsystem is supported per SoC, thus all remoteproc options
are now deleted in configs/* since they are no longer required.
This patch series was tested on am64x EVM, am62x SK, am62ax SK,
am62px SK boards.
Any additional tested by's are welcome since I was not able to
test any additional boards.
Tested by running the following commands in u-boot prompt:
=> setenv dorprocboot 1
=> run boot_rprocs
Link: https://lore.kernel.org/r/20250210202944.1071931-1-jm@ti.com
If SYS_K3_SPL_ATF is enabled, for K3 ARCH enable the
remoteproc ARM64 driver by default so that it does not
have to be defined in each board defconfig file.
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
AM64x SoCs have two R5F clusters in the main power domain.
Extend support for R5F remote proc driver on AM64x with compatible
strings.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Signed-off-by: Judith Mendez <jm@ti.com>
Reviewed-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Andrew Davis <afd@ti.com>
Some K3 devices like AM64, AM62 devices have a M4 processor in MCU
voltage domain.
Add a remote proc driver to support this subsystem to be able to load
and boot the M4 core.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
[Ryan: Fix implicitly include warning]
Signed-off-by: Ryan Eatmon <reatmon@ti.com>
[Judith: Cleanup driver, fix warnings, remove lreset logic]
Signed-off-by: Judith Mendez <jm@ti.com>
Tested-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Andrew Davis <afd@ti.com>
Add CONFIG_BOOTCOUNT_ALTBOOTCMD so the developer is able to add
custom altbootcmd via Kconfig when they enable BOOTCOUNT. With this now
in Kconfig, we need to move it from environment files / config.h files
and in to the defconfig file.
This was done by generating u-boot-initial-env for all platforms before
the Kconfig change, to extract altbootcmd values and then again after to
compare the result.
[trini: Perform migration to defconfigs, reword commit message]
Signed-off-by: Tom Rini <trini@konsulko.com>
From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse time must be at least tREA.
Without this fix we got PMECC errors when reading, after switching to
ONFI timing mode 3 on SAM9X60 SoC with S34ML02G1 raw NAND flash chip.
The approach to set timings used before worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.
The approach to fix the issue was carried over from at91bootstrap, and
has been successfully tested in at91bootstrap, U-Boot and Linux.
Link: https://github.com/linux4sam/at91bootstrap/issues/174
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Pin detection on t20 depends on node name. With recent changes
in node naming, let's remove '_' to be safe about both '_' or
'-' use.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Bind SYSRESET child to parent node since it does not have
its own node in the device tree.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Bind GPIO and SYSRESET children to parent node since they
do not have their own nodes in the device tree.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Requesting of PMIC's GPIO child should be done by binding
GPIO driver to PMIC's node is GPIO driver does not have
its own node.
This reverts commit c03cd98d1a.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
U-Boot pinctrl driver expects a reg property explicitly unlike linux.
To align the DT of U-boot with the Linux, reg property is also arrvied
from child GPIO bank nodes when configured under the pinctrl node.
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
In Linux DT,the pinctrl node acts as parent nodes with all other
gpio banks as child nodes and a single driver in Linux handles both
pinctrl settings and gpio requests.Current U-Boot DT maintains both
pinctrl and gpio nodes as separate nodes and offers two different class
of U-Boot drivers: UCLASS_PINCTRL which handles pin functions and
UCLASS_GPIO which handles gpio requests. In order to align the DT
of U-Boot with the DT of Linux, a hook is been added in the pinctrl
driver to bind the gpio driver with the pinctrl driver so that
when adding gpio nodes as subnodes to pinctrl node (as per the Linux ABI),
the corresponding APIs will be redirected and handled by valid
drivers attached to the pinctrl driver.
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
The qspi controller on sama5d2 and sam9x60 supports "classic" SPI mode
without spi-mem enhancements and accelerations, very similar to the old
SPI controller on sam9g20 or the modern flexcom controllers of the same
SoC family.
Register interface differs somewhat, especially because only one
hardware controlled CS line is supported. Some fields are missing, some
are in different registers, but in principal it works similar. So code
is very much inspired by the old atmel-spi driver.
Tested on sam9x60 with a non-mainline driver to configure an FPGA.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Switching between Serial Memory Mode (SMM) and (classic) SPI mode is a
preparation for implementing .xfer() in the future.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
The Serial Memory Mode (SMM) is enabled with atmel_qspi_set_cfg() on
each invocation of atmel_qspi_exec_op(). Setting SMM through
atmel_qspi_init() at probe time is redundant.
Removing the SMM setting at probe time should therefore 1) be safe to do
and 2) allows for setting it to a different value in a future
implementation of .xfer() which needs to disable SMM.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Port these commits:
- v6.11-rc5-90-g329ca3eed4a9a ("spi: atmel-quadspi: Avoid overwriting delay register settings")
- v6.12-rc1-1-g162d9b5d2308c ("spi: atmel-quadspi: Fix wrong register value written to MR").
- v6.13-rc2-27-gf663898d047a7 ("spi: atmel-quadspi: Factor out switching to Serial Memory Mode to function")
Cc: Csókás Bence <csokas.bence@prolan.hu>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Port changes from a 4 piece patch series from Linux kernel v5.10, merged
with v5.10-rc1-83-gc732b7567d869 ("Merge series "spi: atmel-quadspi: Fix
AHB memory accesses" from Tudor Ambarus …").
Port the single fix v5.15-rc1-14-g09134c5322df9 ("spi: Fixed division by
zero warning").
Reduces differences between linux and u-boot driver.
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: Yoshitaka Ikeda <ikeda@nskint.co.jp>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Most other spi-mem drivers also depend on SPI_MEM. Fixes this build
error:
arm-v5te-linux-gnueabi-ld.bfd: drivers/spi/atmel-quadspi.o: in function `atmel_qspi_supports_op':
/mnt/data/adahl/src/u-boot/drivers/spi/atmel-quadspi.c:460: undefined reference to `spi_mem_default_supports_op'
make[1]: *** [/mnt/data/adahl/src/u-boot/Makefile:1821: u-boot] Error 1
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is inside of an 'if DM_SPI' block, and thus always true.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Show the time taken by each test suite with 'ut all' and the total time
for all suites.
Take care to remove any sandbox time-offset from the values.
Fix the comment-format on timer_test_add_offset() while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
u-boot-dfu-20250211:
CI:
- https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/24556
Android:
- Handle boot images with missing DTB
Usb gadget:
- Fix nullptr in g_dnl when serial# is unset
- Add missing schedule() in f_mass_storage gadget
- Add support for STih407 in dwc3-generic
- Fix usb clocks on STih407
- Migrate STih407 to DM_USB_GADGET
