* Patches by Xianghua Xiao, 15 Oct 2003:

- Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup
* Make sure HUSH is initialized for running auto-update scripts
2026-06-09 05:06:42 +03:00 · 2003-10-15 23:53:47 +00:00 · 2003-10-14 19:43:55 +00:00 · 2003-10-10 10:05:42 +00:00 · 2003-10-09 20:09:04 +00:00 · 2003-10-09 19:00:25 +00:00
287 changed files with 29521 additions and 5043 deletions
--- a/134
+++ b/134
@@ -2,6 +2,138 @@
 Changes for U-Boot 1.0.0:
 ======================================================================

+* Patches by Xianghua Xiao, 15 Oct 2003:
+
+  - Added Motorola CPU 8540/8560 support (cpu/85xx)
+  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
+  - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+
+* Fix flash timings on TRAB board
+
+* Make sure HUSH is initialized for running auto-update scripts
+
+* Make 5200 reset command _really_ reset the board, without running
+  any other code after it
+
+* Fix errors with flash erase when range spans  across banks
+  that are mapped in reverse order
+
+* Fix flash mapping and display on P3G4 board
+
+* Patch by Kyle Harris, 15 Jul 2003:
+  - add support for Intel IXP425 CPU
+  - add support for IXDP425 eval board
+
+* Added config option CONFIG_SILENT_CONSOLE.  See doc/README.silent
+  for more information
+
+* Patch by Steven Scholz, 10 Oct 2003
+  - Add support for Altera FPGA ACEX1K
+
+* Patches by Thomas Lange, 09 Oct 2003:
+  - fix cmd_ide.c for non ppc boards (read/write functions did not
+    add ATA base address)
+  - fix for shannon board
+  - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code
+  - Endian swap ATA identity for all big endian CPUs, not just PPC
+  - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
+    args to linux
+  - add support for dbau1x00 board (MIPS32)
+
+* Patch by Sangmoon Kim, 07 Oct 2003:
+  add support for debris board
+
+* Patch by Martin Krause, 09 Oct 2003:
+  Fixes for TRAB board
+  - /board/trab/rs485.c: correct baudrate
+  - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
+    udelay(); fix some timing problems with adc controller
+  - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
+    modify commands: touch and buzzer
+
+* Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE
+  (quick & dirty workaround for rogue pointer problem in get_vfatname());
+  Use direct function calls for auto_update instead of hush commands
+
+* Patch by Scott McNutt, 04 Oct 2003:
+  - add support for Altera Nios-32 CPU
+  - add support for Nios Cyclone Development Kit (DK-1C20)
+
+* Patch by Steven Scholz, 29 Sep 2003:
+  - A second parameter for bootm overwrites the load address for
+    "Standalone Application" images.
+  - bootm sets environment variable "filesize" to the resulting
+    (uncompressed) data length for "Standalone Application" images
+    when autostart is set to "no". Now you can do something like
+	if bootm $fpgadata $some_free_ram ; then
+		fpga load 0 $some_free_ram $filesize
+	fi
+
+* Patch by Denis Peter, 25 Sept 2003:
+  add support for the MIP405 Rev. C board
+
+* Patch by Yuli Barcohen, 25 Sep 2003:
+  add support for Zephyr Engineering ZPC.1900 board
+
+* Patch by Anders Larsen, 23 Sep 2003:
+  add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only
+  implemented for the x86 architecture)
+
+* Patch by Sangmoon Kim, 23 Sep 2003:
+  fix pll_pci_to_mem_multiplier table for MPC8245
+
+* Patch by Anders Larsen, 22 Sep 2003:
+  enable timed autoboot on PXA
+
+* Patch by David Müller, 22 Sep 2003:
+  - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver
+    returns correct libgcc file path
+  - "latency" reduction of busy-loop waiting to improve "U-Boot" boot
+    time on s3c24x0 systems
+
+* Patch by Jon Diekema, 19 Sep 2003:
+  - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet
+    link state to the fault LED.
+  - In NetLoop, make the Fault LED reflect the link status.  The link
+    status gets updated on entry, and on timeouts.
+
+* Patch by Anders Larsen, 18 Sep 2003:
+  allow mkimage to build and run on Cygwin-hosted systems
+
+* Patch by Frank Müller, 18 Sep 2003:
+  use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in
+  cpu/mpc8xx/fec.c
+
+* Patch by Pantelis Antoniou, 16 Sep 2003:
+  add tool to compute fileds in the PLPRCR register for MPC86x
+
+* Use IH_TYPE_FILESYSTEM for TRAB "disk" images.
+
+* Fix build problems under FreeBSD
+
+* Add generic filesystem image type
+
+* Make fatload set filesize environment variable
+
+* enable basic / medium / high-end configurations for PPChameleonEVB
+  board; fix NAND code
+
+* enable TFTP client code to specify to the server the desired
+  timeout value (see RFC-2349)
+
+* Improve SDRAM setup for TRAB board
+
+* Suppress all output with splashscreen configured only if "splashimage"
+  is set
+
+* Fix problems with I2C support for mpc5200
+
+* Adapt TRAB configuration and auto_update to new memory layout
+
+* Add configuration for wtk board
+
+* Add support for the Sharp LQ065T9DR51U LCD display
+
 * Patch by Rune Torgersen, 17 Sep 2003:
  - Fixes for MPC8266 default config
  - Allow eth_loopback_test() on 8260 to use a subset of the FCC's
@@ -85,6 +217,8 @@ Changes for U-Boot 1.0.0:
 Changes for U-Boot 0.4.8:
 ======================================================================

+* Add I2C and RTC support for RMU board
+
 * Patches by Denis Peter, 9 Sep 2003:
  add FAT support for IDE, SCSI and USB

--- a/39
+++ b/39
@@ -18,14 +18,14 @@ N: Dr. Bruno Achauer
 E: bruno@exet-ag.de
 D: Support for NetBSD (both as host and target system)

-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
 N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration

+N: Swen Anderson
+E: sand@peppercon.de
+D: ERIC Support
+
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA board support, ARTOS support.
@@ -75,7 +75,7 @@ E: clark@esteem.com
 D: ESTEEM192E support

 N: Magnus Damm
-E: eramdam@kieray1.p.y.ki.era.ericsson.se
+E: damm@opensource.se
 D: 8xxrom

 N: Arun Dharankar
@@ -182,13 +182,22 @@ N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board

+N: Sangmoon Kim
+E: dogoil@etinsys.com
+D: Support for debris board
+
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)

+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+
 N: Thomas Lange
-E: thomas@corelatus.com
-D: Support for GTH board; lots of PCMCIA fixes
+E: thomas@corelatus.se
+D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes

 N: The LEOX team
 E: team@leox.org
@@ -219,6 +228,10 @@ N: David M
 E: d.mueller@elsoft.ch
 D: Support for Samsung ARM920T SMDK2410 eval board

+N: Scott McNutt
+E: smcnutt@psyent.com
+D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20)
+
 N: Rolf Offermanns
 E: rof@sysgo.de
 D: Initial support for SSV-DNP1110, SMC91111 driver
@@ -299,12 +312,6 @@ E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com

-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
-
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
--- a/38
+++ b/38
@@ -25,6 +25,10 @@ Pantelis Antoniou <panto@intracom.gr>

 	NETVIA			MPC8xx

+Yuli Barcohen <yuli@arabellasw.com>
+
+	ZPC1900			MPC8265
+
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>

 	sacsng			MPC8260
@@ -108,10 +112,6 @@ Dave Ellis <DGE@sixnetio.com>

 	SXNI855T		MPC8xx

-Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
-
-	ADDERII			MPC852T
-
 Thomas Frieden <ThomasF@hyperion-entertainment.com>

 	AmigaOneG3SE		MPC7xx
@@ -150,11 +150,19 @@ Brad Kemp <Brad.Kemp@seranoa.com>

 	ppmc8260		MPC8260

+Sangmoon Kim <dogoil@etinsys.com>
+
+	debris			MPC8245
+
+Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
+
+	ADDERII			MPC852T
+
 Nye Liu <nyet@zumanetworks.com>

 	ZUMA			MPC7xx_74xx

-Thomas Lange <thomas@corelatus.com>
+Thomas Lange <thomas@corelatus.se>

 	GTH			MPC860

@@ -232,6 +240,11 @@ John Zhan <zhanz@sinovee.com>

 	svm_sc8xx		MPC8xx

+Xianghua Xiao <x.xiao@motorola.com>
+
+	MPC8540ADS		MPC8540
+	MPC8560ADS		MPC8560
+
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
@@ -281,6 +294,7 @@ Kyle Harris <kharris@nexus-tech.net>

 	lubbock			xscale
 	cradle			xscale
+	ixdp425			xscale

 Gary Jennejohn <gj@denx.de>

@@ -333,6 +347,20 @@ Wolfgang Denk <wd@denx.de>
 	incaip			MIPS32 4Kc
 	purple			MIPS64 5Kc

+Thomas Lange <thomas@corelatus.se>
+	dbau1x00		MIPS32 Au1000
+
+#########################################################################
+# Nios-32 Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Scott McNutt <smcnutt@psyent.com>
+
+	DK1C20			Nios-32
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/31
+++ b/31
@@ -69,8 +69,9 @@ LIST_4xx="	\

 LIST_824x="	\
 	A3000           BMW		CPC45		CU824		\
-	MOUSSE          MUSENKI    	OXC		PN62		\
-	Sandpoint8240   Sandpoint8245	SL8245		utx8245		\
+	debris		MOUSSE          MUSENKI    	OXC		\
+	PN62		Sandpoint8240   Sandpoint8245	SL8245		\
+	utx8245								\
 "

 #########################################################################
@@ -82,7 +83,15 @@ LIST_8260="	\
 	gw8260		hymod		IPHASE4539	MPC8260ADS	\
 	MPC8266ADS	PM826		ppmc8260	RPXsuper	\
 	rsdproto	sacsng		sbc8260		SCM		\
-	TQM8260_AC	TQM8260_AD	TQM8260_AE			\
+	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
+"
+
+#########################################################################
+## MPC85xx Systems (includes 8540, 8560 etc.)
+#########################################################################
+
+LIST_85xx="	\
+	MPC8540ADS	MPC8560ADS					\
 "

 #########################################################################
@@ -101,6 +110,7 @@ LIST_7xx="	\
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx} \
 	  ${LIST_8xx}  \
 	  ${LIST_824x} ${LIST_8260} \
+	  ${LIST_85xx}	\
 	  ${LIST_4xx}		    \
 	  ${LIST_74xx} ${LIST_7xx}"

@@ -132,18 +142,22 @@ LIST_ARM9="	\

 LIST_pxa="cradle csb226 innokom lubbock wepep250"

+LIST_ixp="ixdp425"

-LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa}"
+
+LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"

 #########################################################################
-## MIPS 4Kc Systems
+## MIPS Systems
 #########################################################################

 LIST_mips4kc="incaip"

 LIST_mips5kc="purple"

-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc}"
+LIST_au1x00="dbau1x00"
+
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"

 #########################################################################
 ## i386 Systems
@@ -175,7 +189,10 @@ build_target() {
 for arg in $@
 do
 	case "$arg" in
-	5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx|SA|ARM7|ARM9|ppc|arm|pxa|mips|I486|x86)
+	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
+	arm|SA|ARM7|ARM9|pxa|ixp| \
+	mips| \
+	x86|I486)
 			for target in `eval echo '$LIST_'${arg}`
 			do
 				build_target ${target}
--- a/88
+++ b/88
@@ -69,6 +69,9 @@ endif
 ifeq ($(ARCH),mips)
 CROSS_COMPILE = mips_4KC-
 endif
+ifeq ($(ARCH),nios)
+CROSS_COMPILE = nios-elf-
+endif
 endif
 endif

@@ -103,6 +106,9 @@ endif
 ifeq ($(CPU),ppc4xx)
 OBJS +=	cpu/$(CPU)/resetvec.o
 endif
+ifeq ($(CPU),mpc85xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif

 LIBS  =	board/$(BOARDDIR)/lib$(BOARD).a
 LIBS += cpu/$(CPU)/lib$(CPU).a
@@ -118,7 +124,7 @@ LIBS += post/libpost.a post/cpu/libcpu.a
 LIBS += common/libcommon.a
 LIBS += lib_generic/libgeneric.a
 # Add GCC lib
-PLATFORM_LIBS += -L $(shell dirname `$(CC) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc

 #########################################################################
 #########################################################################
@@ -470,9 +476,15 @@ v37_config:	unconfig
 	@echo "#define CONFIG_SHARP_LQ084V1DG21" >>include/config.h
 	@./mkconfig $(@:_config=) ppc mpc8xx v37

+wtk_config:	unconfig
+	@echo "#define CONFIG_LCD" >include/config.h
+	@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>include/config.h
+	@./mkconfig -a TQM823L ppc mpc8xx tqm8xx
+
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
+xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))

 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@@ -552,8 +564,24 @@ PLU405_config:	unconfig
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd

+PPChameleonEVB_MODEL_BA_config	\
+PPChameleonEVB_MODEL_ME_config	\
+PPChameleonEVB_MODEL_HI_config	\
 PPChameleonEVB_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx PPChameleonEVB dave
+	@ >include/config.h
+	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
+		  echo "... BASIC model" ; \
+		}
+	@[ -z "$(findstring _MODEL_ME,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >>include/config.h ; \
+		  echo "... MEDIUM model" ; \
+		}
+	@[ -z "$(findstring _MODEL_HI,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
+		  echo "... HIGH-END model" ; \
+		}
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave

 VOH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
@@ -620,6 +648,9 @@ utx8245_config: unconfig
 ## MPC8260 Systems
 #########################################################################

+atc_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 atc
+
 cogent_mpc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 cogent

@@ -743,8 +774,18 @@ TQM8265_AA_config:  unconfig
 	fi
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260

-atc_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8260 atc
+ZPC1900_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
+
+#########################################################################
+## MPC85xx Systems
+#########################################################################
+
+MPC8540ADS_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
+
+MPC8560ADS_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads

 #########################################################################
 ## 74xx/7xx Systems
@@ -753,24 +794,27 @@ atc_config:	unconfig
 AmigaOneG3SE_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI

+BAB7xx_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
+
+debris_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x debris etin
+
+ELPPC_config: unconfig
+	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
+
 EVB64260_config	\
 EVB64260_750CX_config:	unconfig
 	@./mkconfig EVB64260 ppc 74xx_7xx evb64260

-ZUMA_config:	unconfig
+P3G4_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260

 PCIPPC2_config \
 PCIPPC6_config: unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx pcippc2

-BAB7xx_config: unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx bab7xx eltec
-
-ELPPC_config: unconfig
-	@./mkconfig $(@:_config=) ppc 74xx_7xx elppc eltec
-
-P3G4_config: unconfig
+ZUMA_config:	unconfig
 	@./mkconfig $(@:_config=) ppc 74xx_7xx evb64260

 #========================================================================
@@ -857,6 +901,9 @@ csb226_config	:	unconfig
 innokom_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa innokom

+ixdp425_config	:	unconfig
+	@./mkconfig $(@:_config=) arm ixp ixdp425
+
 lubbock_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa lubbock

@@ -916,6 +963,23 @@ incaip_config: unconfig
 purple_config :		unconfig
 	@./mkconfig $(@:_config=) mips mips purple

+#========================================================================
+# Nios
+#========================================================================
+#########################################################################
+## Nios32
+#########################################################################
+
+DK1C20_config:	unconfig
+	@./mkconfig $(@:_config=) nios nios dk1c20
+
+
+#########################################################################
+## MIPS32 AU1000
+#########################################################################
+dbau1x00_config		: 	unconfig
+	@./mkconfig $(@:_config=) mips mips dbau1x00
+
 #########################################################################
 #########################################################################

--- a/58
+++ b/58
@@ -146,6 +146,7 @@ Directory Hierarchy:
 - cpu/mpc8xx	Files specific to Motorola MPC8xx  CPUs
 - cpu/mpc824x	Files specific to Motorola MPC824x CPUs
 - cpu/mpc8260	Files specific to Motorola MPC8260 CPU
+- cpu/mpc85xx	Files specific to Motorola MPC85xx CPUs
 - cpu/ppc4xx	Files specific to IBM	   4xx	   CPUs


@@ -199,6 +200,10 @@ Directory Hierarchy:
 - board/mbx8xx	Files specific to MBX	     boards
 - board/mpc8260ads
 		Files specific to MPC8260ADS and PQ2FADS-ZU boards
+- board/mpc8540ads
+		Files specific to MPC8540ADS boards
+- board/mpc8560ads
+		Files specific to MPC8560ADS boards
 - board/mpl/	Files specific to boards manufactured by MPL
 - board/mpl/common	Common files for MPL boards
 - board/mpl/pip405	Files specific to PIP405     boards
@@ -210,7 +215,7 @@ Directory Hierarchy:
 - board/oxc	Files specific to OXC        boards
 - board/omap1510inn
 		Files specific to OMAP 1510 Innovator boards
- board/omap1610inn  
+- board/omap1610inn
 		Files specific to OMAP 1610 Innovator boards
 - board/pcippc2	Files specific to PCIPPC2/PCIPPC6 boards
 - board/pm826	Files specific to PM826      boards
@@ -239,6 +244,7 @@ Directory Hierarchy:
 - board/westel/	Files specific to boards manufactured by Westel Wireless
 - board/westel/amx860	Files specific to AMX860     boards
 - board/utx8245	Files specific to UTX8245   boards
+- board/zpc1900	Files specific to Zephyr Engineering ZPC.1900 board

 Software Configuration:
 =======================
@@ -305,6 +311,7 @@ The following options need to be configured:
 		CONFIG_MPC823,	CONFIG_MPC850,	CONFIG_MPC855,	CONFIG_MPC860
 	or	CONFIG_MPC5xx
 	or	CONFIG_MPC824X, CONFIG_MPC8260
+	or	CONFIG_MPC85xx
 	or	CONFIG_IOP480
 	or	CONFIG_405GP
 	or	CONFIG_405EP
@@ -355,7 +362,8 @@ The following options need to be configured:
 		CONFIG_IAD210,     CONFIG_RPXlite,    CONFIG_sbc8260,
 		CONFIG_EBONY,      CONFIG_sacsng,     CONFIG_FPS860L,
 		CONFIG_V37,        CONFIG_ELPT860,    CONFIG_CMI,
-		CONFIG_NETVIA,     CONFIG_RBC823
+		CONFIG_NETVIA,     CONFIG_RBC823,     CONFIG_ZPC1900,
+		CONFIG_MPC8540ADS, CONFIG_MPC8560ADS

 		ARM based boards:
 		-----------------
@@ -393,19 +401,20 @@ The following options need to be configured:
 		Possible values are:
 			CFG_8260ADS	- original MPC8260ADS
 			CFG_8266ADS	- MPC8266ADS (untested)
-			CFG_PQ2FADS	- PQ2FADS-ZU
+			CFG_PQ2FADS	- PQ2FADS-ZU or PQ2FADS-VR


 - MPC824X Family Member (if CONFIG_MPC824X is defined)
-	Define exactly one of
-	CONFIG_MPC8240, CONFIG_MPC8245
+		Define exactly one of
+		CONFIG_MPC8240, CONFIG_MPC8245

 - 8xx CPU Options: (if using an 8xx cpu)
 		Define one or more of
-		CONFIG_8xx_GCLK_FREQ	- if get_gclk_freq() can not work e.g.
-					  no 32KHz reference PIT/RTC clock
+		CONFIG_8xx_GCLK_FREQ	- if get_gclk_freq() cannot work
+					  e.g. if there is no 32KHz
+					  reference PIT/RTC clock

- Clock Interface:
+- Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ

 		U-Boot stores all clock information in Hz
@@ -415,11 +424,16 @@ The following options need to be configured:
 		"clocks_in_mhz" can be defined so that U-Boot
 		converts clock data to MHZ before passing it to the
 		Linux kernel.
-
 		When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
 		"clocks_in_mhz=1" is  automatically  included  in  the
 		default environment.

+		CONFIG_MEMSIZE_IN_BYTES		[relevant for MIPS only]
+
+		When transfering memsize parameter to linux, some versions
+		expect it to be in bytes, others in MB.
+		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.
+
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
@@ -584,7 +598,7 @@ The following options need to be configured:
 		CFG_CMD_DHCP	  DHCP support
 		CFG_CMD_DIAG    * Diagnostics
 		CFG_CMD_DOC     * Disk-On-Chip Support
-		CFG_CMD_DTT       Digital Therm and Thermostat 
+		CFG_CMD_DTT       Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
 		CFG_CMD_ELF	  bootelf, bootvx
@@ -886,9 +900,9 @@ The following options need to be configured:
 		images is included. If not, only uncompressed and gzip
 		compressed images are supported.

-                NOTE: the bzip2 algorithm requires a lot of RAM, so
-                the malloc area (as defined by CFG_MALLOC_LEN) should
-                be at least 4MB.
+		NOTE: the bzip2 algorithm requires a lot of RAM, so
+		the malloc area (as defined by CFG_MALLOC_LEN) should
+		be at least 4MB.

 - Ethernet address:
 		CONFIG_ETHADDR
@@ -1749,6 +1763,14 @@ Note: once the monitor has been relocated, then it will complain if
 the default environment is used; a new CRC is computed as soon as you
 use the "saveenv" command to store a valid environment.

+- CFG_FAULT_ECHO_LINK_DOWN:
+		Echo the inverted Ethernet link state to the fault LED.
+
+		Note: If this option is active, then CFG_FAULT_MII_ADDR
+		      also needs to be defined.
+
+- CFG_FAULT_MII_ADDR:
+		MII address of the PHY to check for the Ethernet link state.

 Low Level (hardware related) configuration options:
 ---------------------------------------------------
@@ -1759,9 +1781,9 @@ Low Level (hardware related) configuration options:
 - CFG_DEFAULT_IMMR:
 		Default address of the IMMR after system reset.

-                Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
-                and RPXsuper) to be able to adjust the position of
-                the IMMR register after a reset.
+		Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
+		and RPXsuper) to be able to adjust the position of
+		the IMMR register after a reset.

 - Floppy Disk Support:
 		CFG_FDC_DRIVE_NUMBER
@@ -1935,7 +1957,9 @@ configurations; the following names are supported:
    GEN860T_config	  EBONY_config		FPS860L_config
    ELPT860_config	  cmi_mpc5xx_config	NETVIA_config
    at91rm9200dk_config	  omap1510inn_config	MPC8260ADS_config
-    omap1610inn_config
+    omap1610inn_config	  ZPC1900_config	MPC8540ADS_config
+    MPC8560ADS_config
+
 Note: for some board special configuration names may exist; check  if
      additional  information is available from the board vendor; for
      instance, the TQM8xxL systems run normally at 50 MHz and use  a
--- a/board/adderII/adderII.h
+++ b/board/adderII/adderII.h
@@ -41,5 +41,3 @@
 * | 			   |
 * | ...                   |
 *****************************************************************************/
-
-
--- a/board/adderII/config.mk
+++ b/board/adderII/config.mk
@@ -26,4 +26,3 @@
 #

 TEXT_BASE = 0xFE000000
-
--- a/board/adderII/u-boot.lds
+++ b/board/adderII/u-boot.lds
@@ -144,4 +144,3 @@ SECTIONS
  _end = . ;
  PROVIDE (end = .);
 }
-
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -51,7 +51,7 @@ int gunzip(void *, int, unsigned char *, int *);
 int board_pre_init (void)
 {
 	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
-        out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */
+	out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */

 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -261,10 +261,13 @@ nand_probe(ulong physadr);
 void
 nand_init(void)
 {
-	ulong totlen;
+	ulong totlen = 0;

+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
+    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
-	totlen = nand_probe (CFG_NAND0_BASE);
+	totlen += nand_probe (CFG_NAND0_BASE);
+#endif	/* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */

 	debug ("Probing at 0x%.8x\n", CFG_NAND1_BASE);
 	totlen += nand_probe (CFG_NAND1_BASE);
--- a/board/dave/PPChameleonEVB/flash.c
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -46,8 +46,8 @@ unsigned long flash_init (void)
 #else
 	unsigned long size_b0;
 	int i;
-        uint pbcr;
-        unsigned long base_b0;
+	uint pbcr;
+	unsigned long base_b0;
 	int size_val = 0;

 	/* Init: no FLASHes known */
@@ -64,14 +64,14 @@ unsigned long flash_init (void)
 			size_b0, size_b0<<20);
 	}

-        /* Setup offsets */
-        flash_get_offsets (-size_b0, &flash_info[0]);
+	/* Setup offsets */
+	flash_get_offsets (-size_b0, &flash_info[0]);

-        /* Re-do sizing to get full correct info */
-        mtdcr(ebccfga, pb0cr);
-        pbcr = mfdcr(ebccfgd);
-        mtdcr(ebccfga, pb0cr);
-        base_b0 = -size_b0;
+	/* Re-do sizing to get full correct info */
+	mtdcr(ebccfga, pb0cr);
+	pbcr = mfdcr(ebccfgd);
+	mtdcr(ebccfga, pb0cr);
+	base_b0 = -size_b0;
 	switch (size_b0) {
 	case 1 << 20:
 		size_val = 0;
@@ -90,15 +90,15 @@ unsigned long flash_init (void)
 		break;
 	}
 	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
-        mtdcr(ebccfgd, pbcr);
+	mtdcr(ebccfgd, pbcr);

-        /* Monitor protection ON by default */
-        (void)flash_protect(FLAG_PROTECT_SET,
-                            -CFG_MONITOR_LEN,
-                            0xffffffff,
-                            &flash_info[0]);
+	/* Monitor protection ON by default */
+	(void)flash_protect(FLAG_PROTECT_SET,
+			    -CFG_MONITOR_LEN,
+			    0xffffffff,
+			    &flash_info[0]);

-        flash_info[0].size = size_b0;
+	flash_info[0].size = size_b0;

 	return (size_b0);
 #endif
--- a/board/dave/common/flash.c
+++ b/board/dave/common/flash.c
@@ -40,11 +40,11 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 	short n;

 	/* set up sector start address table */
-        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
 	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
 	    for (i = 0; i < info->sector_count; i++)
 		info->start[i] = base + (i * 0x00010000);
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@@ -58,7 +58,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 			base += 64 << 10;
 			++i;
 		}
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@@ -75,7 +75,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-        } else {
+	} else {
 	    if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
@@ -103,10 +103,10 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
 void flash_print_info  (flash_info_t *info)
 {
 	int i;
-        int k;
-        int size;
-        int erased;
-        volatile unsigned long *flash;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *flash;

 	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("missing or unknown FLASH type\n");
@@ -164,28 +164,28 @@ void flash_print_info  (flash_info_t *info)
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
 #ifdef CFG_FLASH_EMPTY_INFO
-                /*
-                 * Check if whole sector is erased
-                 */
-                if (i != (info->sector_count-1))
-                  size = info->start[i+1] - info->start[i];
-                else
-                  size = info->start[0] + info->size - info->start[i];
-                erased = 1;
-                flash = (volatile unsigned long *)info->start[i];
-                size = size >> 2;        /* divide by 4 for longword access */
-                for (k=0; k<size; k++)
-                  {
-                    if (*flash++ != 0xffffffff)
-                      {
-                        erased = 0;
-                        break;
-                      }
-                  }
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count-1))
+		  size = info->start[i+1] - info->start[i];
+		else
+		  size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++)
+		  {
+		    if (*flash++ != 0xffffffff)
+		      {
+			erased = 0;
+			break;
+		      }
+		  }

 		if ((i % 5) == 0)
 			printf ("\n   ");
-                /* print empty and read-only info */
+		/* print empty and read-only info */
 		printf (" %08lX%s%s",
 			info->start[i],
 			erased ? " E" : "  ",
@@ -219,7 +219,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	short n;
 	CFG_FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-        volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;

 	/* Write auto select command: read Manufacturer ID */
 	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
@@ -288,42 +288,42 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		break;				/* => 2 MB		*/

 	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
-	        info->flash_id += FLASH_STMW320DT;
-	        info->sector_count = 67;
+		info->flash_id += FLASH_STMW320DT;
+		info->sector_count = 67;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
-	        info->flash_id += FLASH_AM320T;
-	        info->sector_count = 71;
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
-	        info->flash_id += FLASH_AM320B;
+		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
-	        info->flash_id += FLASH_AMDL322T;
-	        info->sector_count = 71;
+		info->flash_id += FLASH_AMDL322T;
+		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
-	        info->flash_id += FLASH_AMDL322B;
+		info->flash_id += FLASH_AMDL322B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
-	        info->flash_id += FLASH_AMDL323T;
+		info->flash_id += FLASH_AMDL323T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
-	        info->flash_id += FLASH_AMDL323B;
+		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/

 	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
-	        info->flash_id += FLASH_AM640U;
+		info->flash_id += FLASH_AM640U;
 		info->sector_count = 128;
 		info->size = 0x00800000;  break;	/* => 8 MB	*/

@@ -346,11 +346,11 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	}

 	/* set up sector start address table */
-        if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
 	    ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
 	    for (i = 0; i < info->sector_count; i++)
 		info->start[i] = base + (i * 0x00010000);
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
@@ -364,7 +364,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			base += 64 << 10;
 			++i;
 		}
-        } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+	} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
 		   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
@@ -381,13 +381,13 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-        } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+	} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
 		/* set sector offsets for top boot block type		*/
 		base += info->size;
 		i = info->sector_count;
-                /*  1 x 16k boot sector */
+		/*  1 x 16k boot sector */
 		base -= 16 << 10;
-                --i;
+		--i;
 		info->start[i] = base;
 		/*  2 x 8k  boot sectors */
 		for (n=0; n<2; ++n) {
@@ -395,9 +395,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-                /*  1 x 32k boot sector */
+		/*  1 x 32k boot sector */
 		base -= 32 << 10;
-                --i;
+		--i;
 		info->start[i] = base;

 		while (i > 0) {			/* 64k regular sectors	*/
@@ -405,7 +405,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 			--i;
 			info->start[i] = base;
 		}
-        } else {
+	} else {
 	    if (info->flash_id & FLASH_BTYPE) {
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
@@ -432,10 +432,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
 		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
-                if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
-                  info->protect[i] = 0;
-                else
-                  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+		  info->protect[i] = 0;
+		else
+		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
 	}

 	/*
@@ -459,7 +459,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	volatile CFG_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
-        int i;
+	int i;

 	if ((s_first < 0) || (s_first > s_last)) {
 		if (info->flash_id == FLASH_UNKNOWN) {
@@ -498,25 +498,25 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
-                    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                        addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-                        addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                        addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                        addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
-                        for (i=0; i<50; i++)
-                          udelay(1000);  /* wait 1 ms */
-                    } else {
-                        if (sect == s_first) {
-                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                            addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-                            addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-                            addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-                        }
-                        addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
-                    }
+		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			for (i=0; i<50; i++)
+			  udelay(1000);  /* wait 1 ms */
+		    } else {
+			if (sect == s_first) {
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			}
+			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+		    }
 		    l_sect = sect;
 		}
 	}
@@ -637,42 +637,42 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-        volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-        volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
-        volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
-        int i;
+	int i;

 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
-             (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+	     (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();

-        for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
-          {
-            addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-            addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-            addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+	  {
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;

-            dest2[i] = data2[i];
+	    dest2[i] = data2[i];

-            /* re-enable interrupts if necessary */
-            if (flag)
-              enable_interrupts();
+	    /* re-enable interrupts if necessary */
+	    if (flag)
+	      enable_interrupts();

-            /* data polling for D7 */
-            start = get_timer (0);
-            while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-                   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
-              if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-                return (1);
-              }
-            }
-          }
+	    /* data polling for D7 */
+	    start = get_timer (0);
+	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		return (1);
+	      }
+	    }
+	  }

 	return (0);
 }
--- a/board/dave/common/fpga.c
+++ b/board/dave/common/fpga.c
@@ -57,16 +57,16 @@
 #define SET_FPGA(data)         out32(GPIO0_OR, data)

 #define FPGA_WRITE_1 {                                                    \
-        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
-        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set data to 1  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);  /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */

 #define FPGA_WRITE_0 {                                                    \
-        SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
-        SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
-        SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */
+	SET_FPGA(FPGA_PRG |            FPGA_DATA);  /* set clock to 0 */  \
+	SET_FPGA(FPGA_PRG);                         /* set data to 0  */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK);              /* set clock to 1 */  \
+	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1  */

 #if 0
 static int fpga_boot (unsigned char *fpgadata, int size)
--- a/board/dbau1x00/Makefile
+++ b/board/dbau1x00/Makefile
@@ -0,0 +1,41 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+SOBJS	= memsetup.o
+
+$(LIB):	.depend $(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/dbau1x00/README
+++ b/board/dbau1x00/README
@@ -0,0 +1,53 @@
+By Thomas.Lange@corelatus.se 2003-10-06
+----------------------------------------
+DbAu1000 is a development board from AMD containing
+an Alchemy AU1000 with mips32 core.
+
+Limitations & comments
+----------------------
+I assume that you set board to BIG endian!
+Little endian not tested, most probably broken.
+
+I named the board dbau1x00, to allow
+support for all three development boards
+some day ( dbau1000, dbau1100 and dbau1500 ).
+
+I only have a dbau1000, so all testing is limited
+to this board!
+
+The board has two different flash banks, that can
+be selected via dip switch. This makes it possible
+to test new bootloaders without thrashing the YAMON
+boot loader deliviered with board.
+
+Ethernet only supported for mac0.
+
+Pcmcia only supported for slot 0, only 3.3V.
+
+Pcmcia IDE tested with Sandisk Compact Flash and
+IBM microdrive.
+
+###################################
+########     NOTE!!!!!!   #########
+###################################
+If you partition a disk on another system (e.g. laptop),
+all bytes will be swapped on 16bit level when using
+PCMCIA!!!!
+
+This is probably due to an error in Au1000 chip.
+
+Solution:
+
+a) Boot via network and partition disk directly from
+dbau1x00. The endian will then be correct.
+
+b) Partition disk on "laptop" and fill it with all files
+you need. Then write a simple program that endian swaps
+whole disk,
+
+Example:
+Original "laptop" byte order:
+B0 B1 B2 B3 B4 B5 B6 B7 B8 B9...
+
+Dbau1000 byte order will then be:
+B1 B0 B3 B2 B5 B4 B7 B6 B9 B8...
--- a/board/dbau1x00/config.mk
+++ b/board/dbau1x00/config.mk
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# AMD development board AMD Alchemy DbAu1x00, MIPS32 core
+#
+
+# ROM version
+TEXT_BASE = 0xbfc00000
+
+# RAM version
+#TEXT_BASE = 0x80100000
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2003
+ * Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+long int initdram(int board_type)
+{
+	/* Sdram is setup by assembler code */
+	/* If memory could be changed, we should return the true value here */
+	return 64*1024*1024;
+}
+
+#define BCSR_PCMCIA_PC0DRVEN		0x0010
+#define BCSR_PCMCIA_PC0RST		0x0080
+
+/* In cpu/mips/cpu.c */
+void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
+
+int checkboard (void)
+{
+	u16 status;
+	volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
+	volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
+	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
+	u32 proc_id;
+
+	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
+
+	proc_id = read_32bit_cp0_register(CP0_PRID);
+
+	switch(proc_id>>24){
+	case 0:
+	  puts("Board: Merlot (DbAu1000)\n");
+	  printf("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
+		 (proc_id>>8)&0xFF,proc_id&0xFF);
+	  break;
+	default:
+	  printf("Unsupported cpu %d, proc_id=0x%x\n",proc_id>>24,proc_id);
+	}
+#ifdef CONFIG_IDE_PCMCIA
+	/* Enable 3.3 V on slot 0 ( VCC )
+	   No 5V */
+	status = 4;
+	*pcmcia_bcsr = status;
+
+	status |= BCSR_PCMCIA_PC0DRVEN;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(300*1000);
+
+	status |= BCSR_PCMCIA_PC0RST;
+	*pcmcia_bcsr = status;
+	au_sync();
+
+	udelay(100*1000);
+
+	/* PCMCIA is on a 36 bit physical address.
+	   We need to map it into a 32 bit addresses */
+
+#if 0
+	/* We dont need theese unless we run whole pcmcia package */
+	write_one_tlb(20,                 /* index */
+		      0x01ffe000,         /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_IO_BASE, /* Hi */
+		      0x3C000017,         /* Lo0 */
+		      0x3C200017);        /* Lo1 */
+
+	write_one_tlb(21,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_ATTR_BASE, /* Hi */
+		      0x3D000017,           /* Lo0 */
+		      0x3D200017);          /* Lo1 */
+#endif
+	write_one_tlb(22,                   /* index */
+		      0x01ffe000,           /* Pagemask, 16 MB pages */
+		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
+		      0x3E000017,           /* Lo0 */
+		      0x3E200017);          /* Lo1 */
+
+	/* Release reset of ethernet PHY chips */
+	/* Always do this, because linux does not know about it */
+	*phy = 3;
+
+	return 0;
+#endif
+}
--- a/board/dbau1x00/flash.c
+++ b/board/dbau1x00/flash.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+unsigned long flash_init (void)
+{
+	printf ("Skipping flash_init\n");
+	return (0);
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	printf ("write_buff not implemented\n");
+	return (-1);
+}
--- a/board/dbau1x00/memsetup.S
+++ b/board/dbau1x00/memsetup.S
@@ -0,0 +1,118 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+
+	.globl	memsetup
+memsetup:
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12 MHz crystal */
+	li              t0, SYS_CPUPLL
+	li              t1, 0x21 /* 396 MHz */
+	sw              t1, 0(t0)
+	sync
+	nop
+
+	/* Setup AUX PLL */
+	li              t0, SYS_AUXPLL
+	li              t1, 8 /* 96 MHz */
+	sw              t1, 0(t0) /* aux pll */
+	sync
+
+/* SDCS 0,1 SDRAM */
+	li		t0, MEM_SDMODE0
+	li		t1, 0x005522AA
+	sw		t1, 0(t0)
+
+	li              t0, MEM_SDMODE1
+	li		t1, 0x005522AA
+	sw		t1, 0(t0)
+
+	li              t0, MEM_SDADDR0
+	li		t1, 0x001003F8
+	sw		t1, 0(t0)
+
+
+	li              t0, MEM_SDADDR1
+	li		t1, 0x001023F8
+	sw		t1, 0(t0)
+	sync
+
+	li              t0, MEM_SDREFCFG
+	li		t1, 0x64000C24 /* Disable */
+	sw		t1, 0(t0)
+	sync
+
+	li              t0, MEM_SDPRECMD
+	sw		zero, 0(t0)
+	sync
+
+	li              t0, MEM_SDAUTOREF
+	sw		zero, 0(t0)
+	sync
+	sw		zero, 0(t0)
+	sync
+
+	li              t0, MEM_SDREFCFG
+	li		t1, 0x66000C24 /* Enable */
+	sw		t1, 0(t0)
+	sync
+
+	li              t0, MEM_SDWRMD0
+	li		t1, 0x00000033
+	sw		t1, 0(t0)
+	sync
+
+	li              t0, MEM_SDWRMD1
+	li		t1, 0x00000033
+	sw		t1, 0(t0)
+	sync
+
+	/*  Static memory controller */
+
+	/* RCE0 AMD 29LV640M MirrorBit Flash */
+	li              t0, MEM_STCFG0
+	li		t1, 0x00000003
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STTIME0
+	li		t1, 0x22080b20
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STADDR0
+	li		t1, 0x11E03F80
+	sw		t1, 0(t0)
+
+	/* RCE1 CPLD Board Logic */
+	li		t0, MEM_STCFG1
+	li		t1, 0x00000080
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STTIME1
+	li		t1, 0x22080a20
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STADDR1
+	li		t1, 0x10c03f00
+	sw		t1, 0(t0)
+
+	/* RCE3 PCMCIA 250ns */
+	li		t0, MEM_STCFG3
+	li		t1, 0x00000002
+	sw		t1, 0(t0)
+
+
+	li		t0, MEM_STTIME3
+	li		t1, 0x280E3E07
+	sw		t1, 0(t0)
+
+	li		t0, MEM_STADDR3
+	li		t1, 0x10000000
+	sw		t1, 0(t0)
+
+	sync
+
+	j	ra
+	nop
--- a/board/dbau1x00/u-boot.lds
+++ b/board/dbau1x00/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips")
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text       :
+	{
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data  : { *(.data) }
+
+	. = ALIGN(4);
+	.sdata  : { *(.sdata) }
+
+	_gp = ALIGN(16);
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss) }
+	.bss  : { *(.bss) }
+	uboot_end = .;
+}
--- a/board/dk1c20/Makefile
+++ b/board/dk1c20/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+SOBJS  = vectors.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/dk1c20/config.mk
+++ b/board/dk1c20/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2003
+# Psyent Corporation
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x018c0000
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
--- a/board/dk1c20/dk1c20.c
+++ b/board/dk1c20/dk1c20.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+void _default_hdlr (void)
+{
+	printf ("default_hdlr\n");
+}
+
+int board_pre_init (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Altera Nios 1C20 Development Kit\n");
+	return 0;
+}
+
+long int initdram (int board_type)
+{
+	return (0);
+}
--- a/board/dk1c20/flash.c
+++ b/board/dk1c20/flash.c
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <nios.h>
+
+/*---------------------------------------------------------------------*/
+#define BANKSZ	(8 * 1024 * 1024)
+#define SECTSZ	(64 * 1024)
+#define USERFLASH (2 * 1024 * 1024)	/* bottom 2 MB for user */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+#define FLASH_WORD_SIZE unsigned char
+
+/*---------------------------------------------------------------------*/
+
+unsigned long flash_init (void)
+{
+	int i;
+	unsigned long addr;
+	flash_info_t *fli = &flash_info[0];
+
+	fli->size = BANKSZ;
+	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->flash_id = FLASH_MAN_AMD;
+
+	addr = CFG_FLASH_BASE;
+	for (i = 0; i < fli->sector_count; ++i) {
+		fli->start[i] = addr;
+		addr += SECTSZ;
+
+		/* Protect all but 2 MByte user area */
+		if (addr < (CFG_FLASH_BASE + USERFLASH))
+			fli->protect[i] = 0;
+		else
+			fli->protect[i] = 1;
+	}
+
+	return (BANKSZ);
+}
+
+/*--------------------------------------------------------------------*/
+void flash_print_info (flash_info_t * info)
+{
+	int i, k;
+	unsigned long size;
+	int erased;
+	volatile unsigned char *flash;
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+
+		/* Check if whole sector is erased */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+		erased = 1;
+		flash = (volatile unsigned char *) info->start[i];
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		/* Print the info */
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s%s", info->start[i], erased ? " E" : "  ",
+			info->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
+
+/*-------------------------------------------------------------------*/
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
+	volatile FLASH_WORD_SIZE *addr2;
+	int prot, sect;
+	int any = 0;
+	unsigned oldpri;
+	ulong start;
+
+	/* Some sanity checking */
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* NOTE: disabling interrupts on Nios can be very bad since it
+	 * also disables the LO_LIMIT exception. It's better here to
+	 * set the interrupt priority to 3 & restore it when we're done.
+	 */
+	oldpri = ipri (3);
+
+	/* It's ok to erase multiple sectors provided we don't delay more
+	 * than 50 usec between cmds ... at which point the erase time-out
+	 * occurs. So don't go and put printf() calls in the loop ... it
+	 * won't be very helpful ;-)
+	 */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr = 0x80;
+			*addr = 0xaa;
+			*addr = 0x55;
+			*addr2 = 0x30;
+			any = 1;
+		}
+	}
+
+	/* Now just wait for 0xff & provide some user feedback while
+	 * we wait.
+	 */
+	if (any) {
+		addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
+		start = get_timer (0);
+		while (*addr2 != 0xff) {
+			udelay (1000 * 1000);
+			putc ('.');
+			if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+				printf ("timeout\n");
+				return 1;
+			}
+		}
+		printf ("\n");
+	}
+
+	/* Restore interrupt priority */
+	ipri (oldpri);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+
+	vu_char *cmd = (vu_char *) info->start[0];
+	vu_char *dst = (vu_char *) addr;
+	unsigned char b;
+	unsigned oldpri;
+	ulong start;
+
+	while (cnt) {
+		/* Check for sufficient erase */
+		b = *src;
+		if ((*dst & b) != b) {
+			printf ("%02x : %02x\n", *dst, b);
+			return (2);
+		}
+
+		/* Disable interrupts other than window underflow
+		 * (interrupt priority 2)
+		 */
+		oldpri = ipri (3);
+		*cmd = 0xaa;
+		*cmd = 0x55;
+		*cmd = 0xa0;
+		*dst = b;
+
+		/* Verify write */
+		start = get_timer (0);
+		while (*dst != b) {
+			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+				ipri (oldpri);
+				return 1;
+			}
+		}
+		dst++;
+		src++;
+		cnt--;
+		ipri (oldpri);
+	}
+
+	return (0);
+}
--- a/board/dk1c20/u-boot.lds
+++ b/board/dk1c20/u-boot.lds
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+OUTPUT_FORMAT("elf32-nios")
+OUTPUT_ARCH(nios)
+ENTRY(_start)
+
+SECTIONS
+{
+	.text :
+	{
+	  cpu/nios/start.o (.text)
+	  *(.text)
+	}
+	__text_end = .;
+
+	. = ALIGN(4);
+	.rodata :
+	{
+		*(.rodata)
+	}
+	__rodata_end = .;
+
+	. = ALIGN(4);
+	.data :
+	{
+		*(.data)
+	}
+	. = ALIGN(4);
+	__data_end = .;
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd :
+	{
+		*(.u_boot_cmd)
+	}
+	. = ALIGN(4);
+	__u_boot_cmd_end = .;
+
+	__bss_start = .;
+	. = ALIGN(4);
+	.bss :
+	{
+		*(.bss)
+	}
+	. = ALIGN(4);
+	__bss_end = .;
+}
--- a/board/dk1c20/vectors.S
+++ b/board/dk1c20/vectors.S
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*************************************************************************
+ * Exception Vector Table
+ *
+ * This could have gone in the cpu soure tree, but the whole point of
+ * Nios is customization -- and polluting the cpu source tree with
+ * board-specific ifdef's really defeats the purpose, no? With this in
+ * the board-specific tree, each board has the freedom to organize
+ * vectors/traps, etc anyway it wants. The init code copies this table
+ * to the proper location.
+ *
+ * Each board can do what it likes here. But there are four "standard"
+ * handlers availble:
+ *
+ *	_cwp_lolimit	-Handles register window underflows.
+ *	_cwp_hilimit	-Handles register window overflows.
+ *	_timebase_int	-Increments the timebase.
+ *	_def_xhandler	-Default exception handler.
+ *
+ * _timebase_int handles a Nios Timer interrupt and increments the
+ * timestamp used for the get_timer(), reset_timer(), etc. routines. It
+ * expects the timer to be configured like the standard-32 low priority
+ * timer.
+ *
+ * _def_xhandler dispatches exceptions/traps via the external_interrupt()
+ * routine. This lets you use the irq_install_handler() and handle your
+ * interrupts/traps with code written in C.
+ ************************************************************************/
+
+	.data
+	.global _vectors
+	.align	4
+_vectors:
+
+	.long	_def_xhandler@h		/* Vector 0  - NMI */
+	.long	_cwp_lolimit@h		/* Vector 1  -  underflow */
+	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
+
+	.long	_def_xhandler@h		/* Vector 3 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 4 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 5 - GNUPro debug */
+	.long	_def_xhandler@h		/* Vector 6 - future reserved */
+	.long	_def_xhandler@h		/* Vector 7 - future reserved */
+	.long	_def_xhandler@h		/* Vector 8 - future reserved */
+	.long	_def_xhandler@h		/* Vector 9 - future reserved */
+	.long	_def_xhandler@h		/* Vector 10 - future reserved */
+	.long	_def_xhandler@h		/* Vector 11 - future reserved */
+	.long	_def_xhandler@h		/* Vector 12 - future reserved */
+	.long	_def_xhandler@h		/* Vector 13 - future reserved */
+	.long	_def_xhandler@h		/* Vector 14 - future reserved */
+	.long	_def_xhandler@h		/* Vector 15 - future reserved */
+	.long	_def_xhandler@h		/* Vector 16 */
+	.long	_def_xhandler@h		/* Vector 17 */
+	.long	_def_xhandler@h		/* Vector 18 */
+	.long	_def_xhandler@h		/* Vector 19 */
+	.long	_def_xhandler@h		/* Vector 20 */
+	.long	_def_xhandler@h		/* Vector 21 */
+	.long	_def_xhandler@h		/* Vector 22 */
+	.long	_def_xhandler@h		/* Vector 23 */
+	.long	_def_xhandler@h		/* Vector 24 */
+	.long	_def_xhandler@h		/* Vector 25 */
+	.long	_def_xhandler@h		/* Vector 26 */
+	.long	_def_xhandler@h		/* Vector 27 */
+	.long	_def_xhandler@h		/* Vector 28 */
+	.long	_def_xhandler@h		/* Vector 29 */
+	.long	_def_xhandler@h		/* Vector 30 */
+	.long	_def_xhandler@h		/* Vector 31 */
+	.long	_def_xhandler@h		/* Vector 32 */
+	.long	_def_xhandler@h		/* Vector 33 */
+	.long	_def_xhandler@h		/* Vector 34 */
+	.long	_def_xhandler@h		/* Vector 35 */
+	.long	_def_xhandler@h		/* Vector 36 */
+	.long	_def_xhandler@h		/* Vector 37 */
+	.long	_def_xhandler@h		/* Vector 38 */
+	.long	_def_xhandler@h		/* Vector 39 */
+	.long	_def_xhandler@h		/* Vector 40 */
+	.long	_def_xhandler@h		/* Vector 41 */
+	.long	_def_xhandler@h		/* Vector 42 */
+	.long	_def_xhandler@h		/* Vector 43 */
+	.long	_def_xhandler@h		/* Vector 44 */
+	.long	_def_xhandler@h		/* Vector 45 */
+	.long	_def_xhandler@h		/* Vector 46 */
+	.long	_def_xhandler@h		/* Vector 47 */
+	.long	_def_xhandler@h		/* Vector 48 */
+	.long	_def_xhandler@h		/* Vector 49 */
+	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
+	.long	_def_xhandler@h		/* Vector 51 */
+	.long	_def_xhandler@h		/* Vector 52 */
+	.long	_def_xhandler@h		/* Vector 53 */
+	.long	_def_xhandler@h		/* Vector 54 */
+	.long	_def_xhandler@h		/* Vector 55 */
+	.long	_def_xhandler@h		/* Vector 56 */
+	.long	_def_xhandler@h		/* Vector 57 */
+	.long	_def_xhandler@h		/* Vector 58 */
+	.long	_def_xhandler@h		/* Vector 59 */
+	.long	_def_xhandler@h		/* Vector 60 */
+	.long	_def_xhandler@h		/* Vector 61 */
+	.long	_def_xhandler@h		/* Vector 62 */
+	.long	_def_xhandler@h		/* Vector 63 */
--- a/board/esd/common/xilinx_jtag/lenval.c
+++ b/board/esd/common/xilinx_jtag/lenval.c
@@ -64,7 +64,7 @@ long value( lenVal*     plvValue )
 * Returns:      void.
 *****************************************************************************/
 void initLenVal( lenVal*    plv,
-                 long       lValue )
+		 long       lValue )
 {
 	plv->len    = 1;
 	plv->val[0] = (unsigned char)lValue;
@@ -79,8 +79,8 @@ void initLenVal( lenVal*    plv,
 * Returns:      short   - 0 = mismatch; 1 = equal.
 *****************************************************************************/
 short EqualLenVal( lenVal*  plvTdoExpected,
-                   lenVal*  plvTdoCaptured,
-                   lenVal*  plvTdoMask )
+		   lenVal*  plvTdoCaptured,
+		   lenVal*  plvTdoMask )
 {
 	short           sEqual;
 	short           sIndex;
@@ -120,8 +120,8 @@ short EqualLenVal( lenVal*  plvTdoExpected,
 * Returns:      short   - the bit value.
 *****************************************************************************/
 short RetBit( lenVal*   plv,
-              int       iByte,
-              int       iBit )
+	      int       iByte,
+	      int       iBit )
 {
 	/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
 	/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
@@ -139,9 +139,9 @@ short RetBit( lenVal*   plv,
 * Returns:      void.
 *****************************************************************************/
 void SetBit( lenVal*    plv,
-             int        iByte,
-             int        iBit,
-             short      sVal )
+	     int        iByte,
+	     int        iBit,
+	     short      sVal )
 {
 	unsigned char   ucByteVal;
 	unsigned char   ucBitMask;
@@ -166,8 +166,8 @@ void SetBit( lenVal*    plv,
 * Returns:      void.
 *****************************************************************************/
 void addVal( lenVal*    plvResVal,
-             lenVal*    plvVal1,
-             lenVal*    plvVal2 )
+	     lenVal*    plvVal1,
+	     lenVal*    plvVal2 )
 {
 	unsigned char   ucCarry;
 	unsigned short  usSum;
@@ -204,7 +204,7 @@ void addVal( lenVal*    plvResVal,
 * Returns:      void.
 *****************************************************************************/
 void readVal( lenVal*   plv,
-              short     sNumBytes )
+	      short     sNumBytes )
 {
 	unsigned char*  pucVal;

--- a/board/esd/common/xilinx_jtag/micro.c
+++ b/board/esd/common/xilinx_jtag/micro.c
@@ -114,20 +114,20 @@ extern int filesize;

 #ifdef  DEBUG_MODE
 #define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat ); }
 #define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat, arg1 ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1 ); }
 #define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat, arg1, arg2 ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2 ); }
 #define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    printf( pzFormat, arg1, arg2, arg3 ); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    printf( pzFormat, arg1, arg2, arg3 ); }
 #define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
-                { if ( xsvf_iDebugLevel >= iDebugLevel ) \
-                    xsvfPrintLenVal(plenVal); }
+		{ if ( xsvf_iDebugLevel >= iDebugLevel ) \
+		    xsvfPrintLenVal(plenVal); }
 #else   /* !DEBUG_MODE */
 #define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
 #define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
@@ -327,68 +327,68 @@ TXsvfDoCmdFuncPtr   xsvf_pfDoCmd[]  =
 #ifdef  DEBUG_MODE
 char* xsvf_pzCommandName[]  =
 {
-        "XCOMPLETE",
-        "XTDOMASK",
-        "XSIR",
-        "XSDR",
-        "XRUNTEST",
-        "Reserved5",
-        "Reserved6",
-        "XREPEAT",
-        "XSDRSIZE",
-        "XSDRTDO",
-        "XSETSDRMASKS",
-        "XSDRINC",
-        "XSDRB",
-        "XSDRC",
-        "XSDRE",
-        "XSDRTDOB",
-        "XSDRTDOC",
-        "XSDRTDOE",
-        "XSTATE",
-        "XENDIR",
-        "XENDDR",
-        "XSIR2",
-        "XCOMMENT",
-        "XWAIT"
+	"XCOMPLETE",
+	"XTDOMASK",
+	"XSIR",
+	"XSDR",
+	"XRUNTEST",
+	"Reserved5",
+	"Reserved6",
+	"XREPEAT",
+	"XSDRSIZE",
+	"XSDRTDO",
+	"XSETSDRMASKS",
+	"XSDRINC",
+	"XSDRB",
+	"XSDRC",
+	"XSDRE",
+	"XSDRTDOB",
+	"XSDRTDOC",
+	"XSDRTDOE",
+	"XSTATE",
+	"XENDIR",
+	"XENDDR",
+	"XSIR2",
+	"XCOMMENT",
+	"XWAIT"
 };

 char*   xsvf_pzErrorName[]  =
 {
-        "No error",
-        "ERROR:  Unknown",
-        "ERROR:  TDO mismatch",
-        "ERROR:  TDO mismatch and exceeded max retries",
-        "ERROR:  Unsupported XSVF command",
-        "ERROR:  Illegal state specification",
-        "ERROR:  Data overflows allocated MAX_LEN buffer size"
+	"No error",
+	"ERROR:  Unknown",
+	"ERROR:  TDO mismatch",
+	"ERROR:  TDO mismatch and exceeded max retries",
+	"ERROR:  Unsupported XSVF command",
+	"ERROR:  Illegal state specification",
+	"ERROR:  Data overflows allocated MAX_LEN buffer size"
 };

 char*   xsvf_pzTapState[] =
 {
-        "RESET",        /* 0x00 */
-        "RUNTEST/IDLE", /* 0x01 */
-        "DRSELECT",     /* 0x02 */
-        "DRCAPTURE",    /* 0x03 */
-        "DRSHIFT",      /* 0x04 */
-        "DREXIT1",      /* 0x05 */
-        "DRPAUSE",      /* 0x06 */
-        "DREXIT2",      /* 0x07 */
-        "DRUPDATE",     /* 0x08 */
-        "IRSELECT",     /* 0x09 */
-        "IRCAPTURE",    /* 0x0A */
-        "IRSHIFT",      /* 0x0B */
-        "IREXIT1",      /* 0x0C */
-        "IRPAUSE",      /* 0x0D */
-        "IREXIT2",      /* 0x0E */
-        "IRUPDATE"      /* 0x0F */
+	"RESET",        /* 0x00 */
+	"RUNTEST/IDLE", /* 0x01 */
+	"DRSELECT",     /* 0x02 */
+	"DRCAPTURE",    /* 0x03 */
+	"DRSHIFT",      /* 0x04 */
+	"DREXIT1",      /* 0x05 */
+	"DRPAUSE",      /* 0x06 */
+	"DREXIT2",      /* 0x07 */
+	"DRUPDATE",     /* 0x08 */
+	"IRSELECT",     /* 0x09 */
+	"IRCAPTURE",    /* 0x0A */
+	"IRSHIFT",      /* 0x0B */
+	"IREXIT1",      /* 0x0C */
+	"IRPAUSE",      /* 0x0D */
+	"IREXIT2",      /* 0x0E */
+	"IRUPDATE"      /* 0x0F */
 };
 #endif  /* DEBUG_MODE */

-//#ifdef DEBUG_MODE
-//    FILE* in;   /* Legacy DEBUG_MODE file pointer */
+/*#ifdef DEBUG_MODE	*/
+/*    FILE* in;   /XXX* Legacy DEBUG_MODE file pointer */
 int xsvf_iDebugLevel;
-//#endif /* DEBUG_MODE */
+/*#endif /XXX* DEBUG_MODE */

 /*============================================================================
 * Utility Functions
@@ -493,7 +493,7 @@ void xsvfTmsTransition( short sTms )
 * Returns:      int             - 0 = success; otherwise error.
 *****************************************************************************/
 int xsvfGotoTapState( unsigned char*   pucTapState,
-                      unsigned char    ucTargetState )
+		      unsigned char    ucTargetState )
 {
 	int i;
 	int iErrorCode;
@@ -708,9 +708,9 @@ int xsvfGotoTapState( unsigned char*   pucTapState,
 * Returns:      void.
 *****************************************************************************/
 void xsvfShiftOnly( long    lNumBits,
-                    lenVal* plvTdi,
-                    lenVal* plvTdoCaptured,
-                    int     iExitShift )
+		    lenVal* plvTdi,
+		    lenVal* plvTdoCaptured,
+		    int     iExitShift )
 {
 	unsigned char*  pucTdi;
 	unsigned char*  pucTdo;
@@ -796,15 +796,15 @@ void xsvfShiftOnly( long    lNumBits,
 *               is NOT all zeros and sMatch==1.
 *****************************************************************************/
 int xsvfShift( unsigned char*   pucTapState,
-               unsigned char    ucStartState,
-               long             lNumBits,
-               lenVal*          plvTdi,
-               lenVal*          plvTdoCaptured,
-               lenVal*          plvTdoExpected,
-               lenVal*          plvTdoMask,
-               unsigned char    ucEndState,
-               long             lRunTestTime,
-               unsigned char    ucMaxRepeat )
+	       unsigned char    ucStartState,
+	       long             lNumBits,
+	       lenVal*          plvTdi,
+	       lenVal*          plvTdoCaptured,
+	       lenVal*          plvTdoExpected,
+	       lenVal*          plvTdoMask,
+	       unsigned char    ucEndState,
+	       long             lRunTestTime,
+	       unsigned char    ucMaxRepeat )
 {
 	int             iErrorCode;
 	int             iMismatch;
@@ -935,15 +935,15 @@ int xsvfShift( unsigned char*   pucTapState,
 * Returns:      int                 - 0 = success; otherwise TDO mismatch.
 *****************************************************************************/
 int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
-                      long              lShiftLengthBits,
-                      short             sShiftLengthBytes,
-                      lenVal*           plvTdi,
-                      lenVal*           plvTdoCaptured,
-                      lenVal*           plvTdoExpected,
-                      lenVal*           plvTdoMask,
-                      unsigned char     ucEndState,
-                      long              lRunTestTime,
-                      unsigned char     ucMaxRepeat )
+		      long              lShiftLengthBits,
+		      short             sShiftLengthBytes,
+		      lenVal*           plvTdi,
+		      lenVal*           plvTdoCaptured,
+		      lenVal*           plvTdoExpected,
+		      lenVal*           plvTdoMask,
+		      unsigned char     ucEndState,
+		      long              lRunTestTime,
+		      unsigned char     ucMaxRepeat )
 {
 	readVal( plvTdi, sShiftLengthBytes );
 	if ( plvTdoExpected )
@@ -968,9 +968,9 @@ int xsvfBasicXSDRTDO( unsigned char*    pucTapState,
 *****************************************************************************/
 #ifdef  XSVF_SUPPORT_COMPRESSION
 void xsvfDoSDRMasking( lenVal*  plvTdi,
-                       lenVal*  plvNextData,
-                       lenVal*  plvAddressMask,
-                       lenVal*  plvDataMask )
+		       lenVal*  plvNextData,
+		       lenVal*  plvAddressMask,
+		       lenVal*  plvDataMask )
 {
 	int             i;
 	unsigned char   ucTdi;
--- a/board/esd/common/xilinx_jtag/micro.h
+++ b/board/esd/common/xilinx_jtag/micro.h
@@ -1,64 +1,64 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*****************************************************************************
- * File:         micro.h
- * Description:  This header file contains the function prototype to the
- *               primary interface function for the XSVF player.
- * Usage:        FIRST - PORTS.C
- *               Customize the ports.c function implementations to establish
- *               the correct protocol for communicating with your JTAG ports
- *               (setPort() and readTDOBit()) and tune the waitTime() delay
- *               function.  Also, establish access to the XSVF data source
- *               in the readByte() function.
- *               FINALLY - Call xsvfExecute().
- *****************************************************************************/
-#ifndef XSVF_MICRO_H
-#define XSVF_MICRO_H
-
-/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
-#define XSVF_LEGACY_SUCCESS 1
-#define XSVF_LEGACY_ERROR   0
-
-/* 4.04 [NEW] Error codes for xsvfExecute. */
-/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
-#define XSVF_ERROR_NONE         0
-#define XSVF_ERROR_UNKNOWN      1
-#define XSVF_ERROR_TDOMISMATCH  2
-#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
-#define XSVF_ERROR_ILLEGALCMD   4
-#define XSVF_ERROR_ILLEGALSTATE 5
-#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
-/* Insert new errors here */
-#define XSVF_ERROR_LAST         7
-
-/*****************************************************************************
- * Function:     xsvfExecute
- * Description:  Process, interpret, and apply the XSVF commands.
- *               See port.c:readByte for source of XSVF data.
- * Parameters:   none.
- * Returns:      int - For error codes see above.
- *****************************************************************************/
-int xsvfExecute(void);
-
-#endif  /* XSVF_MICRO_H */
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File:         micro.h
+ * Description:  This header file contains the function prototype to the
+ *               primary interface function for the XSVF player.
+ * Usage:        FIRST - PORTS.C
+ *               Customize the ports.c function implementations to establish
+ *               the correct protocol for communicating with your JTAG ports
+ *               (setPort() and readTDOBit()) and tune the waitTime() delay
+ *               function.  Also, establish access to the XSVF data source
+ *               in the readByte() function.
+ *               FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR   0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE         0
+#define XSVF_ERROR_UNKNOWN      1
+#define XSVF_ERROR_TDOMISMATCH  2
+#define XSVF_ERROR_MAXRETRIES   3   /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD   4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6   /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST         7
+
+/*****************************************************************************
+ * Function:     xsvfExecute
+ * Description:  Process, interpret, and apply the XSVF commands.
+ *               See port.c:readByte for source of XSVF data.
+ * Parameters:   none.
+ * Returns:      int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif  /* XSVF_MICRO_H */
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -97,7 +97,7 @@ int checkboard (void)
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 	unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
-                                   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+				   0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
 	unsigned char id1, id2;

 	puts ("Board: ");
--- a/board/etin/debris/Makefile
+++ b/board/etin/debris/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o phantom.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/etin/debris/config.mk
+++ b/board/etin/debris/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000, 2001
+# Sangmoon, Etin Systems, dogoil@etinsys.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Debris boards
+#
+
+#TEXT_BASE = 0x00090000
+TEXT_BASE = 0xFFF00000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
--- a/board/etin/debris/debris.c
+++ b/board/etin/debris/debris.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2000
+ * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc824x.h>
+#include <pci.h>
+
+int checkboard (void)
+{
+	/*TODO: Check processor type */
+
+	puts (	"Board: Debris "
+#ifdef CONFIG_MPC8240
+		"8240"
+#endif
+#ifdef CONFIG_MPC8245
+		"8245"
+#endif
+		" ##Test not implemented yet##\n");
+	return 0;
+}
+
+#if 0 	/* NOT USED */
+int checkflash (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("## Test not implemented yet ##\n");
+
+	return (0);
+}
+#endif
+
+long int initdram (int board_type)
+{
+	int		 i, cnt;
+	volatile uchar * base= CFG_SDRAM_BASE;
+	volatile ulong * addr;
+	ulong		 save[32];
+	ulong		 val, ret  = 0;
+
+	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
+		addr = (volatile ulong *)base + cnt;
+		save[i++] = *addr;
+		*addr = ~cnt;
+	}
+
+	addr = (volatile ulong *)base;
+	save[i] = *addr;
+	*addr = 0;
+
+	if (*addr != 0) {
+		*addr = save[i];
+		goto Done;
+	}
+
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
+		addr = (volatile ulong *)base + cnt;
+		val = *addr;
+		*addr = save[--i];
+		if (val != ~cnt) {
+/*			ulong new_bank0_end = cnt * sizeof(long) - 1;
+			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
+			mear1 =  (mear1  & 0xFFFFFF00) |
+			((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+			emear1 = (emear1 & 0xFFFFFF00) |
+			((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg(MEAR1,  mear1);
+			mpc824x_mpc107_setreg(EMEAR1, emear1);*/
+
+			ret = cnt * sizeof(long);
+			goto Done;
+		}
+	}
+
+	ret = CFG_MAX_RAM_SIZE;
+Done:
+	return ret;
+}
+
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_debris_config_table[] = {
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				       PCI_ENET0_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
+				       PCI_ENET1_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ }
+};
+#endif
+
+struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_debris_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+	pci_mpc824x_init(&hose);
+}
+
+void *nvram_read(void *dest, const long src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*) dest;
+	volatile uchar *s = (volatile uchar*) src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+	return dest;
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	volatile uchar *d = (volatile uchar*)dest;
+	volatile uchar *s = (volatile uchar*)src;
+	while(count--) {
+		*d++ = *s++;
+		asm volatile("sync");
+	}
+}
+
+int misc_init_r(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* Write ethernet addr in NVRAM for VxWorks */
+	nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
+			(char*)&gd->bd->bi_enetaddr[0], 6);
+	return 0;
+}
--- a/board/etin/debris/flash.c
+++ b/board/etin/debris/flash.c
@@ -0,0 +1,720 @@
+/*
+ * board/eva/flash.c
+ *
+ * (C) Copyright 2002
+ * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/pci_io.h>
+#include <mpc824x.h>
+
+int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
+int (*write_dword)(flash_info_t*, ulong, uint64_t);
+
+typedef uint64_t cfi_word;
+
+#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
+
+#define cfi_write(flash, val, addr) \
+	move64((cfi_word*)&val, \
+			(cfi_word*)(flash->start[0] + addr))
+
+#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
+
+static void write32(unsigned long addr, uint32_t value)
+{
+	*(volatile uint32_t*)(addr) = value;
+	asm volatile("sync");
+}
+
+static uint32_t read32(unsigned long addr)
+{
+	uint32_t value;
+	value = *(volatile uint32_t*)addr;
+	asm volatile("sync");
+	return value;
+}
+
+static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
+{
+	uint32_t base = flash->start[0];
+	uint32_t val=(cmd << 16) | cmd;
+	addr <<= 3;
+	write32(base + addr, val);
+	return addr;
+}
+
+static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
+{
+	uint32_t base = flash->start[0];
+	addr <<= 3;
+	return (uint16_t)read32(base + addr);
+}
+
+flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+static void move64(uint64_t *src, uint64_t *dest)
+{
+	asm volatile("lfd  0, 0(3)\n\t" /* fpr0   =  *scr       */
+	 "stfd 0, 0(4)"         /* *dest  =  fpr0       */
+	 : : : "fr0" );         /* Clobbers fr0         */
+	return;
+}
+
+static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
+{
+	unsigned long start;
+	cfi_word status = 0;
+
+	status = cfi_read(flash, dest);
+	data &= status;
+
+	cfi_cmd(flash, 0x40, 0);
+	cfi_write(flash, data, dest);
+
+	udelay(10);
+	start = get_timer (0);
+	for(;;) {
+		status = cfi_read(flash, dest);
+		status &= CMD(0x80);
+		if(status == CMD(0x80))
+			break;
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			cfi_cmd(flash, 0xff, 0);
+			return 1;
+		}
+		udelay(1);
+	}
+	cfi_cmd(flash, 0xff, 0);
+
+	return 0;
+}
+
+static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
+{
+	ulong start;
+	cfi_word status = 0;
+
+	status = cfi_read(flash, dest);
+	if(status != CMD(0xffff)) return 2;
+
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	cfi_cmd(flash, 0xa0, 0x555);
+
+	cfi_write(flash, data, dest);
+
+	udelay(10);
+	start = get_timer (0);
+	status = ~data;
+	while(status != data) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+			return 1;
+		status = cfi_read(flash, dest);
+		udelay(1);
+	}
+	return 0;
+}
+
+static __inline__ unsigned long get_msr(void)
+{
+	unsigned long msr;
+	__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
+	return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+}
+
+int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	int i, s, l, rc;
+	cfi_word data;
+	uint8_t *t = (uint8_t*)&data;
+	unsigned long base = flash->start[0];
+	uint32_t msr;
+
+	if (flash->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	if (cnt == 0)
+		return 0;
+
+	addr -= base;
+
+	msr = get_msr();
+	set_msr(msr|MSR_FP);
+
+	wp = (addr & ~7);   /* get lower word aligned address */
+
+	if((addr-wp) != 0) {
+		data = cfi_read(flash, wp);
+		s = addr & 7;
+		l = ( cnt < (8-s) ) ? cnt : (8-s);
+		for(i = 0; i < l; i++)
+			t[s+i] = *src++;
+		if ((rc = write_dword(flash, wp, data)) != 0)
+			goto DONE;
+		wp += 8;
+		cnt -= l;
+	}
+
+	while (cnt >= 8) {
+		for (i = 0; i < 8; i++)
+			t[i] = *src++;
+		if ((rc = write_dword(flash, wp, data)) != 0)
+			goto DONE;
+		wp  += 8;
+		cnt -= 8;
+	}
+
+	if (cnt == 0) {
+		rc = 0;
+		goto DONE;
+	}
+
+	data = cfi_read(flash, wp);
+	for(i = 0; i < cnt; i++)
+		t[i] = *src++;
+	rc = write_dword(flash, wp, data);
+DONE:
+	set_msr(msr);
+	return rc;
+}
+
+static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
+{
+	int sa;
+	int flag;
+	ulong start, last, now;
+	cfi_word status;
+
+	flag = disable_interrupts();
+
+	sa = (flash->start[sect] - flash->start[0]);
+	write32(flash->start[sect], 0x00200020);
+	write32(flash->start[sect], 0x00d000d0);
+
+	if (flag)
+		enable_interrupts();
+
+	udelay(1000);
+	start = get_timer (0);
+	last  = start;
+
+	for (;;) {
+		status = cfi_read(flash, sa);
+		status &= CMD(0x80);
+		if (status == CMD(0x80))
+			break;
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			cfi_cmd(flash, 0xff, 0);
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+
+		if ((now - last) > 1000) {
+			serial_putc ('.');
+			last = now;
+		}
+		udelay(10);
+	}
+	cfi_cmd(flash, 0xff, 0);
+	return ERR_OK;
+}
+
+static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
+{
+	int sect;
+	int rc = ERR_OK;
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (flash->protect[sect] == 0) {
+			rc = cfi_erase_oneblock(flash, sect);
+			if (rc != ERR_OK) break;
+		}
+	}
+	printf (" done\n");
+	return rc;
+}
+
+static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
+{
+	int sect;
+	cfi_word status;
+	int sa = -1;
+	int flag;
+	ulong start, last, now;
+
+	flag = disable_interrupts();
+
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	cfi_cmd(flash, 0x80, 0x555);
+	cfi_cmd(flash, 0xaa, 0x555);
+	cfi_cmd(flash, 0x55, 0x2aa);
+	for ( sect = s_first; sect <= s_last; sect++) {
+		if (flash->protect[sect] == 0) {
+			sa = flash->start[sect] - flash->start[0];
+			write32(flash->start[sect], 0x00300030);
+		}
+	}
+	if (flag)
+		enable_interrupts();
+
+	if (sa < 0)
+		goto DONE;
+
+	udelay (1000);
+	start = get_timer (0);
+	last  = start;
+	for(;;) {
+		status = cfi_read(flash, sa);
+		if (status == CMD(0xffff))
+			break;
+
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return ERR_TIMOUT;
+		}
+
+		if ((now - last) > 1000) {
+			serial_putc ('.');
+			last = now;
+		}
+		udelay(10);
+	}
+DONE:
+	cfi_cmd(flash, 0xf0, 0);
+
+	printf (" done\n");
+
+	return ERR_OK;
+}
+
+int flash_erase (flash_info_t *flash, int s_first, int s_last)
+{
+	int sect;
+	int prot;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (flash->flash_id == FLASH_UNKNOWN)
+			printf ("- missing\n");
+		else
+			printf ("- no sectors to erase\n");
+		return ERR_NOT_ERASED;
+	}
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return ERR_NOT_ERASED;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++)
+		if (flash->protect[sect]) prot++;
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+					                        prot);
+	else
+		printf ("\n");
+
+	return do_flash_erase(flash, s_first, s_last);
+}
+
+struct jedec_flash_info {
+	const uint16_t mfr_id;
+	const uint16_t dev_id;
+	const char *name;
+	const int DevSize;
+	const int InterfaceDesc;
+	const int NumEraseRegions;
+	const ulong regions[4];
+};
+
+#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
+
+#define SIZE_1MiB 20
+#define SIZE_2MiB 21
+#define SIZE_4MiB 22
+
+static const struct jedec_flash_info jedec_table[] = {
+	{
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV800T,
+		name: "AMD AM29LV800T",
+		DevSize: SIZE_1MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV800B,
+		name: "AMD AM29LV800B",
+		DevSize: SIZE_1MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,15),
+		          ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV160T,
+		name: "AMD AM29LV160T",
+		DevSize: SIZE_2MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x10000,31),
+		          ERASEINFO(0x08000,1),
+			  ERASEINFO(0x02000,2),
+			  ERASEINFO(0x04000,1)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV160B,
+		name: "AMD AM29LV160B",
+		DevSize: SIZE_2MiB,
+		NumEraseRegions: 4,
+		regions: {ERASEINFO(0x04000,1),
+		          ERASEINFO(0x02000,2),
+			  ERASEINFO(0x08000,1),
+			  ERASEINFO(0x10000,31)
+		}
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV320T,
+		name: "AMD AM29LV320T",
+		DevSize: SIZE_4MiB,
+		NumEraseRegions: 2,
+		regions: {ERASEINFO(0x10000,63),
+		          ERASEINFO(0x02000,8)
+		}
+
+	}, {
+		mfr_id: (uint16_t)AMD_MANUFACT,
+		dev_id: (uint16_t)AMD_ID_LV320B,
+		name: "AMD AM29LV320B",
+		DevSize: SIZE_4MiB,
+		NumEraseRegions: 2,
+		regions: {ERASEINFO(0x02000,8),
+		          ERASEINFO(0x10000,63)
+		}
+	}
+};
+
+static ulong cfi_init(uint32_t base,  flash_info_t *flash)
+{
+	int sector;
+	int block;
+	int block_count;
+	int offset = 0;
+	int reverse = 0;
+	int primary;
+	int mfr_id;
+	int dev_id;
+
+	flash->start[0] = base;
+	cfi_cmd(flash, 0xF0, 0);
+	cfi_cmd(flash, 0x98, 0);
+	if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
+		cfi_read_query(flash, 0x11) == 'R' &&
+		cfi_read_query(flash, 0x12) == 'Y' )) {
+		cfi_cmd(flash, 0xff, 0);
+		return 0;
+	}
+
+	flash->size = 1 << cfi_read_query(flash, 0x27);
+	flash->size *= 4;
+	block_count = cfi_read_query(flash, 0x2c);
+	primary = cfi_read_query(flash, 0x15);
+	if ( cfi_read_query(flash, primary + 4) == 0x30)
+		reverse = (cfi_read_query(flash, 0x1) & 0x01);
+	else
+		reverse = (cfi_read_query(flash, primary+15) == 3);
+
+	flash->sector_count = 0;
+
+	for ( block = reverse ? block_count - 1	: 0;
+		      reverse ? block >= 0	: block < block_count;
+		      reverse ? block--		: block ++) {
+		int sector_size =
+			(cfi_read_query(flash, 0x2d + block*4+2) |
+			(cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
+		int sector_count =
+			(cfi_read_query(flash, 0x2d + block*4+0) |
+			(cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
+		for(sector = 0; sector < sector_count; sector++) {
+			flash->start[flash->sector_count++] = base + offset;
+			offset += sector_size * 4;
+		}
+	}
+	mfr_id = cfi_read_query(flash, 0x00);
+	dev_id = cfi_read_query(flash, 0x01);
+
+	cfi_cmd(flash, 0xff, 0);
+
+	flash->flash_id = (mfr_id << 16) | dev_id;
+
+	for (sector = 0; sector < flash->sector_count; sector++) {
+		write32(flash->start[sector], 0x00600060);
+		write32(flash->start[sector], 0x00d000d0);
+	}
+	cfi_cmd(flash, 0xff, 0);
+
+	for (sector = 0; sector < flash->sector_count; sector++)
+		flash->protect[sector] = 0;
+
+	do_flash_erase = cfi_erase;
+	write_dword = cfi_write_dword;
+
+	return flash->size;
+}
+
+static ulong jedec_init(unsigned long base, flash_info_t *flash)
+{
+	int i;
+	int block, block_count;
+	int sector, offset;
+	int mfr_id, dev_id;
+	flash->start[0] = base;
+	cfi_cmd(flash, 0xF0, 0x000);
+	cfi_cmd(flash, 0xAA, 0x555);
+	cfi_cmd(flash, 0x55, 0x2AA);
+	cfi_cmd(flash, 0x90, 0x555);
+	mfr_id = cfi_read_query(flash, 0x000);
+	dev_id = cfi_read_query(flash, 0x0001);
+	cfi_cmd(flash, 0xf0, 0x000);
+
+	for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
+		if((jedec_table[i].mfr_id == mfr_id) &&
+			(jedec_table[i].dev_id == dev_id)) {
+
+			flash->flash_id = (mfr_id << 16) | dev_id;
+			flash->size = 1 << jedec_table[0].DevSize;
+			flash->size *= 4;
+			block_count = jedec_table[i].NumEraseRegions;
+			offset = 0;
+			flash->sector_count = 0;
+			for (block = 0; block < block_count; block++) {
+				int sector_size = jedec_table[i].regions[block];
+				int sector_count = (sector_size & 0xff) + 1;
+				sector_size >>= 8;
+				for (sector=0; sector<sector_count; sector++) {
+					flash->start[flash->sector_count++] =
+						base + offset;
+					offset += sector_size * 4;
+				}
+			}
+			break;
+		}
+	}
+
+	for (sector = 0; sector < flash->sector_count; sector++)
+		flash->protect[sector] = 0;
+
+	do_flash_erase = jedec_erase;
+	write_dword = jedec_write_dword;
+
+	return flash->size;
+}
+
+inline void mtibat1u(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   530, %0" :: "r" (x));
+}
+
+inline void mtibat1l(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   531, %0" :: "r" (x));
+}
+
+inline void mtdbat1u(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   538, %0" :: "r" (x));
+}
+
+inline void mtdbat1l(unsigned int x)
+{
+	__asm__ __volatile__ ("mtspr   539, %0" :: "r" (x));
+}
+
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+	unsigned int msr;
+
+	/* BAT1 */
+	CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
+	CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
+	msr = get_msr();
+	set_msr(msr & ~(MSR_IR | MSR_DR));
+	mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
+	mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
+	set_msr(msr);
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
+	if (!size)
+		size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN)
+		printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+
+	return size;
+}
+
+void flash_print_info  (flash_info_t *flash)
+{
+	int i;
+	int k;
+	int size;
+	int erased;
+	volatile unsigned long *p;
+
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		flash_init();
+	}
+
+	if (flash->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (((flash->flash_id) >> 16) & 0xff) {
+	case 0x01:
+		printf ("AMD ");
+		break;
+	case 0x04:
+		printf("FUJITSU ");
+		break;
+	case 0x20:
+		printf("STM ");
+		break;
+	case 0xBF:
+		printf("SST ");
+		break;
+	case 0x89:
+	case 0xB0:
+		printf("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch ((flash->flash_id) & 0xffff) {
+	case (uint16_t)AMD_ID_LV800T:
+		printf ("AM29LV800T\n");
+		break;
+	case (uint16_t)AMD_ID_LV800B:
+		printf ("AM29LV800B\n");
+		break;
+	case (uint16_t)AMD_ID_LV160T:
+		printf ("AM29LV160T\n");
+		break;
+	case (uint16_t)AMD_ID_LV160B:
+		printf ("AM29LV160B\n");
+		break;
+	case (uint16_t)AMD_ID_LV320T:
+		printf ("AM29LV320T\n");
+		break;
+	case (uint16_t)AMD_ID_LV320B:
+		printf ("AM29LV320B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F800C3T:
+		printf ("28F800C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F800C3B:
+		printf ("28F800C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F160C3T:
+		printf ("28F160C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F160C3B:
+		printf ("28F160C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F320C3T:
+		printf ("28F320C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F320C3B:
+		printf ("28F320C3B\n");
+		break;
+	case (uint16_t)INTEL_ID_28F640C3T:
+		printf ("28F640C3T\n");
+		break;
+	case (uint16_t)INTEL_ID_28F640C3B:
+		printf ("28F640C3B\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (flash->size >= (1 << 20)) {
+		printf ("  Size: %ld MB in %d Sectors\n",
+				flash->size >> 20, flash->sector_count);
+	} else {
+		printf ("  Size: %ld kB in %d Sectors\n",
+				flash->size >> 10, flash->sector_count);
+	}
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < flash->sector_count; ++i) {
+		/* Check if whole sector is erased*/
+		if (i != (flash->sector_count-1))
+			size = flash->start[i+1] - flash->start[i];
+		else
+			size = flash->start[0] + flash->size - flash->start[i];
+
+		erased = 1;
+		p = (volatile unsigned long *)flash->start[i];
+		size = size >> 2;        /* divide by 4 for longword access */
+		for (k=0; k<size; k++) {
+			if (*p++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s%s",
+			flash->start[i],
+			erased ? " E" : "  ",
+			flash->protect[i] ? "RO " : "   ");
+	}
+	printf ("\n");
+}
--- a/board/etin/debris/phantom.c
+++ b/board/etin/debris/phantom.c
@@ -0,0 +1,310 @@
+/*
+ * board/eva/phantom.c
+ *
+ * Phantom RTC device driver for EVA
+ *
+ * Author: Sangmoon Kim
+ *         dogoil@etinsys.com
+ *
+ * Copyright 2002 Etinsys Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8)
+
+#define RTC_YEAR                ( RTC_BASE + 7 )
+#define RTC_MONTH               ( RTC_BASE + 6 )
+#define RTC_DAY_OF_MONTH        ( RTC_BASE + 5 )
+#define RTC_DAY_OF_WEEK         ( RTC_BASE + 4 )
+#define RTC_HOURS               ( RTC_BASE + 3 )
+#define RTC_MINUTES             ( RTC_BASE + 2 )
+#define RTC_SECONDS             ( RTC_BASE + 1 )
+#define RTC_CENTURY             ( RTC_BASE + 0 )
+
+#define RTC_CONTROLA            RTC_CENTURY
+#define RTC_CONTROLB            RTC_SECONDS
+#define RTC_CONTROLC            RTC_DAY_OF_WEEK
+
+#define RTC_CA_WRITE            0x80
+#define RTC_CA_READ             0x40
+
+#define RTC_CB_OSC_DISABLE      0x80
+
+#define RTC_CC_BATTERY_FLAG     0x80
+#define RTC_CC_FREQ_TEST        0x40
+
+
+static int phantom_flag = -1;
+static int century_flag = -1;
+
+static uchar rtc_read(unsigned int addr)
+{
+	return *(volatile unsigned char *)(addr);
+}
+
+static void rtc_write(unsigned int addr, uchar val)
+{
+	*(volatile unsigned char *)(addr) = val;
+}
+
+static unsigned char phantom_rtc_sequence[] = {
+	0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
+};
+
+static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
+{
+	int i, j;
+	unsigned char v;
+	unsigned char save = rtc_read(addr);
+
+	for (j = 0; j < 8; j++) {
+		v = phantom_rtc_sequence[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	for (j = 0; j < 8; j++) {
+		v = 0;
+		for (i = 0; i < 8; i++) {
+			if(rtc_read(addr) & 1)
+				v |= 1 << i;
+		}
+		rtc[j] = v;
+	}
+	rtc_write(addr, save);
+	return rtc;
+}
+
+static void phantom_rtc_write(int addr, unsigned char rtc[8])
+{
+	int i, j;
+	unsigned char v;
+	unsigned char save = rtc_read(addr);
+	for (j = 0; j < 8; j++) {
+		v = phantom_rtc_sequence[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	for (j = 0; j < 8; j++) {
+		v = rtc[j];
+		for (i = 0; i < 8; i++) {
+			rtc_write(addr, v & 1);
+			v >>= 1;
+		}
+	}
+	rtc_write(addr, save);
+}
+
+static int get_phantom_flag(void)
+{
+	int i;
+	unsigned char rtc[8];
+
+	phantom_rtc_read(RTC_BASE, rtc);
+
+	for(i = 1; i < 8; i++) {
+		if (rtc[i] != rtc[0])
+			return 1;
+	}
+	return 0;
+}
+
+void rtc_reset(void)
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag) {
+		unsigned char rtc[8];
+		phantom_rtc_read(RTC_BASE, rtc);
+		if(rtc[4] & 0x30) {
+			printf( "real-time-clock was stopped. Now starting...\n" );
+			rtc[4] &= 0x07;
+			phantom_rtc_write(RTC_BASE, rtc);
+		}
+	} else {
+		uchar reg_a, reg_b, reg_c;
+		reg_a = rtc_read( RTC_CONTROLA );
+		reg_b = rtc_read( RTC_CONTROLB );
+
+		if ( reg_b & RTC_CB_OSC_DISABLE )
+		{
+			printf( "real-time-clock was stopped. Now starting...\n" );
+			reg_a |= RTC_CA_WRITE;
+			reg_b &= ~RTC_CB_OSC_DISABLE;
+			rtc_write( RTC_CONTROLA, reg_a );
+			rtc_write( RTC_CONTROLB, reg_b );
+		}
+
+		/* make sure read/write clock register bits are cleared */
+		reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
+		rtc_write( RTC_CONTROLA, reg_a );
+
+		reg_c = rtc_read( RTC_CONTROLC );
+		if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
+			printf( "RTC battery low. Clock setting may not be reliable.\n");
+	}
+}
+
+inline unsigned bcd2bin (uchar n)
+{
+	return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+inline unsigned char bin2bcd (unsigned int n)
+{
+	return (((n / 10) << 4) | (n % 10));
+}
+
+static int get_century_flag(void)
+{
+	int flag = 0;
+	int bcd, century;
+	bcd = rtc_read( RTC_CENTURY );
+	century = bcd2bin( bcd & 0x3F );
+	rtc_write( RTC_CENTURY, bin2bcd(century+1));
+	if (bcd == rtc_read( RTC_CENTURY ))
+		flag = 1;
+	rtc_write( RTC_CENTURY, bcd);
+	return flag;
+}
+
+void rtc_get( struct rtc_time *tmp)
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag)
+	{
+		unsigned char rtc[8];
+
+		phantom_rtc_read(RTC_BASE, rtc);
+
+		tmp->tm_sec	= bcd2bin(rtc[1] & 0x7f);
+		tmp->tm_min	= bcd2bin(rtc[2] & 0x7f);
+		tmp->tm_hour	= bcd2bin(rtc[3] & 0x1f);
+		tmp->tm_wday	= bcd2bin(rtc[4] & 0x7);
+		tmp->tm_mday	= bcd2bin(rtc[5] & 0x3f);
+		tmp->tm_mon	= bcd2bin(rtc[6] & 0x1f);
+		tmp->tm_year	= bcd2bin(rtc[7]) + 1900;
+		tmp->tm_yday = 0;
+		tmp->tm_isdst = 0;
+
+		if( (rtc[3] & 0x80)  && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
+		if (tmp->tm_year < 1970) tmp->tm_year += 100;
+	} else {
+		uchar sec, min, hour;
+		uchar mday, wday, mon, year;
+
+		int century;
+
+		uchar reg_a;
+
+		if (century_flag < 0)
+			century_flag = get_century_flag();
+
+		reg_a = rtc_read( RTC_CONTROLA );
+		/* lock clock registers for read */
+		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
+
+		sec     = rtc_read( RTC_SECONDS );
+		min     = rtc_read( RTC_MINUTES );
+		hour    = rtc_read( RTC_HOURS );
+		mday    = rtc_read( RTC_DAY_OF_MONTH );
+		wday    = rtc_read( RTC_DAY_OF_WEEK );
+		mon     = rtc_read( RTC_MONTH );
+		year    = rtc_read( RTC_YEAR );
+		century = rtc_read( RTC_CENTURY );
+
+		/* unlock clock registers after read */
+		rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
+
+		tmp->tm_sec  = bcd2bin( sec  & 0x7F );
+		tmp->tm_min  = bcd2bin( min  & 0x7F );
+		tmp->tm_hour = bcd2bin( hour & 0x3F );
+		tmp->tm_mday = bcd2bin( mday & 0x3F );
+		tmp->tm_mon  = bcd2bin( mon & 0x1F );
+		tmp->tm_wday = bcd2bin( wday & 0x07 );
+
+		if (century_flag) {
+			tmp->tm_year = bcd2bin( year ) +
+				( bcd2bin( century & 0x3F ) * 100 );
+		} else {
+			tmp->tm_year = bcd2bin( year ) + 1900;
+			if (tmp->tm_year < 1970) tmp->tm_year += 100;
+		}
+
+		tmp->tm_yday = 0;
+		tmp->tm_isdst= 0;
+	}
+}
+
+void rtc_set( struct rtc_time *tmp )
+{
+	if (phantom_flag < 0)
+		phantom_flag = get_phantom_flag();
+
+	if (phantom_flag) {
+		uint year;
+		unsigned char rtc[8];
+
+		year = tmp->tm_year;
+		year -= (year < 2000) ? 1900 : 2000;
+
+		rtc[0] = bin2bcd(0);
+		rtc[1] = bin2bcd(tmp->tm_sec);
+		rtc[2] = bin2bcd(tmp->tm_min);
+		rtc[3] = bin2bcd(tmp->tm_hour);
+		rtc[4] = bin2bcd(tmp->tm_wday);
+		rtc[5] = bin2bcd(tmp->tm_mday);
+		rtc[6] = bin2bcd(tmp->tm_mon);
+		rtc[7] = bin2bcd(year);
+
+		phantom_rtc_write(RTC_BASE, rtc);
+	} else {
+		uchar reg_a;
+		if (century_flag < 0)
+			century_flag = get_century_flag();
+
+		/* lock clock registers for write */
+		reg_a = rtc_read( RTC_CONTROLA );
+		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
+
+		rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
+
+		rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
+		rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
+		rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
+		rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
+		rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
+
+		/* break year up into century and year in century */
+		if (century_flag) {
+			rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
+			rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
+			reg_a &= 0xc0;
+			reg_a |= bin2bcd( tmp->tm_year / 100 );
+		} else {
+			rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
+				((tmp->tm_year < 2000) ? 1900 : 2000)));
+		}
+
+		/* unlock clock registers after read */
+		rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
+	}
+}
+
+#endif
--- a/board/etin/debris/speed.h
+++ b/board/etin/debris/speed.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*-----------------------------------------------------------------------
+ * Timer value for timer 2, ICLK = 10
+ *
+ * SPEED_FCOUNT2 =  GCLK / (16 * (TIMER_TMR_PS + 1))
+ * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
+ *
+ * SPEED_FCOUNT2	timer 2 counting frequency
+ * GCLK	      		CPU clock
+ * SPEED_TMR2_PS	prescaler
+ */
+#define SPEED_TMR2_PS  	(250 - 1)	/* divide by 250	*/
+
+/*-----------------------------------------------------------------------
+ * Timer value for PIT
+ *
+ * PIT_TIME = SPEED_PITC / PITRTCLK
+ * PITRTCLK = 8192
+ */
+#define SPEED_PITC	(82 << 16)	/* start counting from 82	*/
+
+/*
+ * The new value for PTA is calculated from
+ *
+ *	PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
+ *
+ * gclk		CPU clock (not bus clock !)
+ * Trefresh	Refresh cycle * 4 (four word bursts used)
+ * DFBRG	For normal mode (no clock reduction) always 0
+ * PTP		Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
+ * NCS		Number of SDRAM banks (chip selects) on this UPM.
+ */
--- a/board/etin/debris/u-boot.lds
+++ b/board/etin/debris/u-boot.lds
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc824x/start.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_ppc/ppcstring.o	(.text)
+
+	. = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o (.text)
+
+	*(.text)
+
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/evb64260/flash.c
+++ b/board/evb64260/flash.c
@@ -79,7 +79,11 @@ flash_init (void)
 	size_b0 = flash_get_size(CFG_BOOT_FLASH_WIDTH, (vu_long *)base,
 	                         &flash_info[0]);

-	printf("[%ldkB@%lx] ", size_b0/1024, base);
+#ifndef CONFIG_P3G4
+	printf("[");
+	print_size (size_b0, "");
+	printf("@%08lX] ", base);
+#endif

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n",
@@ -90,7 +94,11 @@ flash_init (void)
 	for(i=1;i<CFG_MAX_FLASH_BANKS;i++) {
 	    unsigned long size = flash_get_size(CFG_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);

-	    printf("[%ldMB@%lx] ", size>>20, base);
+#ifndef CONFIG_P3G4
+	    printf("[");
+	    print_size (size, "");
+	    printf("@%08lX] ", size>>20, base);
+#endif

 	    if (flash_info[i].flash_id == FLASH_UNKNOWN) {
 		if(i==1) {
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -123,7 +123,7 @@ static flash_info_t *flash_get_info(ulong base)

 	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
-		if (info->size && 
+		if (info->size &&
 			info->start[0] <= base && base <= info->start[0] + info->size - 1)
 			break;
 	}
@@ -260,7 +260,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
 	addr2 = (FPW *)((ulong)addr | 0x800000);
 	if (addr2 != addr &&
 		((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
-		/* Seems 2 banks are the same space (8Mb chip is installed, 
+		/* Seems 2 banks are the same space (8Mb chip is installed,
 		 * J24 in default position (CS0)). Disable this (first) bank.
 		 */
 		info->flash_id = FLASH_UNKNOWN;
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -174,9 +174,9 @@ void flash_preinit(void)
 void flash_afterinit(ulong size)
 {
 	if (size == 0x800000) { /* adjust mapping */
-		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = 
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 			START_REG(CFG_BOOTCS_START | size);
-		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = 
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 			STOP_REG(CFG_BOOTCS_START | size, size);
 	}
 }
--- a/board/ixdp425/Makefile
+++ b/board/ixdp425/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= ixdp425.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/ixdp425/config.mk
+++ b/board/ixdp425/config.mk
@@ -0,0 +1,2 @@
+#TEXT_BASE = 0x00100000
+TEXT_BASE = 0x00f00000
--- a/board/ixdp425/flash.c
+++ b/board/ixdp425/flash.c
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               		x
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               		__swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		default:
+			panic ("configured to many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
+		       &flash_info[0]);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW * addr, flash_info_t * info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];	/* device ID            */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status =
+				 *addr) & (FPW) 0x00800080) !=
+			       (FPW) 0x00800080) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = (FPW) 0x00500050;	/* clear status register cmd.   */
+			*addr = (FPW) 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
--- a/board/ixdp425/ixdp425.c
+++ b/board/ixdp425/ixdp425.c
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/ixp425.h>
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/* local prototypes */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int
+/**********************************************************/
+board_post_init (void)
+/**********************************************************/
+{
+	return (0);
+}
+
+int
+/**********************************************************/
+board_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = 245;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	return 0;
+}
+
+int
+/**********************************************************/
+dram_init (void)
+/**********************************************************/
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
--- a/board/ixdp425/u-boot.lds
+++ b/board/ixdp425/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/ixp/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	armboot_end_data = .;
+
+	. = ALIGN(4);
+	bss_start = .;
+	.bss : { *(.bss) }
+	bss_end = .;
+
+	armboot_end = .;
+}
--- a/board/mpc8266ads/mpc8266ads.c
+++ b/board/mpc8266ads/mpc8266ads.c
@@ -562,13 +562,13 @@ long int initdram(int board_type)
    printf(", Using Bank Based Interleave\n");
 #else
    printf(", Using Page Based Interleave\n");
-#endif    
+#endif
 	printf("\tTotal size: ");

-    /* this delay only needed for original 16MB DIMM... 
+    /* this delay only needed for original 16MB DIMM...
     * Not needed for any other memory configuration */
    if ((sdram_size * chipselects) == (16 *1024 *1024))
-        udelay (250000);
+	udelay (250000);
    return (sdram_size * chipselects);
 	/*return (16 * 1024 * 1024);*/
 }
@@ -584,4 +584,3 @@ void pci_init_board(void)
 	pci_mpc8250_init(&hose);
 }
 #endif
-
--- a/board/mpc8540ads/Makefile
+++ b/board/mpc8540ads/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/mpc8540ads/config.mk
+++ b/board/mpc8540ads/config.mk
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- a/board/mpc8540ads/flash.c
+++ b/board/mpc8540ads/flash.c
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	case FLASH_28F640J3A:   printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+	value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1] & 0x00FF00FF;             /* device ID            */
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case (INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		sector_offset = 0x40000;
+		break;                          /* => 2x8 MB             */
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			asm("sync");
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			asm("sync");
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			asm("sync");
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			asm("sync");
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			asm("sync");
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			    asm("sync");
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if(*addr & 0x00200020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+			asm("sync");
+		}
+	}
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+	asm("sync");
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	asm("sync");
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+	asm("sync");
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+	start = get_timer (0);
+	while((*addr & 0x00800080) != 0x00800080){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
--- a/board/mpc8540ads/init.S
+++ b/board/mpc8540ads/init.S
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if defined(CFG_FLASH_PORT_WIDTH_16)
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+  #if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+  #if defined(CONFIG_RAM_AS_FLASH)
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+  #else
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+  #ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+  #else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,8,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,9,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+	entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
--- a/board/mpc8540ads/mpc8540ads.c
+++ b/board/mpc8540ads/mpc8540ads.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+long int fixed_sdram (void);
+
+/* MPC8540ADS Board Status & Control Registers */
+#if 0
+typedef struct bscr_ {
+	unsigned long bcsr0;
+	unsigned long bcsr1;
+	unsigned long bcsr2;
+	unsigned long bcsr3;
+	unsigned long bcsr4;
+	unsigned long bcsr5;
+	unsigned long bcsr6;
+	unsigned long bcsr7;
+} bcsr_t;
+#endif
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Motorola MPC8540ADS Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	return (0);
+}
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
--- a/board/mpc8540ads/u-boot.lds
+++ b/board/mpc8540ads/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8540ads/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8540ads/init.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/pci.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/mpc8560ads/Makefile
+++ b/board/mpc8560ads/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+SOBJS	:= init.o
+#SOBJS	:=
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/mpc8560ads/config.mk
+++ b/board/mpc8560ads/config.mk
@@ -0,0 +1,32 @@
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- a/board/mpc8560ads/flash.c
+++ b/board/mpc8560ads/flash.c
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ *  Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	unsigned long size;
+	int i;
+
+	/* Init: enable write,
+	 * or we cannot even write flash commands
+	 */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+
+		/* set the default sector offset */
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size, size<<20);
+	}
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      &flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+#endif
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
+	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+				break;
+	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+				break;
+	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+				break;
+	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+				break;
+	case FLASH_28F640J3A:   printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+				break;
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+	ulong sector_offset;
+
+#ifdef DEBUG
+	printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+	/* Write "Intelligent Identifier" command: read Manufacturer ID */
+	*addr = 0x90909090;
+	udelay(20);
+	asm("sync");
+
+	value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+	printf("manufacturer=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case MT_MANUFACT:	/* SHARP, MT or => Intel */
+	case INTEL_ALT_MANU:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		printf("unknown manufacturer: %x\n", (unsigned int)value);
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[1] & 0x00FF00FF;             /* device ID            */
+
+#ifdef DEBUG
+	printf("deviceID=0x%x\n",(uint)value);
+#endif
+	switch (value) {
+	case (INTEL_ID_28F016S):
+		info->flash_id += FLASH_28F016SV;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F160S3):
+		info->flash_id += FLASH_28F160S3;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		sector_offset = 0x20000;
+		break;				/* => 2x2 MB		*/
+
+	case (INTEL_ID_28F320S3):
+		info->flash_id += FLASH_28F320S3;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		sector_offset = 0x20000;
+		break;				/* => 2x4 MB		*/
+
+	case (INTEL_ID_28F640J3A):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x01000000;
+		sector_offset = 0x40000;
+		break;                          /* => 8 MB             */
+
+	case SHARP_ID_28F016SCL:
+	case SHARP_ID_28F016SCZ:
+		info->flash_id      = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+		info->sector_count  = 32;
+		info->size          = 0x00800000;
+		sector_offset = 0x40000;
+		break;				/* => 4x2 MB		*/
+
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = base;
+		base += sector_offset;
+		/* don't know how to check sector protection */
+		info->protect[i] = 0;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_long *)info->start[0];
+		*addr = 0xFFFFFF;	/* reset bank to read array mode */
+		asm("sync");
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+#ifdef DEBUG
+	printf("\nFlash Erase:\n");
+#endif
+	/* Make Sure Block Lock Bit is not set. */
+	if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+		return 1;
+	}
+
+	/* Start erase on unprotected sectors */
+#if defined(DEBUG)
+	printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *)(info->start[sect]);
+			asm("sync");
+
+			last = start = get_timer (0);
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts();
+
+			/* Reset Array */
+			*addr = 0xffffffff;
+			asm("sync");
+			/* Clear Status Register */
+			*addr = 0x50505050;
+			asm("sync");
+			/* Single Block Erase Command */
+			*addr = 0x20202020;
+			asm("sync");
+			/* Confirm */
+			*addr = 0xD0D0D0D0;
+			asm("sync");
+
+			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+			    /* Resume Command, as per errata update */
+			    *addr = 0xD0D0D0D0;
+			    asm("sync");
+			}
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+			while ((*addr & 0x00800080) != 0x00800080) {
+				if(*addr & 0x00200020){
+					printf("Error in Block Erase - Lock Bit may be set!\n");
+					printf("Status Register = 0x%X\n", (uint)*addr);
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xFFFFFFFF;	/* reset bank */
+					asm("sync");
+					return 1;
+				}
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+			}
+
+			/* reset to read mode */
+			*addr = 0xFFFFFFFF;
+			asm("sync");
+		}
+	}
+
+	printf ("flash erase done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)dest;
+	ulong start, csr;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Write Command */
+	*addr = 0x10101010;
+	asm("sync");
+
+	/* Write Data */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	flag  = 0;
+
+	while (((csr = *addr) & 0x00800080) != 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			flag = 1;
+			break;
+		}
+	}
+	if (csr & 0x40404040) {
+		printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+		flag = 1;
+	}
+
+	/* Clear Status Registers Command */
+	*addr = 0x50505050;
+	asm("sync");
+	/* Reset to read array mode */
+	*addr = 0xFFFFFFFF;
+	asm("sync");
+
+	return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long  * addr)
+{
+	ulong start, now;
+
+	/* Reset Array */
+	*addr = 0xffffffff;
+	asm("sync");
+	/* Clear Status Register */
+	*addr = 0x50505050;
+	asm("sync");
+
+	*addr = 0x60606060;
+	asm("sync");
+	*addr = 0xd0d0d0d0;
+	asm("sync");
+
+	start = get_timer (0);
+	while((*addr & 0x00800080) != 0x00800080){
+		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout on clearing Block Lock Bit\n");
+			*addr = 0xFFFFFFFF;	/* reset bank */
+			asm("sync");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
--- a/board/mpc8560ads/init.S
+++ b/board/mpc8560ads/init.S
@@ -0,0 +1,178 @@
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define	entry_start \
+	mflr	r1 	;	\
+	bl	0f 	;
+
+#define	entry_end \
+0:	mflr	r0	;	\
+	mtlr	r1	;	\
+	blr		;
+
+/* TLB1 entries configuration: */
+
+	.section	.bootpg, "ax"
+	.globl	tlb1_entry
+tlb1_entry:
+	entry_start
+
+	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+
+	.long TLB1_MAS0(1,1,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if defined(CFG_FLASH_PORT_WIDTH_16)
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,2,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,3,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+  #if !defined(CONFIG_SPD_EEPROM)
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,4,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,5,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+
+	.long TLB1_MAS0(1,6,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+  #if defined(CONFIG_RAM_AS_FLASH)
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+  #else
+	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,7,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+  #ifdef CONFIG_L2_INIT_RAM
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+  #else
+	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+  #endif
+	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,8,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1,9,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+  #else
+	.long TLB1_MAS0(1,15,0)
+	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+  #endif
+	entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ *   f800_0000-fbff_ffff: LBC SDRAM(64M)
+ *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ *   fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ *       Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+	.section .bootpg, "ax"
+	.globl  law_entry
+law_entry:
+	entry_start
+	.long 0x03
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	entry_end
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
+	/* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
+	/* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
+	/* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
+	/* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
+	/* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
+	/* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
+	/* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
+	/* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
+	/* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
+	/* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
+	/* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
+    },
+
+    /* Port D */
+    {   /*            conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
+	/* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* MPC8560ADS Board Status & Control Registers */
+typedef struct bscr_ {
+	volatile unsigned char bcsr0;
+	volatile unsigned char bcsr1;
+	volatile unsigned char bcsr2;
+	volatile unsigned char bcsr3;
+	volatile unsigned char bcsr4;
+	volatile unsigned char bcsr5;
+} bcsr_t;
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+    pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+	return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+	/* reset Giga bit Ethernet port if needed here */
+
+	/* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+	bcsr->bcsr2 &= ~FETH2_RST;
+	udelay(2);
+	bcsr->bcsr2 |=  FETH2_RST;
+	udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+	bcsr->bcsr3 &= ~FETH3_RST;
+	udelay(2);
+	bcsr->bcsr3 |=  FETH3_RST;
+	udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+	miiphy_reset(0x0);	/* reset PHY */
+	miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
+	miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info (&sysinfo);
+
+	printf ("Board: Motorola MPC8560ADS Board\n");
+	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	} else {
+		printf("\tLBC: unknown\n");
+	}
+	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+
+	return (0);
+}
+
+
+long int initdram (int board_type)
+{
+	long dram_size = 0;
+	extern long spd_sdram (void);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	sys_info_t sysinfo;
+	uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+	volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+	uint temp_ddrdll = 0;
+
+	/* Work around to stabilize DDR DLL */
+	temp_ddrdll = gur->ddrdllcr;
+	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+	dram_size = spd_sdram ();
+#else
+	dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
+	get_sys_info(&sysinfo);
+	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	} else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		udelay(200);
+		temp_lbcdll = gur->lbcdllcr;
+		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		asm("sync;isync;msync");
+	}
+	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	(unsigned int) * (ulong *)0 = 0x000000ff;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	lbc->lsrt = CFG_LBC_LSRT;
+	asm("sync");
+	lbc->mrtpr = CFG_LBC_MRTPR;
+	asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+	{
+		/* Initialize all of memory for ECC, then
+		 * enable errors */
+		uint *p = 0;
+		uint i = 0;
+		volatile immap_t *immap = (immap_t *)CFG_IMMR;
+		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+		dma_init();
+		for (*p = 0; p < (uint *)(8 * 1024); p++) {
+			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+			*p = (unsigned int)0xdeadbeef;
+			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+		}
+
+		/* 8K */
+		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+		/* 16K */
+		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+		/* 32K */
+		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+		/* 64K */
+		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+		/* 128k */
+		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+		/* 256k */
+		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+		/* 512k */
+		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+		/* 1M */
+		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+		/* 2M */
+		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+		/* 4M */
+		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+		for (i = 1; i < dram_size / 0x800000; i++) {
+			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+		}
+
+		/* Enable errors for ECC */
+		ddr->err_disable = 0x00000000;
+		asm("sync;isync;msync");
+	}
+#endif
+
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("SDRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("SDRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("SDRAM test passed.\n");
+	return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+  #ifndef CFG_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+	ddr->sdram_mode = CFG_DDR_MODE;
+	ddr->sdram_interval = CFG_DDR_INTERVAL;
+    #if defined (CONFIG_DDR_ECC)
+	ddr->err_disable = 0x0000000D;
+	ddr->err_sbe = 0x00ff0000;
+    #endif
+	asm("sync;isync;msync");
+	udelay(500);
+    #if defined (CONFIG_DDR_ECC)
+	/* Enable ECC checking */
+	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+    #else
+	ddr->sdram_cfg = CFG_DDR_CONTROL;
+    #endif
+	asm("sync; isync; msync");
+	udelay(500);
+  #endif
+	return ( CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif	/* !defined(CONFIG_SPD_EEPROM) */
--- a/board/mpc8560ads/u-boot.lds
+++ b/board/mpc8560ads/u-boot.lds
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  .bootpg 0xFFFFF000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+    board/mpc8560ads/init.o (.bootpg)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc85xx/start.o	(.text)
+    board/mpc8560ads/init.o (.text)
+    cpu/mpc85xx/commproc.o (.text)
+    cpu/mpc85xx/traps.o (.text)
+    cpu/mpc85xx/interrupts.o (.text)
+    cpu/mpc85xx/serial_scc.o (.text)
+    cpu/mpc85xx/ether_fcc.o (.text)
+    cpu/mpc85xx/cpu_init.o (.text)
+    cpu/mpc85xx/cpu.o (.text)
+    cpu/mpc85xx/tsec.o (.text)
+    cpu/mpc85xx/speed.o (.text)
+    cpu/mpc85xx/i2c.o (.text)
+    cpu/mpc85xx/spd_sdram.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -86,14 +86,14 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt);
 * The first thing we do is to map the Flash CS to the Flash area and
 * the MPS CS to the MPS area. Since the flash size is unknown at this
 * point, we use the max flash size and the lowest flash address as base.
- * 
+ *
 * After flash detection we adjust the size of the CS area accordingly.
 * The board_init_r will fill in wrong values in the board init structure,
 * but this will be fixed in the misc_init_r routine:
 * bd->bi_flashstart=0-flash_info[0].size
 * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
 * bd->bi_flashoffset=0
- * 
+ *
 */
 int get_boot_mode(void)
 {
@@ -152,10 +152,9 @@ void setup_cs_reloc(void)
 }


-
 unsigned long flash_init (void)
 {
-	unsigned long size_b0, size_b1,flashcr;
+	unsigned long size_b0, size_b1,flashcr, size_reg;
 	int mode, i;
 	extern char version_string;
 	char *p=&version_string;
@@ -196,6 +195,21 @@ unsigned long flash_init (void)
 	size_b1 = 0 ;
 	flash_info[0].size = size_b0;
 	/* set up flash cs according to the size */
+	size_reg=(flash_info[0].size >>20);
+	switch (size_reg) {
+		case 0:
+		case 1: i=0; break; /* <= 1MB */
+		case 2: i=1; break; /* = 2MB */
+		case 4: i=2; break; /* = 4MB */
+		case 8: i=3; break; /* = 8MB */
+		case 16: i=4; break; /* = 16MB */
+		case 32: i=5; break; /* = 32MB */
+		case 64: i=6; break; /* = 64MB */
+		case 128: i=7; break; /*= 128MB */
+		default:
+			printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
+			while(1);
+	}
 	if(mode & BOOT_MPS) {
 		/* flash is on CS1 */
 		mtdcr(ebccfga, pb1cr);
@@ -203,7 +217,7 @@ unsigned long flash_init (void)
 		/* we map the flash high in every case */
 		flashcr&=0x0001FFFF; /* mask out address bits */
 		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
-		flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+		flashcr|= (i << 17); /* size addr */
 		mtdcr(ebccfga, pb1cr);
 		mtdcr(ebccfgd, flashcr);
 	}
@@ -214,7 +228,7 @@ unsigned long flash_init (void)
 		/* we map the flash high in every case */
 		flashcr&=0x0001FFFF; /* mask out address bits */
 		flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */
-		flashcr|= (((flash_info[0].size >>21) & 0x07) << 17); /* size addr */
+		flashcr|= (i << 17); /* size addr */
 		mtdcr(ebccfga, pb0cr);
 		mtdcr(ebccfgd, flashcr);
 	}
@@ -330,7 +344,7 @@ void flash_print_info  (flash_info_t *info)


 /*-----------------------------------------------------------------------
- 
+
 */

 /*
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -167,6 +167,15 @@ const sdram_t sdram_table[] = {
 		3,	/* Address Mode = 3 */
 		5,	/* size value */
 		1},	/* ECC enabled */
+	{ 0x2f,	/* Rev C, 128MByte -3 Board */
+		3,	/* Case Latenty = 3 */
+		3,	/* trp 20ns / 7.5 ns datain[27] */
+		3,	/* trcd 20ns /7.5 ns (datain[29]) */
+		6,	/* tras 44ns /7.5 ns  (datain[30]) */
+		4,	/* tcpt 44 - 20ns = 24ns */
+		3,	/* Address Mode = 3 */
+		5,	/* size value */
+		1},	/* ECC enabled */
 	{ 0xff, /* terminator */
 	  0xff,
 	  0xff,
@@ -550,7 +559,8 @@ void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
 		tmp >>= 1;
 	}
 	rc++;
-	if((((bc>>4) & 0xf)==0x1) /* Rev B PCB with */
+	if((  (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
+	   || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
 		&& (rc==0x1))     /* Population Option 1 is a -3 */
 		rc=3;
 	*pcbrev=(bc >> 4) & 0xf;
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -178,4 +178,3 @@ U_BOOT_CMD(
 	"vcma9   - VCMA9 specific commands\n",
 	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory\n"
 );
-
--- a/board/mpl/vcma9/memsetup.S
+++ b/board/mpl/vcma9/memsetup.S
@@ -153,14 +153,14 @@ memsetup:
 	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
 	mov	r4, #SDRAMDATA1_END-SDRAMDATA
 	/* calculate start and end point */
-	mla	r0, r3, r4, r0 
+	mla	r0, r3, r4, r0
 	add     r2, r0, r4
 0:
 	ldr     r3, [r0], #4
 	str     r3, [r1], #4
 	cmp     r2, r0
 	bne     0b
-	
+
 	/* everything is fine now */
 	mov	pc, lr

@@ -194,7 +194,7 @@ SDRAMDATA1_END:
    .word 0x32 + BURST_EN
    .word 0x30
    .word 0x30
-    
+
 /* 2Mx8x4 (not implemented yet) */
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
@@ -202,7 +202,7 @@ SDRAMDATA1_END:
    .word 0x32 + BURST_EN
    .word 0x30
    .word 0x30
-    
+
 /* 4Mx8x2 (not implemented yet) */
    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -190,21 +190,21 @@ nand_init(void)
 static u8 Get_PLD_ID(void)
 {
 	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-	
+
 	return(pld->ID);
 }

 static u8 Get_PLD_BOARD(void)
 {
 	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-	
+
 	return(pld->BOARD);
 }

 static u8 Get_PLD_SDRAM(void)
 {
 	VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-	
+
 	return(pld->SDRAM);
 }

@@ -253,7 +253,7 @@ static ulong Get_SDRAM_ChipSize(void)
 		case 2: return  8 * (1024*1024);
 		case 3: return  8 * (1024*1024);
 		default: return 0;
-	}	
+	}
 }
 static const char * Get_SDRAM_ChipGeom(void)
 {
@@ -339,10 +339,10 @@ int overwrite_console(void)
 * Print VCMA9 Info
 ************************************************************************/
 void print_vcma9_info(void)
-{	
+{
 	unsigned char s[50];
 	int i;
-	
+
 	if ((i = getenv_r("serial#", s, 32)) < 0) {
 		puts ("### No HW ID - assuming VCMA9");
 		printf("i %d", i*24);
--- a/board/omap1610inn/flash.c
+++ b/board/omap1610inn/flash.c
@@ -54,7 +54,6 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 #define mb() __asm__ __volatile__ ("" : : : "memory")


-
 /* Flash Organization Structure */
 typedef struct OrgDef {
 	unsigned int sector_number;
@@ -240,8 +239,6 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 }


-
-
 /* unprotects a sector for write and erase
 * on some intel parts, this unprotects the entire chip, but it
 * wont hurt to call this additional times per sector...
@@ -298,8 +295,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	}


-
-
 	start = get_timer (0);
 	last = start;

@@ -326,7 +321,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 			while (((status =
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
-					if (get_timer_masked () > 
+					if (get_timer_masked () >
 					CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
--- a/board/omap1610inn/platform.S
+++ b/board/omap1610inn/platform.S
@@ -132,8 +132,6 @@ watch2Wait:
 	bne	watch2Wait


-
-
 	/* Set memory timings corresponding to the new clock speed */

 	/* Check execution location to determine current execution location
@@ -275,7 +273,7 @@ REG_ARM_CKCTL:			/* 16 bits */
 REG_ARM_IDLECT3:		/* 16 bits */
 	.word 0xfffece24
 REG_ARM_IDLECT2:		/* 16 bits */
-	.word 0xfffece08        
+	.word 0xfffece08
 REG_ARM_IDLECT1:		/* 16 bits */
 	.word 0xfffece04

@@ -293,7 +291,7 @@ REG_WSPRDOG:
 	.word 0xfffeb048
 /* watchdog write pending */
 REG_WWPSDOG:
-	.word 0xfffeb034 
+	.word 0xfffeb034

 WSPRDOG_VAL1:
 	.word 0x0000aaaa
@@ -342,7 +340,7 @@ REG_WATCHDOG:

 /* 96 MHz Samsung Mobile DDR */
 SDRAM_CONFIG_VAL:
-	.word 0x001200f4 
+	.word 0x001200f4

 DLL_LRD_CONTROL_VAL:
 	.word 0x00800002
--- a/board/omap1610inn/u-boot.lds
+++ b/board/omap1610inn/u-boot.lds
@@ -39,11 +39,11 @@ SECTIONS
 	.data : { *(.data) }
 	. = ALIGN(4);
 	.got : { *(.got) }
-	
+
 	__u_boot_cmd_start = .;
 	.u_boot_cmd : { *(.u_boot_cmd) }
 	__u_boot_cmd_end = .;
-	
+
 	armboot_end_data = .;
 	. = ALIGN(4);
 	.bss : { *(.bss) }
--- a/board/sacsng/sacsng.c
+++ b/board/sacsng/sacsng.c
@@ -533,11 +533,11 @@ int misc_init_r(void)
 	setenv("Daq128xSampling", "1");
    }

-    /* 
-     * Display the ADC/DAC clocking information 
+    /*
+     * Display the ADC/DAC clocking information
     */
    if (!quiet) {
-        Daq_Display_Clocks();
+	Daq_Display_Clocks();
    }

    /*
@@ -572,9 +572,9 @@ int misc_init_r(void)
     * 3) Write the I2C address to register 6
     * 4) Enable address matching by setting the MSB in register 7
     */
-    
+
    if (!quiet) {
-        printf("Initializing the ADC...\n");
+	printf("Initializing the ADC...\n");
    }
    udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */

@@ -720,7 +720,7 @@ int misc_init_r(void)
    I2C_TRISTATE;

    if (!quiet) {
-        printf("\n");
+	printf("\n");
    }

 #ifdef CONFIG_ETHER_LOOPBACK_TEST
@@ -795,14 +795,14 @@ void show_boot_progress (int status)
    if(status > 0) {
 	last_boot_progress = status;
    } else {
-        /* 
+	/*
 	 * If a specific failure code is given, flash this code
 	 * else just use the last success code we've seen
 	 */
 	if(status < -1)
 	    last_boot_progress = -status;
-	
-	/* 
+
+	/*
 	 * Flash this code 5 times
 	 */
 	for(j=0; j<5; j++) {
@@ -813,15 +813,15 @@ void show_boot_progress (int status)
 	    status_led_set(STATUS_LED_RED, STATUS_LED_ON);
 	    flash_code(last_boot_progress, 5, 3);

-	    /* 
-	     * Delay 5 seconds between repetitions, 
-	     * with the fault LED blinking 
+	    /*
+	     * Delay 5 seconds between repetitions,
+	     * with the fault LED blinking
 	     */
 	    for(i=0; i<5; i++) {
-	    	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
-	    	udelay(500000);
-	    	status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-	    	udelay(500000);
+		status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+		udelay(500000);
+		status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+		udelay(500000);
 	    }
 	}

--- a/board/sl8245/sl8245.c
+++ b/board/sl8245/sl8245.c
@@ -92,4 +92,3 @@ void pci_init_board(void)
 {
 	pci_mpc824x_init(&hose);
 }
-
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -368,8 +368,8 @@ long int initdram (int board_type)
 	memctl->memc_or5 = CFG_OR5_ISP1362;
 	memctl->memc_br5 = CFG_BR5_ISP1362;
 #endif							/* CONFIG_ISP1362_USB */
-	    
-	    
+
+
 	return (size_b0 + size_b1);
 }

--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -105,14 +105,14 @@ struct flash_layout
 #define AU_FL_APP_ND		0x005BFFFF
 #define AU_FL_DISK_ST		0x005C0000
 #define AU_FL_DISK_ND		0x00FFFFFF
-#else						/*  8 MB Flash, 16 MB RAM */
+#else						/*  8 MB Flash, 32 MB RAM */
 #define AU_FL_FIRMWARE_ST	0x00000000
-#define AU_FL_FIRMWARE_ND	0x0003FFFF
-#define AU_FL_KERNEL_ST		0x00040000
-#define AU_FL_KERNEL_ND		0x0011FFFF
-#define AU_FL_APP_ST		0x00120000
-#define AU_FL_APP_ND		0x003FFFFF
-#define AU_FL_DISK_ST		0x00400000
+#define AU_FL_FIRMWARE_ND	0x0005FFFF
+#define AU_FL_KERNEL_ST		0x00060000
+#define AU_FL_KERNEL_ND		0x0013FFFF
+#define AU_FL_APP_ST		0x00140000
+#define AU_FL_APP_ND		0x0067FFFF
+#define AU_FL_DISK_ST		0x00680000
 #define AU_FL_DISK_ND		0x007DFFFF
 #define AU_FL_VFD_ST		0x007E0000
 #define AU_FL_VFD_ND		0x007FFFFF
@@ -183,11 +183,9 @@ struct flash_layout aufl_layout[AU_MAXFILES - 3] = { \
 #define FIDX_TO_LIDX(idx) ((idx) - 2)

 /* where to load files into memory */
-#define LOAD_ADDR ((unsigned char *)0x0C100100)
-/* where to build strings in memory - 256 bytes should be enough */
-#define STRING_ADDR ((char *)0x0C100000)
-/* the disk is the largest image */
-#define MAX_LOADSZ ausize[IDX_DISK]
+#define LOAD_ADDR ((unsigned char *)0x0C100000)
+/* the app is the largest image */
+#define MAX_LOADSZ ausize[IDX_APP]

 /* externals */
 extern int fat_register_device(block_dev_desc_t *, int);
@@ -199,10 +197,14 @@ extern int i2c_write (uchar, uint, int , uchar* , int);
 extern int trab_vfd (ulong);
 extern int transfer_pic(unsigned char, unsigned char *, int, int);
 #endif
+extern int flash_sect_erase(ulong, ulong);
+extern int flash_sect_protect (int, ulong, ulong);
+extern int flash_write (uchar *, ulong, ulong);
 /* change char* to void* to shutup the compiler */
 extern int i2c_write_multiple (uchar, uint, int, void *, int);
 extern int i2c_read_multiple (uchar, uint, int, void *, int);
 extern block_dev_desc_t *get_dev (char*, int);
+extern int u_boot_hush_start(void);

 int
 au_check_valid(int idx, long nbytes)
@@ -222,7 +224,7 @@ au_check_valid(int idx, long nbytes)
 #endif
 	if (ntohl(hdr->ih_magic) != IH_MAGIC ||
 	    hdr->ih_arch != IH_CPU_ARM ||
-	    nbytes < ntohl(hdr->ih_size))
+	    nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size)))
 	{
 		printf ("Image %s bad MAGIC or ARCH or SIZE\n", aufile[idx]);
 		return -1;
@@ -254,9 +256,11 @@ au_check_valid(int idx, long nbytes)
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
-	if ((idx == IDX_DISK || idx == IDX_APP)
-		&& (hdr->ih_type != IH_TYPE_RAMDISK))
-	{
+	if ((idx == IDX_DISK) && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
+		printf ("Image %s wrong type\n", aufile[idx]);
+		return -1;
+	}
+	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK)) {
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
@@ -269,8 +273,14 @@ au_check_valid(int idx, long nbytes)
 	/* special case for prepare.img */
 	if (idx == IDX_PREPARE)
 		return 0;
-	/* check the size does not exceed space in flash */
-	if ((ausize[idx] != 0) && (ausize[idx] < ntohl(hdr->ih_size))) {
+	/* recycle checksum */
+	checksum = ntohl(hdr->ih_size);
+	/* for kernel and app the image header must also fit into flash */
+	if (idx != IDX_DISK)
+		checksum += sizeof(*hdr);
+	/* check the size does not exceed space in flash. HUSH scripts */
+	/* all have ausize[] set to 0 */
+	if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
 		printf ("Image %s is bigger than FLASH\n", aufile[idx]);
 		return -1;
 	}
@@ -297,13 +307,12 @@ au_check_valid(int idx, long nbytes)
 #define POWER_OFF (1 << 1)

 int
-au_do_update(int idx, long sz, int repeat)
+au_do_update(int idx, long sz)
 {
 	image_header_t *hdr;
 	char *addr;
 	long start, end;
-	char *strbuf = STRING_ADDR;
-	int off;
+	int off, rc;
 	uint nbytes;

 	hdr = (image_header_t *)LOAD_ADDR;
@@ -313,9 +322,12 @@ au_do_update(int idx, long sz, int repeat)

 	/* execute a script */
 	if (hdr->ih_type == IH_TYPE_SCRIPT) {
-		addr = (char *)((char *)hdr + sizeof(*hdr) + 8);
-		parse_string_outer(addr,
-			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+		addr = (char *)((char *)hdr + sizeof(*hdr));
+		/* stick a NULL at the end of the script, otherwise */
+		/* parse_string_outer() runs off the end. */
+		addr[ntohl(hdr->ih_size)] = 0;
+		addr += 8;
+		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
 		return 0;
 	}

@@ -331,25 +343,17 @@ au_do_update(int idx, long sz, int repeat)
 		start = aufl_layout[1].start;
 		end = aufl_layout[1].end;
 #endif
-		debug ("protect off %lx %lx\n", start, end);
-		sprintf(strbuf, "protect off %lx %lx\n", start, end);
-		parse_string_outer(strbuf,
-			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+		flash_sect_protect(0, start, end);
 	}

 	/*
-	 * erase the address range. Multiple erases seem to cause
-	 * problems.
+	 * erase the address range.
 	 */
-	if (repeat == 0) {
-		debug ("erase %lx %lx\n", start, end);
-		sprintf(strbuf, "erase %lx %lx\n", start, end);
-		parse_string_outer(strbuf,
-			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
-	}
+	debug ("flash_sect_erase(%lx, %lx);\n", start, end);
+	flash_sect_erase(start, end);
 	wait_ms(100);
-	/* strip the header - except for the kernel */
-	if (idx == IDX_FIRMWARE || idx == IDX_DISK || idx == IDX_APP) {
+	/* strip the header - except for the kernel and app */
+	if (idx == IDX_FIRMWARE || idx == IDX_DISK) {
 		addr = (char *)((char *)hdr + sizeof(*hdr));
 #ifdef AU_UPDATE_TEST
 		/* copy it to where Linux goes */
@@ -365,10 +369,12 @@ au_do_update(int idx, long sz, int repeat)
 	}

 	/* copy the data from RAM to FLASH */
-	debug ("cp.b %p %lx %x\n", addr, start, nbytes);
-	sprintf(strbuf, "cp.b %p %lx %x\n", addr, start, nbytes);
-	parse_string_outer(strbuf,
-		FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+	debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
+	rc = flash_write(addr, start, nbytes);
+	if (rc != 0) {
+		printf("Flashing failed due to error %d\n", rc);
+		return -1;
+	}

 	/* check the dcrc of the copy */
 	if (crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)) != ntohl(hdr->ih_dcrc)) {
@@ -378,12 +384,8 @@ au_do_update(int idx, long sz, int repeat)

 	/* protect the address range */
 	/* this assumes that ONLY the firmware is protected! */
-	if (idx == IDX_FIRMWARE) {
-		debug ("protect on %lx %lx\n", start, end);
-		sprintf(strbuf, "protect on %lx %lx\n", start, end);
-		parse_string_outer(strbuf,
-			FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
-	}
+	if (idx == IDX_FIRMWARE)
+		flash_sect_protect(1, start, end);
 	return 0;
 }

@@ -485,42 +487,60 @@ do_auto_update(void)
 	 * now check whether start and end are defined using environment
 	 * variables.
 	 */
-	start = end = 0;
+	start = -1;
+	end = 0;
 	env = getenv("firmware_st");
 	if (env != NULL)
 		start = simple_strtoul(env, NULL, 16);
 	env = getenv("firmware_nd");
 	if (env != NULL)
 		end = simple_strtoul(env, NULL, 16);
-	if (start && end && end > start)
+	if (start >= 0 && end && end > start) {
 		ausize[IDX_FIRMWARE] = (end + 1) - start;
-	start = end = 0;
+		aufl_layout[0].start = start;
+		aufl_layout[0].end = end;
+	}
+	start = -1;
+	end = 0;
 	env = getenv("kernel_st");
 	if (env != NULL)
 		start = simple_strtoul(env, NULL, 16);
 	env = getenv("kernel_nd");
 	if (env != NULL)
 		end = simple_strtoul(env, NULL, 16);
-	if (start && end && end > start)
+	if (start >= 0 && end && end > start) {
 		ausize[IDX_KERNEL] = (end + 1) - start;
-	start = end = 0;
+		aufl_layout[1].start = start;
+		aufl_layout[1].end = end;
+	}
+	start = -1;
+	end = 0;
 	env = getenv("app_st");
 	if (env != NULL)
 		start = simple_strtoul(env, NULL, 16);
 	env = getenv("app_nd");
 	if (env != NULL)
 		end = simple_strtoul(env, NULL, 16);
-	if (start && end && end > start)
+	if (start >= 0 && end && end > start) {
 		ausize[IDX_APP] = (end + 1) - start;
-	start = end = 0;
+		aufl_layout[2].start = start;
+		aufl_layout[2].end = end;
+	}
+	start = -1;
+	end = 0;
 	env = getenv("disk_st");
 	if (env != NULL)
 		start = simple_strtoul(env, NULL, 16);
 	env = getenv("disk_nd");
 	if (env != NULL)
 		end = simple_strtoul(env, NULL, 16);
-	if (start && end && end > start)
+	if (start >= 0 && end && end > start) {
 		ausize[IDX_DISK] = (end + 1) - start;
+		aufl_layout[3].start = start;
+		aufl_layout[3].end = end;
+	}
+	/* make certain that HUSH is runnable */
+	u_boot_hush_start();
 	/* make sure that we see CTRL-C and save the old state */
 	old_ctrlc = disable_ctrlc(0);

@@ -564,7 +584,7 @@ do_auto_update(void)
 		cnt = 0;
 		got_ctrlc = 0;
 		do {
-			res = au_do_update(i, sz, cnt);
+			res = au_do_update(i, sz);
 			/* let the user break out of the loop */
 			if (ctrlc() || had_ctrlc()) {
 				clear_ctrlc();
@@ -585,6 +605,9 @@ do_auto_update(void)
 		 */
 		if (got_ctrlc == 0)
 			au_update_eeprom(i);
+		else
+			/* enable the power switch */
+			*CPLD_VFD_BK &= ~POWER_OFF;
 	}
 	usb_stop();
 	/* restore the old state */
--- a/board/trab/cmd_trab.c
+++ b/board/trab/cmd_trab.c
--- a/board/trab/memsetup.S
+++ b/board/trab/memsetup.S
@@ -48,8 +48,8 @@
 #define BWSCON 0x14000000

 /* Bank0 */
-#define B0_Tacs	0x0	/* 0 clk */
-#define B0_Tcos	0x0	/* 0 clk */
+#define B0_Tacs	0x3	/* 4 clk */
+#define B0_Tcos	0x3	/* 4 clk */
 #define B0_Tacc	0x7	/* 14 clk */
 #define B0_Tcoh	0x0	/* 0 clk */
 #define B0_Tah	0x0	/* 0 clk */
@@ -104,12 +104,12 @@
 #ifndef CONFIG_RAM_16MB		/* 32 MB RAM */
 /* Bank6 */
 #define	B6_MT	0x3	/* SDRAM */
-#define	B6_Trcd	0x1	/* 3clk */
+#define	B6_Trcd	0x0	/* 2clk */
 #define	B6_SCAN	0x1	/* 9 bit */

 /* Bank7 */
 #define	B7_MT	0x3	/* SDRAM */
-#define	B7_Trcd	0x1	/* 3clk */
+#define	B7_Trcd	0x0	/* 2clk */
 #define	B7_SCAN	0x1	/* 9 bit */
 #else	/* CONFIG_RAM_16MB	=  16 MB RAM */
 /* Bank6 */
@@ -178,5 +178,5 @@ SMRDATA:
 #else	/* CONFIG_RAM_16MB	=  16 MB RAM */
 	.word	0x17	/* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
 #endif	/* CONFIG_RAM_16MB */
-	.word	0x30	/* MRSR6, CL=3clk */
-	.word	0x30	/* MRSR7 */
+	.word	0x20	/* MRSR6, CL=2clk */
+	.word	0x20	/* MRSR7 */
--- a/board/trab/rs485.c
+++ b/board/trab/rs485.c
@@ -47,8 +47,8 @@ static void rs485_setbrg (void)
 	unsigned int reg = 0;

 	/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
-        /* reg = (33000000 / (16 * gd->baudrate)) - 1; */
-        reg = (33000000 / (16 * 38.400)) - 1;
+	/* reg = (33000000 / (16 * gd->baudrate)) - 1; */
+	reg = (33000000 / (16 * 38400)) - 1;

 	/* FIFO enable, Tx/Rx FIFO clear */
 	uart->UFCON = 0x07;
@@ -67,18 +67,18 @@ static void rs485_setbrg (void)

 static void rs485_cfgio (void)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

-        gpio->PFCON &= ~(0x3 << 2);
-        gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */
+	gpio->PFCON &= ~(0x3 << 2);
+	gpio->PFCON |=  (0x2 << 2); /* configure GPF1 as RXD1 */

-        gpio->PFCON &= ~(0x3 << 6);
-        gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */
+	gpio->PFCON &= ~(0x3 << 6);
+	gpio->PFCON |=  (0x2 << 6); /* configure GPF3 as TXD1 */

-        gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
-        gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */
+	gpio->PFUP |= (1 << 1); /* disable pullup on GPF1 */
+	gpio->PFUP |= (1 << 3); /* disable pullup on GPF3 */

-        gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
+	gpio->PACON &= ~(1 << 11); /* set GPA11 (RS485_DE) to output */
 }

 /*
@@ -88,8 +88,8 @@ static void rs485_cfgio (void)
 */
 int rs485_init (void)
 {
-        rs485_cfgio ();
-        rs485_setbrg ();
+	rs485_cfgio ();
+	rs485_setbrg ();

 	return (0);
 }
@@ -168,13 +168,13 @@ static void set_rs485re(unsigned char rs485re_state)

 static void set_rs485de(unsigned char rs485de_state)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

-        /* This is on PORT A bit 11 */
-        if(rs485de_state)
-                gpio->PADAT |= (1 << 11);
-        else
-                gpio->PADAT &= ~(1 << 11);
+	/* This is on PORT A bit 11 */
+	if(rs485de_state)
+		gpio->PADAT |= (1 << 11);
+	else
+		gpio->PADAT &= ~(1 << 11);
 }


--- a/board/trab/trab_fkt.c
+++ b/board/trab/trab_fkt.c
--- a/board/trab/tsc2000.c
+++ b/board/trab/tsc2000.c
@@ -38,7 +38,7 @@ void spi_init(void)
 	int i;

 	/* Configure I/O ports. */
- 	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+	gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
 	gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
 	gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
 	gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
@@ -48,7 +48,7 @@ void spi_init(void)
 	spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
 	spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
 	spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
-                                    CPHA=1 */
+				    CPHA=1 */

 	/* Dummy byte ensures clock to be low. */
 	for (i = 0; i < 10; i++) {
@@ -73,7 +73,7 @@ void tsc2000_write(unsigned short reg, unsigned short data)

 	SET_CS_TOUCH();
 	command = reg;
-        spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
 	spi->ch[0].SPTDAT = (command & 0x00FF);
 	spi_wait_transmit_done();
@@ -94,12 +94,12 @@ unsigned short tsc2000_read (unsigned short reg)
 	SET_CS_TOUCH();
 	command = 0x8000 | reg;

-        spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+	spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
 	spi_wait_transmit_done();
 	spi->ch[0].SPTDAT = (command & 0x00FF);
 	spi_wait_transmit_done();

-        spi->ch[0].SPTDAT = 0xFF;
+	spi->ch[0].SPTDAT = 0xFF;
 	spi_wait_transmit_done();
 	data = spi->ch[0].SPRDAT;
 	spi->ch[0].SPTDAT = 0xFF;
@@ -112,7 +112,7 @@ unsigned short tsc2000_read (unsigned short reg)

 void tsc2000_set_mux (unsigned int channel)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

 	CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
 	CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
@@ -189,7 +189,7 @@ void tsc2000_set_mux (unsigned int channel)

 void tsc2000_set_range (unsigned int range)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

 	switch (range) {
 	case 1:
@@ -216,8 +216,8 @@ u16 tsc2000_read_channel (unsigned int channel)
 	udelay(3 * TSC2000_DELAY_BASE);

 	tsc2000_write(TSC2000_REG_ADC, 0x2036);
-        adc_wait_conversion_done ();
-        res = tsc2000_read(TSC2000_REG_AUX1);
+	adc_wait_conversion_done ();
+	res = tsc2000_read(TSC2000_REG_AUX1);
 	return res;
 }

@@ -225,36 +225,36 @@ u16 tsc2000_read_channel (unsigned int channel)
 s32 tsc2000_contact_temp (void)
 {
 	long adc_pt1000, offset;
-        long u_pt1000;
+	long u_pt1000;
 	long contact_temp;


-        tsc2000_reg_init ();
+	tsc2000_reg_init ();
 	tsc2000_set_range (3);

-        adc_pt1000 = tsc2000_read_channel (14);
-        debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+	adc_pt1000 = tsc2000_read_channel (14);
+	debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);

-        offset = tsc2000_read_channel (15);
-        debug ("read channel 15 (offset): %ld\n", offset);
+	offset = tsc2000_read_channel (15);
+	debug ("read channel 15 (offset): %ld\n", offset);

-        /*
-         * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
-         * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
-         * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
-         * error correction Values err_vref and err_amp3 are assumed as 0 in
-         * u-boot, because this could cause only a very small error (< 1%).
-         */
-        u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
-        debug ("u_pt1000: %ld\n", u_pt1000);
+	/*
+	 * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+	 * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+	 * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+	 * error correction Values err_vref and err_amp3 are assumed as 0 in
+	 * u-boot, because this could cause only a very small error (< 1%).
+	 */
+	u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+	debug ("u_pt1000: %ld\n", u_pt1000);

-        if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
-                                &contact_temp) == -1) {
-                printf ("%s: error interpolating PT1000 vlaue\n",
-                         __FUNCTION__);
-                return (-1000);
-        }
-        debug ("contact_temp: %ld\n", contact_temp);
+	if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+				&contact_temp) == -1) {
+		printf ("%s: error interpolating PT1000 vlaue\n",
+			 __FUNCTION__);
+		return (-1000);
+	}
+	debug ("contact_temp: %ld\n", contact_temp);

 	return contact_temp;
 }
@@ -262,7 +262,7 @@ s32 tsc2000_contact_temp (void)

 void tsc2000_reg_init (void)
 {
-        S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

 	tsc2000_write(TSC2000_REG_ADC, 0x2036);
 	tsc2000_write(TSC2000_REG_REF, 0x0011);
@@ -315,5 +315,5 @@ int tsc2000_interpolate(long value, long data[][2], long *result)

 void adc_wait_conversion_done(void)
 {
-        while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+	while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
 }
--- a/board/trab/tsc2000.h
+++ b/board/trab/tsc2000.h
@@ -112,7 +112,7 @@
 #define TSC2000_NO_SENSOR	-0x10000

 #define ERROR_BATTERY   220     /* must be adjusted, if R68 is changed on
-                                 * TRAB */
+				 * TRAB */

 void tsc2000_write(unsigned short, unsigned short);
 unsigned short tsc2000_read (unsigned short);
--- a/board/zpc1900/Makefile
+++ b/board/zpc1900/Makefile
@@ -0,0 +1,47 @@
+
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/zpc1900/config.mk
+++ b/board/zpc1900/config.mk
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# ZPC.1900 board
+#
+
+TEXT_BASE = 0xFFF00000
+#TEXT_BASE = 0x03000000
--- a/board/zpc1900/flash.c
+++ b/board/zpc1900/flash.c
@@ -0,0 +1,818 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Modified to work with AMD flashes
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+#undef  DEBUG_FLASH
+/*
+ * This file implements a Common Flash Interface (CFI) driver for U-Boot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ *
+ * TODO
+ *
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
+ * Table (ALT) to determine if protection is available
+ *
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_WRITE_TO_BUFFER       0xE8
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM  0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define AMD_CMD_RESET			0xF0
+#define AMD_CMD_WRITE			0xA0
+#define AMD_CMD_ERASE_START		0x80
+#define AMD_CMD_ERASE_SECTOR		0x30
+
+#define AMD_STATUS_TOGGLE		0x40
+#define AMD_STATUS_ERROR		0x20
+
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT             0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT             0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT         0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT         0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE          0x28
+#define FLASH_OFFSET_BUFFER_SIZE        0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION    0x85
+#define FLASH_OFFSET_INTEL_PROTECTION   0x81
+
+
+#define FLASH_MAN_CFI			0x01000000
+
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+} cfiword_t;
+
+typedef union {
+	volatile unsigned char  *cp;
+	volatile unsigned short *wp;
+	volatile unsigned long  *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uint offset, uchar cmd);
+static void flash_unlock_seq(flash_info_t *info);
+static int flash_isequal(flash_info_t * info, int sect, uint offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uint offset, uchar cmd);
+static int flash_toggle(flash_info_t * info, int sect, uint offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
+#endif
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, uint offset)
+{
+	return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uint offset)
+{
+	uchar *cp;
+	cp = flash_make_addr(info, 0, offset);
+	return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a short word by swapping for ppc format.
+ */
+ushort flash_read_ushort(flash_info_t * info, int sect,  uint offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uint offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
+	    (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size = 0;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(bank_base[i], i);
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, flash_info[i].size, flash_info[i].size << 20);
+		}
+	}
+
+	/* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[0]);
+#endif
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot;
+	int sect;
+
+	if( info->flash_id != FLASH_MAN_CFI) {
+		printf ("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+	if ((s_first < 0) || (s_first > s_last)) {
+		printf ("- no sectors to erase\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) { /* not protected */
+#ifdef INTEL_COMMANDS
+			flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+			flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+#else
+			flash_unlock_seq(info);
+			flash_write_cmd(info, sect, 0x555, AMD_CMD_ERASE_START);
+			flash_unlock_seq(info);
+			flash_write_cmd(info, sect, 0, AMD_CMD_ERASE_SECTOR);
+#endif
+
+			if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
+				rcode = 1;
+			} else
+				printf(".");
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id != FLASH_MAN_CFI) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	printf("CFI conformant FLASH (%d x %d)",
+	       (info->portwidth	 << 3 ), (info->chipwidth  << 3 ));
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+	printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
+	       info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n");
+		printf (" %08lX%5s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : " "
+			);
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong wp;
+	ulong cp;
+	int aln;
+	cfiword_t cword;
+	int i, rc;
+
+	/* get lower aligned address */
+	wp = (addr & ~(info->portwidth - 1));
+
+	/* handle unaligned start */
+	if((aln = addr - wp) != 0) {
+		cword.l = 0;
+		cp = wp;
+		for(i=0;i<aln; ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+
+		for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+			flash_add_byte(info, &cword, *src++);
+			cnt--;
+			cp++;
+		}
+		for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+			flash_add_byte(info, &cword, (*(uchar *)cp));
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp = cp;
+	}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+	while(cnt >= info->portwidth) {
+		i = info->buffer_size > cnt? cnt: info->buffer_size;
+		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
+			return rc;
+		wp += i;
+		src += i;
+		cnt -=i;
+	}
+#else
+	/* handle the aligned part */
+	while(cnt >= info->portwidth) {
+		cword.l = 0;
+		for(i = 0; i < info->portwidth; i++) {
+			flash_add_byte(info, &cword, *src++);
+		}
+		if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+			return rc;
+		wp += info->portwidth;
+		cnt -= info->portwidth;
+	}
+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	cword.l = 0;
+	for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+		flash_add_byte(info, &cword, *src++);
+		--cnt;
+	}
+	for (; i<info->portwidth; ++i, ++cp) {
+		flash_add_byte(info, & cword, (*(uchar *)cp));
+	}
+
+	return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#ifdef CFG_FLASH_PROTECTION
+
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	int retcode = 0;
+
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
+	if(prot)
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
+	else
+		flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
+
+	if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
+					 prot?"protect":"unprotect")) == 0) {
+
+		info->protect[sector] = prot;
+		/* Intel's unprotect unprotects all locking */
+		if(prot == 0) {
+			int i;
+			for(i = 0 ; i<info->sector_count; i++) {
+				if(info->protect[i])
+					flash_real_protect(info, i, 1);
+			}
+		}
+	}
+
+	return retcode;
+}
+
+#endif /* CFG_FLASH_PROTECTION */
+/*-----------------------------------------------------------------------
+ *  wait for XSR.7 to be set. Time out with an error if it does not.
+ *  This routine does not set the flash to read-array mode.
+ */
+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	ulong start;
+
+	/* Wait for command completion */
+	start = get_timer (0);
+	while (
+#ifdef INTEL_COMMANDS
+		!flash_isset(info, sector, 0, FLASH_STATUS_DONE)
+#else
+		flash_toggle(info, sector, 0, AMD_STATUS_TOGGLE)
+#endif
+	      ) {
+		if (get_timer(start) > info->erase_blk_tout) {
+			printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
+#ifdef INTEL_COMMANDS
+			flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+#else
+			flash_write_cmd(info, sector, 0, AMD_CMD_RESET);
+#endif
+			return ERR_TIMOUT;
+		}
+	}
+	return ERR_OK;
+}
+/*-----------------------------------------------------------------------
+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
+ * This routine sets the flash to read-array mode.
+ */
+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
+{
+	int retcode;
+	retcode = flash_status_check(info, sector, tout, prompt);
+#ifdef INTEL_COMMANDS
+	if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
+		retcode = ERR_INVAL;
+		printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
+		if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
+			printf("Command Sequence Error.\n");
+		} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
+			printf("Block Erase Error.\n");
+		        retcode = ERR_NOT_ERASED;
+		} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
+			printf("Locking Error\n");
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
+			printf("Block locked.\n");
+			retcode = ERR_PROTECTED;
+		}
+		if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
+			printf("Vpp Low Error.\n");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
+#endif
+	return retcode;
+}
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cword->c = c;
+		break;
+	case FLASH_CFI_16BIT:
+		cword->w = (cword->w << 8) | c;
+		break;
+	case FLASH_CFI_32BIT:
+		cword->l = (cword->l << 8) | c;
+	}
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+	int i;
+	uchar *cp = (uchar *)cmdbuf;
+	for(i=0; i< info->portwidth; i++)
+		*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uint offset, uchar cmd)
+{
+
+	volatile cfiptr_t addr;
+	cfiword_t cword;
+	addr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		*addr.cp = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		*addr.wp = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		*addr.lp = cword.l;
+		break;
+	}
+}
+
+static void flash_unlock_seq(flash_info_t *info)
+{
+	flash_write_cmd(info, 0, 0x555, 0xAA);
+	flash_write_cmd(info, 0, 0x2AA, 0x55);
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uint offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = (cptr.cp[0] == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = (cptr.wp[0] == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = (cptr.lp[0] == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uint offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) == cword.l);
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_toggle(flash_info_t * info, int sect, uint offset, uchar cmd)
+{
+	cfiptr_t cptr;
+	cfiword_t cword;
+	int retval;
+	cptr.cp = flash_make_addr(info, sect, offset);
+	flash_make_cmd(info, cmd, &cword);
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
+		break;
+	case FLASH_CFI_16BIT:
+		retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
+		break;
+	case FLASH_CFI_32BIT:
+		retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
+		break;
+	default:
+		retval = 0;
+		break;
+	}
+	return retval;
+}
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+	for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+	    info->portwidth <<= 1) {
+		for(info->chipwidth =FLASH_CFI_BY8;
+		    info->chipwidth <= info->portwidth;
+		    info->chipwidth <<= 1) {
+			flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+			flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+			if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+			   flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+				return 1;
+		}
+	}
+	return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ *
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+	flash_info_t * info = &flash_info[banknum];
+	int i, j;
+	int sect_cnt;
+	unsigned long sector;
+	unsigned long tmp;
+	int size_ratio;
+	uchar num_erase_regions;
+	int  erase_region_size;
+	int  erase_region_count;
+
+	info->start[0] = base;
+
+	if(flash_detect_cfi(info)){
+		size_ratio = info->portwidth / info->chipwidth;
+		num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH
+		printf("found %d erase regions\n", num_erase_regions);
+#endif
+		sect_cnt = 0;
+		sector = base;
+		for(i = 0 ; i < num_erase_regions; i++) {
+			if(i > NUM_ERASE_REGIONS) {
+				printf("%d erase regions found, only %d used\n",
+				       num_erase_regions, NUM_ERASE_REGIONS);
+				break;
+			}
+			tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+			erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+			tmp >>= 16;
+			erase_region_count = (tmp & 0xffff) +1;
+			for(j = 0; j< erase_region_count; j++) {
+				info->start[sect_cnt] = sector;
+				sector += (erase_region_size * size_ratio);
+				info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+				sect_cnt++;
+			}
+		}
+
+		info->sector_count = sect_cnt;
+		/* multiply the size by the number of chips */
+		info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+		info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
+		info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
+		info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
+		tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
+		info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+		info->flash_id = FLASH_MAN_CFI;
+	}
+
+	flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+	return(info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+
+	cfiptr_t ctladdr;
+	cfiptr_t cptr;
+	int flag;
+
+	ctladdr.cp = flash_make_addr(info, 0, 0);
+	cptr.cp = (uchar *)dest;
+
+
+	/* Check if Flash is (sufficiently) erased */
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		flag = ((cptr.cp[0] & cword.c) == cword.c);
+		break;
+	case FLASH_CFI_16BIT:
+		flag = ((cptr.wp[0] & cword.w) == cword.w);
+		break;
+	case FLASH_CFI_32BIT:
+		flag = ((cptr.lp[0] & cword.l)	== cword.l);
+		break;
+	default:
+		return 2;
+	}
+	if(!flag)
+		return 2;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+#ifdef INTEL_COMMANDS
+	flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+#else
+	flash_unlock_seq(info);
+	flash_write_cmd(info, 0, 0x555, AMD_CMD_WRITE);
+#endif
+
+	switch(info->portwidth) {
+	case FLASH_CFI_8BIT:
+		cptr.cp[0] = cword.c;
+		break;
+	case FLASH_CFI_16BIT:
+		cptr.wp[0] = cword.w;
+		break;
+	case FLASH_CFI_32BIT:
+		cptr.lp[0] = cword.l;
+		break;
+	}
+
+	/* re-enable interrupts if necessary */
+	if(flag)
+		enable_interrupts();
+
+	return flash_full_status_check(info, 0, info->write_tout, "write");
+}
+
+#ifdef CFG_FLASH_USE_BUFFER_WRITE
+
+/* loop through the sectors from the highest address
+ * when the passed address is greater or equal to the sector address
+ * we have a match
+ */
+static int find_sector(flash_info_t *info, ulong addr)
+{
+	int sector;
+	for(sector = info->sector_count - 1; sector >= 0; sector--) {
+		if(addr >= info->start[sector])
+			break;
+	}
+	return sector;
+}
+
+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
+{
+
+	int sector;
+	int cnt;
+	int retcode;
+	volatile cfiptr_t src;
+	volatile cfiptr_t dst;
+
+	src.cp = cp;
+	dst.cp = (uchar *)dest;
+	sector = find_sector(info, dest);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
+	if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
+					 "write to buffer")) == ERR_OK) {
+		switch(info->portwidth) {
+		case FLASH_CFI_8BIT:
+			cnt = len;
+			break;
+		case FLASH_CFI_16BIT:
+			cnt = len >> 1;
+			break;
+		case FLASH_CFI_32BIT:
+			cnt = len >> 2;
+			break;
+		default:
+			return ERR_INVAL;
+			break;
+		}
+		flash_write_cmd(info, sector, 0, (uchar)cnt-1);
+		while(cnt-- > 0) {
+			switch(info->portwidth) {
+			case FLASH_CFI_8BIT:
+				*dst.cp++ = *src.cp++;
+				break;
+			case FLASH_CFI_16BIT:
+				*dst.wp++ = *src.wp++;
+				break;
+			case FLASH_CFI_32BIT:
+				*dst.lp++ = *src.lp++;
+				break;
+			default:
+				return ERR_INVAL;
+				break;
+			}
+		}
+		flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
+		retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
+					     "buffer write");
+	}
+	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
+	return retcode;
+}
+#endif /* CFG_USE_FLASH_BUFFER_WRITE */
--- a/board/zpc1900/u-boot.lds
+++ b/board/zpc1900/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
--- a/board/zpc1900/zpc1900.c
+++ b/board/zpc1900/zpc1900.c
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <i2c.h>
+#include <spd.h>
+#include <miiphy.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB  */
+	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav */
+	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
+	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB  */
+	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC  */
+	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
+	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
+	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
+	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
+	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
+	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
+	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
+	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
+	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
+	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   0,   0,   0,   0,   0,   0   }, /* PA6 */
+	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
+	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
+	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
+	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER  */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV  */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN  */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER  */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL    */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS    */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
+	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
+	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
+	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN  */
+	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
+	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
+	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
+	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN CLSN */
+	/* PC28 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
+	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
+	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC21 */
+	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC20 */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RENA */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT972 MDC */
+	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT972 MDIO */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* PC0 */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD  */
+	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD  */
+	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
+	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
+	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
+	/* PD26 */ {   0,   0,   0,   0,   0,   0   }, /* PD26 */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+#ifdef CFG_NVRAM_ACCESS_ROUTINE
+void *nvram_read(void *dest, long src, size_t count)
+{
+	return memcpy(dest, (const void *)src, count);
+}
+
+void nvram_write(long dest, const void *src, size_t count)
+{
+	vu_char     *p1 = (vu_char *)(CFG_EEPROM + 0x1555);
+	vu_char     *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA);
+	vu_char     *d = (vu_char *)dest;
+	const uchar *s = (const uchar *)src;
+
+	/* Unprotect the EEPROM */
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0x80;
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0x20;
+	udelay(10000);
+
+	/* Write the data to the EEPROM */
+	while (count--) {
+		*d++ = *s++;
+		while (*(d - 1) != *(s - 1))
+			/* wait */;
+	}
+
+	/* Protect the EEPROM */
+	*p1 = 0xAA;
+	*p2 = 0x55;
+	*p1 = 0xA0;
+	udelay(10000);
+}
+#endif /* CFG_NVRAM_ACCESS_ROUTINE */
+
+long int initdram(int board_type)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	vu_char *ramaddr;
+	uchar c = 0xFF;
+	long int msize = CFG_SDRAM_SIZE;
+	uint psdmr = CFG_PSDMR;
+	int i;
+
+	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
+		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+		immap->im_siu_conf.sc_siumcr =
+			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
+			| SIUMCR_LBPC01;
+	}
+
+#ifndef CFG_RAMBOOT
+	immap->im_siu_conf.sc_ppc_acr  = 0x03;
+	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+#ifdef CFG_LSDRAM_BASE
+	/*
+	  Initialise local bus SDRAM only if the pins
+	  are configured as local bus pins and not as PCI.
+	*/
+	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
+		memctl->memc_lsrt  = CFG_LSRT;
+		memctl->memc_or4   = 0xFFC01480;
+		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+		ramaddr = (vu_char *)CFG_LSDRAM_BASE;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
+		for (i = 0; i < 8; i++)
+			*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW;
+		*ramaddr = c;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN;
+	}
+#endif /* CFG_LSDRAM_BASE */
+
+	/* Initialise 60x bus SDRAM */
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or2  = 0xFC0028C0;
+	memctl->memc_br2  = CFG_SDRAM_BASE | 0x00000041;
+	/*
+	 * The mode data for Mode Register Write command must appear on
+	 * the address lines during a mode-set cycle. It is driven by
+	 * the memory controller, in single PowerQUICC II mode,
+	 * according to PSDMR[CL] and PSDMR[BL] fields. In
+	 * 60x-compatible mode, software must drive the correct value on
+	 * the address lines. BL=0 because for 64-bit port size burst
+	 * length must be 4.
+	 */
+	ramaddr = (vu_char *)(CFG_SDRAM_BASE |
+			      ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
+	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	*ramaddr = c;
+	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	/* Return total 60x bus SDRAM size */
+	return msize * 1024 * 1024;
+}
+
+int checkboard(void)
+{
+	vu_char *bcsr = (vu_char *)CFG_BCSR;
+
+	printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
+	return 0;
+}
--- a/common/ACEX1K.c
+++ b/common/ACEX1K.c
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>		/* core U-Boot definitions */
+#include <ACEX1K.h>		/* ACEX device family */
+
+#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
+
+/* Define FPGA_DEBUG to get debug printf's */
+/* #define FPGA_DEBUG */
+
+#ifdef	FPGA_DEBUG
+#define PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+#undef CFG_FPGA_CHECK_BUSY
+#define CFG_FPGA_PROG_FEEDBACK
+
+/* Note: The assumption is that we cannot possibly run fast enough to
+ * overrun the device (the Slave Parallel mode can free run at 50MHz).
+ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
+ * the board config file to slow things down.
+ */
+#ifndef CONFIG_FPGA_DELAY
+#define CONFIG_FPGA_DELAY()
+#endif
+
+#ifndef CFG_FPGA_WAIT
+#define CFG_FPGA_WAIT 100
+#endif
+
+static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize );
+static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
+/* static int ACEX1K_ps_info( Altera_desc *desc ); */
+static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset );
+
+/* ------------------------------------------------------------------------- */
+/* ACEX1K Generic Implementation */
+int ACEX1K_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;
+
+	switch (desc->iface) {
+	case passive_serial:
+		PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
+		ret_val = ACEX1K_ps_load (desc, buf, bsize);
+		break;
+
+		/* Add new interface types here */
+
+	default:
+		printf ("%s: Unsupported interface type, %d\n",
+				__FUNCTION__, desc->iface);
+	}
+
+	return ret_val;
+}
+
+int ACEX1K_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;
+
+	switch (desc->iface) {
+	case passive_serial:
+		PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
+		ret_val = ACEX1K_ps_dump (desc, buf, bsize);
+		break;
+
+		/* Add new interface types here */
+
+	default:
+		printf ("%s: Unsupported interface type, %d\n",
+				__FUNCTION__, desc->iface);
+	}
+
+	return ret_val;
+}
+
+int ACEX1K_info( Altera_desc *desc )
+{
+	return FPGA_SUCCESS;
+}
+
+
+int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+	int ret_val = FPGA_FAIL;	/* assume a failure */
+
+	if (desc->family != Altera_ACEX1K) {
+		printf ("%s: Unsupported family type, %d\n",
+				__FUNCTION__, desc->family);
+		return FPGA_FAIL;
+	} else
+		switch (desc->iface) {
+		case passive_serial:
+			ret_val = ACEX1K_ps_reloc (desc, reloc_offset);
+			break;
+
+		/* Add new interface types here */
+
+		default:
+			printf ("%s: Unsupported interface type, %d\n",
+					__FUNCTION__, desc->iface);
+		}
+
+	return ret_val;
+}
+
+
+/* ------------------------------------------------------------------------- */
+/* ACEX1K Passive Serial Generic Implementation                                  */
+
+static int ACEX1K_ps_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;	/* assume the worst */
+	Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
+	int i;
+
+	PRINTF ("%s: start with interface functions @ 0x%p\n",
+			__FUNCTION__, fn);
+
+	if (fn) {
+		size_t bytecount = 0;
+		unsigned char *data = (unsigned char *) buf;
+		int cookie = desc->cookie;	/* make a local copy */
+		unsigned long ts;		/* timestamp */
+
+		PRINTF ("%s: Function Table:\n"
+				"ptr:\t0x%p\n"
+				"struct: 0x%p\n"
+				"config:\t0x%p\n"
+				"status:\t0x%p\n"
+				"clk:\t0x%p\n"
+				"data:\t0x%p\n"
+				"done:\t0x%p\n\n",
+				__FUNCTION__, &fn, fn, fn->config, fn->status,
+				fn->clk, fn->data, fn->done);
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		printf ("Loading FPGA Device %d (@ %ld)...\n", cookie, ts);
+#endif
+
+		/*
+		 * Run the pre configuration function if there is one.
+		 */
+		if (*fn->pre) {
+			(*fn->pre) (cookie);
+		}
+
+		/* Establish the initial state */
+		(*fn->config) (TRUE, TRUE, cookie);	/* Assert nCONFIG */
+
+		udelay(2);		/* T_cfg > 2us	*/
+
+		/* nSTATUS should be asserted now */
+		(*fn->done) (cookie);
+		if ( !(*fn->status) (cookie) ) {
+			puts ("** nSTATUS is not asserted.\n");
+			(*fn->abort) (cookie);
+			return FPGA_FAIL;
+		}
+
+		(*fn->config) (FALSE, TRUE, cookie);	/* Deassert nCONFIG */
+		udelay(2);		/* T_cf2st1 < 4us	*/
+
+		/* Wait for nSTATUS to be released (i.e. deasserted) */
+		ts = get_timer (0);		/* get current time */
+		do {
+			CONFIG_FPGA_DELAY ();
+			if (get_timer (ts) > CFG_FPGA_WAIT) {	/* check the time */
+				puts ("** Timeout waiting for STATUS to go high.\n");
+				(*fn->abort) (cookie);
+				return FPGA_FAIL;
+			}
+			(*fn->done) (cookie);
+		} while ((*fn->status) (cookie));
+
+		/* Get ready for the burn */
+		CONFIG_FPGA_DELAY ();
+
+		/* Load the data */
+		while (bytecount < bsize) {
+			unsigned char val=0;
+#ifdef CFG_FPGA_CHECK_CTRLC
+			if (ctrlc ()) {
+				(*fn->abort) (cookie);
+				return FPGA_FAIL;
+			}
+#endif
+			/* Altera detects an error if INIT goes low (active)
+			   while DONE is low (inactive) */
+#if 0 /* not yet implemented */
+			if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+				puts ("** CRC error during FPGA load.\n");
+				(*fn->abort) (cookie);
+				return (FPGA_FAIL);
+			}
+#endif
+			val = data [bytecount ++ ];
+			i = 8;
+			do {
+				/* Deassert the clock */
+				(*fn->clk) (FALSE, TRUE, cookie);
+				CONFIG_FPGA_DELAY ();
+				/* Write data */
+				(*fn->data) ( (val & 0x01), TRUE, cookie);
+				CONFIG_FPGA_DELAY ();
+				/* Assert the clock */
+				(*fn->clk) (TRUE, TRUE, cookie);
+				CONFIG_FPGA_DELAY ();
+				val >>= 1;
+				i --;
+			} while (i > 0);
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+			if (bytecount % (bsize / 40) == 0)
+				putc ('.');		/* let them know we are alive */
+#endif
+		}
+
+		CONFIG_FPGA_DELAY ();
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		putc ('\n');			/* terminate the dotted line */
+#endif
+
+	/*
+	 * Checking FPGA's CONF_DONE signal - correctly booted ?
+	 */
+
+	if ( ! (*fn->done) (cookie) ) {
+		puts ("** Booting failed! CONF_DONE is still deasserted.\n");
+		(*fn->abort) (cookie);
+		return (FPGA_FAIL);
+	}
+
+	/*
+	 * "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
+	 */
+
+	for (i = 0; i < 12; i++) {
+		CONFIG_FPGA_DELAY ();
+		(*fn->clk) (TRUE, TRUE, cookie);	/* Assert the clock pin */
+		CONFIG_FPGA_DELAY ();
+		(*fn->clk) (FALSE, TRUE, cookie);	/* Deassert the clock pin */
+	}
+
+	ret_val = FPGA_SUCCESS;
+
+#ifdef CFG_FPGA_PROG_FEEDBACK
+		if (ret_val == FPGA_SUCCESS) {
+			puts ("Done.\n");
+		}
+		else {
+			puts ("Fail.\n");
+		}
+#endif
+	(*fn->post) (cookie);
+
+	} else {
+		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+	}
+
+	return ret_val;
+}
+
+static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+	/* Readback is only available through the Slave Parallel and         */
+	/* boundary-scan interfaces.                                         */
+	printf ("%s: Passive Serial Dumping is unavailable\n",
+			__FUNCTION__);
+	return FPGA_FAIL;
+}
+
+static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+	int ret_val = FPGA_FAIL;	/* assume the worst */
+	Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn =
+			(Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns);
+
+	if (fn) {
+		ulong addr;
+
+		/* Get the relocated table address */
+		addr = (ulong) fn + reloc_offset;
+		fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr;
+
+		if (!fn_r->relocated) {
+
+			if (memcmp (fn_r, fn,
+						sizeof (Altera_ACEX1K_Passive_Serial_fns))
+				== 0) {
+				/* good copy of the table, fix the descriptor pointer */
+				desc->iface_fns = fn_r;
+			} else {
+				PRINTF ("%s: Invalid function table at 0x%p\n",
+						__FUNCTION__, fn_r);
+				return FPGA_FAIL;
+			}
+
+			PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
+					desc);
+
+			addr = (ulong) (fn->pre) + reloc_offset;
+			fn_r->pre = (Altera_pre_fn) addr;
+
+			addr = (ulong) (fn->config) + reloc_offset;
+			fn_r->config = (Altera_config_fn) addr;
+
+			addr = (ulong) (fn->status) + reloc_offset;
+			fn_r->status = (Altera_status_fn) addr;
+
+			addr = (ulong) (fn->done) + reloc_offset;
+			fn_r->done = (Altera_done_fn) addr;
+
+			addr = (ulong) (fn->clk) + reloc_offset;
+			fn_r->clk = (Altera_clk_fn) addr;
+
+			addr = (ulong) (fn->data) + reloc_offset;
+			fn_r->data = (Altera_data_fn) addr;
+
+			addr = (ulong) (fn->abort) + reloc_offset;
+			fn_r->abort = (Altera_abort_fn) addr;
+
+			addr = (ulong) (fn->post) + reloc_offset;
+			fn_r->post = (Altera_post_fn) addr;
+
+			fn_r->relocated = TRUE;
+
+		} else {
+			/* this table has already been moved */
+			/* XXX - should check to see if the descriptor is correct */
+			desc->iface_fns = fn_r;
+		}
+
+		ret_val = FPGA_SUCCESS;
+	} else {
+		printf ("%s: NULL Interface function table!\n", __FUNCTION__);
+	}
+
+	return ret_val;
+
+}
+
+#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
--- a/common/Makefile
+++ b/common/Makefile
@@ -27,7 +27,7 @@ LIB	= libcommon.a

 AOBJS	=

-COBJS	= main.o altera.o bedbug.o \
+COBJS	= main.o ACEX1K.o altera.o bedbug.o \
 	  cmd_autoscript.o \
 	  cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
 	  cmd_cache.o cmd_console.o \
--- a/common/altera.c
+++ b/common/altera.c
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 *
@@ -22,21 +25,14 @@
 *
 */

-/*
- * Note that this is just boilerplate - there is no Altera support yet.
- */
-
-
 /*
 *  Altera FPGA support
 */
 #include <common.h>
-#include <fpga.h>                     /* Generic FPGA support  */
-#include <altera.h>                   /* Altera specific stuff */
+#include <ACEX1K.h>

-#if 0
-#define FPGA_DEBUG
-#endif
+/* Define FPGA_DEBUG to get debug printf's */
+/* #define FPGA_DEBUG */

 #ifdef	FPGA_DEBUG
 #define	PRINTF(fmt,args...)	printf (fmt ,##args)
@@ -46,28 +42,191 @@

 #if (CONFIG_FPGA & CFG_FPGA_ALTERA)

+/* Local Static Functions */
+static int altera_validate (Altera_desc * desc, char *fn);
+
 /* ------------------------------------------------------------------------- */
 int altera_load( Altera_desc *desc, void *buf, size_t bsize )
 {
-	printf( "No support for Altera devices yet.\n" );
-	return FPGA_FAIL;
+	int ret_val = FPGA_FAIL;	/* assume a failure */
+
+	if (!altera_validate (desc, __FUNCTION__)) {
+		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+	} else {
+		switch (desc->family) {
+		case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX1K)
+			PRINTF ("%s: Launching the ACEX1K Loader...\n",
+					__FUNCTION__);
+			ret_val = ACEX1K_load (desc, buf, bsize);
+#else
+			printf ("%s: No support for ACEX1K devices.\n",
+					__FUNCTION__);
+#endif
+			break;
+
+		default:
+			printf ("%s: Unsupported family type, %d\n",
+					__FUNCTION__, desc->family);
+		}
+	}
+
+	return ret_val;
 }

 int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
 {
-	printf( "No support for Altera devices yet.\n" );
-	return FPGA_FAIL;
+	int ret_val = FPGA_FAIL;	/* assume a failure */
+
+	if (!altera_validate (desc, __FUNCTION__)) {
+		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+	} else {
+		switch (desc->family) {
+		case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX)
+			PRINTF ("%s: Launching the ACEX1K Reader...\n",
+					__FUNCTION__);
+			ret_val = ACEX1K_dump (desc, buf, bsize);
+#else
+			printf ("%s: No support for ACEX1K devices.\n",
+					__FUNCTION__);
+#endif
+			break;
+
+		default:
+			printf ("%s: Unsupported family type, %d\n",
+					__FUNCTION__, desc->family);
+		}
+	}
+
+	return ret_val;
 }

 int altera_info( Altera_desc *desc )
 {
-	printf( "No support for Altera devices yet.\n" );
-	return FPGA_FAIL;
+	int ret_val = FPGA_FAIL;
+
+	if (altera_validate (desc, __FUNCTION__)) {
+		printf ("Family:        \t");
+		switch (desc->family) {
+		case Altera_ACEX1K:
+			printf ("ACEX1K\n");
+			break;
+			/* Add new family types here */
+		default:
+			printf ("Unknown family type, %d\n", desc->family);
+		}
+
+		printf ("Interface type:\t");
+		switch (desc->iface) {
+		case passive_serial:
+			printf ("Passive Serial (PS)\n");
+			break;
+		case passive_parallel_synchronous:
+			printf ("Passive Parallel Synchronous (PPS)\n");
+			break;
+		case passive_parallel_asynchronous:
+			printf ("Passive Parallel Asynchronous (PPA)\n");
+			break;
+		case passive_serial_asynchronous:
+			printf ("Passive Serial Asynchronous (PSA)\n");
+			break;
+		case altera_jtag_mode:		/* Not used */
+			printf ("JTAG Mode\n");
+			break;
+			/* Add new interface types here */
+		default:
+			printf ("Unsupported interface type, %d\n", desc->iface);
+		}
+
+		printf ("Device Size:   \t%d bytes\n"
+				"Cookie:        \t0x%x (%d)\n",
+				desc->size, desc->cookie, desc->cookie);
+
+		if (desc->iface_fns) {
+			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
+			switch (desc->family) {
+			case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX1K)
+				ACEX1K_info (desc);
+#else
+				/* just in case */
+				printf ("%s: No support for ACEX1K devices.\n",
+						__FUNCTION__);
+#endif
+				break;
+				/* Add new family types here */
+			default:
+				/* we don't need a message here - we give one up above */
+			}
+		} else {
+			printf ("No Device Function Table.\n");
+		}
+
+		ret_val = FPGA_SUCCESS;
+	} else {
+		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+	}
+
+	return ret_val;
+}
+
+int altera_reloc( Altera_desc *desc, ulong reloc_offset)
+{
+	int ret_val = FPGA_FAIL;	/* assume a failure */
+
+	if (!altera_validate (desc, __FUNCTION__)) {
+		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
+	} else {
+		switch (desc->family) {
+		case Altera_ACEX1K:
+#if (CONFIG_FPGA & CFG_ACEX1K)
+			ret_val = ACEX1K_reloc (desc, reloc_offset);
+#else
+			printf ("%s: No support for ACEX devices.\n",
+					__FUNCTION__);
+#endif
+			break;
+			/* Add new family types here */
+		default:
+			printf ("%s: Unsupported family type, %d\n",
+					__FUNCTION__, desc->family);
+		}
+	}
+
+	return ret_val;
 }

 /* ------------------------------------------------------------------------- */

+static int altera_validate (Altera_desc * desc, char *fn)
+{
+	int ret_val = FALSE;
+
+	if (desc) {
+		if ((desc->family > min_altera_type) &&
+			(desc->family < max_altera_type)) {
+			if ((desc->iface > min_altera_iface_type) &&
+				(desc->iface < max_altera_iface_type)) {
+				if (desc->size) {
+					ret_val = TRUE;
+				} else {
+					printf ("%s: NULL part size\n", fn);
+				}
+			} else {
+				printf ("%s: Invalid Interface type, %d\n",
+					fn, desc->iface);
+			}
+		} else {
+			printf ("%s: Invalid family type, %d\n", fn, desc->family);
+		}
+	} else {
+		printf ("%s: NULL descriptor!\n", fn);
+	}
+
+	return ret_val;
+}

 /* ------------------------------------------------------------------------- */

-#endif  /* CONFIG_FPGA & CFG_FPGA_ALTERA */
+#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -55,7 +55,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_num ("flashoffset",   bd->bi_flashoffset	);
 	print_num ("sramstart",	    bd->bi_sramstart	);
 	print_num ("sramsize",	    bd->bi_sramsize	);
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_E500)
 	print_num ("immr_base",	    bd->bi_immr_base	);
 #endif
 	print_num ("bootflags",	    bd->bi_bootflags	);
@@ -66,13 +66,13 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	print_str ("pci_busfreq",	    strmhz(buf, bd->bi_pci_busfreq));
 #endif
 #else	/* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
 	print_str ("vco",	    strmhz(buf, bd->bi_vco));
 	print_str ("sccfreq",	    strmhz(buf, bd->bi_sccfreq));
 	print_str ("brgfreq",	    strmhz(buf, bd->bi_brgfreq));
 #endif
 	print_str ("intfreq",	    strmhz(buf, bd->bi_intfreq));
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
 	print_str ("cpmfreq",	    strmhz(buf, bd->bi_cpmfreq));
 #endif
 	print_str ("busfreq",	    strmhz(buf, bd->bi_busfreq));
@@ -81,12 +81,19 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
 	}
-#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB)
+#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
+    || (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
 	printf ("\neth1addr    =");
 	for (i=0; i<6; ++i) {
 		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
 	}
 #endif /* CONFIG_PN62 */
+#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
+       printf ("\neth2addr    =");
+       for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
+	}
+#endif
 #ifdef CONFIG_HERMES
 	print_str ("ethspeed",	    strmhz(buf, bd->bi_ethspeed));
 #endif
@@ -95,6 +102,33 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	return 0;
 }

+#elif defined(CONFIG_NIOS) /* NIOS*/
+
+int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	int i;
+	bd_t *bd = gd->bd;
+
+	print_num ("memstart",		(ulong)bd->bi_memstart);
+	print_num ("memsize",		(ulong)bd->bi_memsize);
+	print_num ("flashstart",	(ulong)bd->bi_flashstart);
+	print_num ("flashsize",		(ulong)bd->bi_flashsize);
+	print_num ("flashoffset",	(ulong)bd->bi_flashoffset);
+
+	printf ("ethaddr     =");
+	for (i=0; i<6; ++i) {
+		printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
+	}
+	printf ("\nip_addr     = ");
+	print_IPaddr (bd->bi_ip_addr);
+	printf ("\nbaudrate    = %ld bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
+
 #else /* ! PPC, which leaves MIPS */

 int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
--- a/common/cmd_boot.c
+++ b/common/cmd_boot.c
@@ -59,7 +59,14 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 */
 	argv[0] = (char *)gd;
 #endif
+#if !defined(CONFIG_NIOS)
 	rc = ((ulong (*)(int, char *[]))addr) (--argc, &argv[1]);
+#else
+	/*
+	 * Nios function pointers are address >> 1
+	 */
+	rc = ((ulong (*)(int, char *[]))(addr>>1)) (--argc, &argv[1]);
+#endif
 	if (rc != 0) rcode = 1;

 	printf ("## Application terminated, rc = 0x%lX\n", rc);
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -117,6 +117,9 @@ static boot_os_Fcn do_bootm_linux;
 #else
 extern boot_os_Fcn do_bootm_linux;
 #endif
+#ifdef CONFIG_SILENT_CONSOLE
+static void fixup_silent_linux (void);
+#endif
 static boot_os_Fcn do_bootm_netbsd;
 static boot_os_Fcn do_bootm_rtems;
 #if (CONFIG_COMMANDS & CFG_CMD_ELF)
@@ -235,6 +238,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	if (hdr->ih_arch != IH_CPU_I386)
 #elif defined(__mips__)
 	if (hdr->ih_arch != IH_CPU_MIPS)
+#elif defined(__nios__)
+	if (hdr->ih_arch != IH_CPU_NIOS)
 #else
 # error Unknown CPU type
 #endif
@@ -247,6 +252,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

 	switch (hdr->ih_type) {
 	case IH_TYPE_STANDALONE:	name = "Standalone Application";
+					/* A second argument overwrites the load address */
+					if (argc > 2) {
+						hdr->ih_load = simple_strtoul(argv[2], NULL, 16);
+					}
 					break;
 	case IH_TYPE_KERNEL:		name = "Kernel Image";
 					break;
@@ -347,8 +356,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		/* load (and uncompress), but don't start if "autostart"
 		 * is set to "no"
 		 */
-		if (((s = getenv("autostart")) != NULL) && (strcmp(s,"no") == 0))
+		if (((s = getenv("autostart")) != NULL) && (strcmp(s,"no") == 0)) {
+			char buf[32];
+			sprintf(buf, "%lX", len);
+			setenv("filesize", buf);
 			return 0;
+		}
 		appl = (int (*)(cmd_tbl_t *, int, int, char *[]))ntohl(hdr->ih_ep);
 		(*appl)(cmdtp, flag, argc-1, &argv[1]);
 		return 0;
@@ -368,6 +381,9 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	switch (hdr->ih_os) {
 	default:			/* handled by (original) Linux case */
 	case IH_OS_LINUX:
+#ifdef CONFIG_SILENT_CONSOLE
+	    fixup_silent_linux();
+#endif
 	    do_bootm_linux  (cmdtp, flag, argc, argv,
 			     addr, len_ptr, verify);
 	    break;
@@ -422,6 +438,40 @@ U_BOOT_CMD(
 	"        'arg' can be the address of an initrd image\n"
 );

+#ifdef CONFIG_SILENT_CONSOLE
+static void
+fixup_silent_linux ()
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	char buf[256], *start, *end;
+	char *cmdline = getenv ("bootargs");
+
+	/* Only fix cmdline when requested */
+	if (!(gd->flags & GD_FLG_SILENT))
+		return;
+
+	debug ("before silent fix-up: %s\n", cmdline);
+	if (cmdline) {
+		if ((start = strstr (cmdline, "console=")) != NULL) {
+			end = strchr (start, ' ');
+			strncpy (buf, cmdline, (start - cmdline + 8));
+			if (end)
+				strcpy (buf + (start - cmdline + 8), end);
+			else
+				buf[start - cmdline + 8] = '\0';
+		} else {
+			strcpy (buf, cmdline);
+			strcat (buf, " console=");
+		}
+	} else {
+		strcpy (buf, "console=");
+	}
+
+	setenv ("bootargs", buf);
+	debug ("after silent fix-up: %s\n", buf);
+}
+#endif /* CONFIG_SILENT_CONSOLE */
+
 #ifdef CONFIG_PPC
 static void
 do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
@@ -508,7 +558,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
 		/* convert all clock information to MHz */
 		kbd->bi_intfreq /= 1000000L;
 		kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
 		kbd->bi_cpmfreq /= 1000000L;
 		kbd->bi_brgfreq /= 1000000L;
 		kbd->bi_sccfreq /= 1000000L;
@@ -708,7 +758,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,

 	SHOW_BOOT_PROGRESS (15);

-#ifdef CFG_INIT_RAM_LOCK
+#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
 	unlock_ram_in_cache();
 #endif
 	/*
@@ -1291,4 +1341,3 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int flag,
 }

 #endif /* CONFIG_LYNXKDI */
-
--- a/common/cmd_fat.c
+++ b/common/cmd_fat.c
@@ -37,8 +37,6 @@
 #include <fat.h>


-
-
 block_dev_desc_t *get_dev (char* ifname, int dev)
 {
 #if (CONFIG_COMMANDS & CFG_CMD_IDE)
@@ -74,6 +72,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	long size;
 	unsigned long offset;
 	unsigned long count;
+	char buf [12];
 	block_dev_desc_t *dev_desc=NULL;
 	int dev=0;
 	int part=1;
@@ -107,17 +106,19 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		count = 0;
 	size = file_fat_read (argv[4], (unsigned char *) offset, count);

-	if(size==-1)
+	if(size==-1) {
 		printf("\n** Unable to read \"%s\" from %s %d:%d **\n",argv[4],argv[1],dev,part);
-	else
+	} else {
 		printf ("\n%ld bytes read\n", size);

+		sprintf(buf, "%lX", size);
+		setenv("filesize", buf);
+	}
+
 	return size;
 }


-
-
 U_BOOT_CMD(
 	fatload,	6,	0,	do_fat_fsload,
 	"fatload - load binary file from a dos filesystem\n",
--- a/common/cmd_fdos.c
+++ b/common/cmd_fdos.c
@@ -43,7 +43,7 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
    char *ep;
    int size;
    int rcode = 0;
-    char buf [10];
+    char buf [12];
    int drive = CFG_FDC_DRIVE_NUMBER;

    /* pre-set load_addr */
--- a/common/cmd_flash.c
+++ b/common/cmd_flash.c
@@ -164,6 +164,11 @@ flash_fill_sect_ranges (ulong addr_first, ulong addr_last,
 			sect = s_last[bank];
 			addr_first = (sect == s_end) ? b_end + 1: info->start[sect + 1];
 			(*s_count) += s_last[bank] - s_first[bank] + 1;
+		} else if (s_last[bank] >= 0) {
+			printf("Error: cannot span across banks when they are"
+			       " mapped in reverse order\n");
+			rcode = 1;
+			break;
 		}
 	}

--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -42,8 +42,12 @@
 #ifdef CONFIG_STATUS_LED
 # include <status_led.h>
 #endif
-#ifdef __I386__
+#ifndef __PPC__
 #include <asm/io.h>
+#ifdef __MIPS__
+/* Macros depend on this variable */
+static unsigned long mips_io_port_base = 0;
+#endif
 #endif

 #ifdef CONFIG_SHOW_BOOT_PROGRESS
@@ -65,6 +69,7 @@

 #if (CONFIG_COMMANDS & CFG_CMD_IDE)

+#ifdef CONFIG_IDE_8xx_DIRECT
 /* Timings for IDE Interface
 *
 * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
@@ -101,6 +106,8 @@ static int pio_mode = CFG_PIO_MODE;

 #define PCMCIA_MK_CLKS( t, T ) (( (t) * (T) + 999U ) / 1000U )

+#endif /* CONFIG_IDE_8xx_DIRECT */
+
 /* ------------------------------------------------------------------------- */

 /* Current I/O Device	*/
@@ -116,9 +123,8 @@ ulong ide_bus_offset[CFG_IDE_MAXBUS] = {
 #endif
 };

-#ifdef __PPC__
+
 #define	ATA_CURR_BASE(dev)	(CFG_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
-#endif

 #ifndef CONFIG_AMIGAONEG3SE
 static int	    ide_bus_ok[CFG_IDE_MAXBUS];
@@ -164,9 +170,6 @@ static uchar ide_wait  (int dev, ulong t);

 static void __inline__ ide_outb(int dev, int port, unsigned char val);
 static unsigned char __inline__ ide_inb(int dev, int port);
-#ifdef __PPC__
-static void input_swap_data(int dev, ulong *sect_buf, int words);
-#endif
 static void input_data(int dev, ulong *sect_buf, int words);
 static void output_data(int dev, ulong *sect_buf, int words);
 static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
@@ -180,8 +183,6 @@ ulong atapi_read (int device, ulong blknr, ulong blkcnt, ulong *buffer);

 #ifdef CONFIG_IDE_8xx_DIRECT
 static void set_pcmcia_timing (int pmode);
-#else
-#define set_pcmcia_timing(a)	/* dummy */
 #endif

 /* ------------------------------------------------------------------------- */
@@ -472,9 +473,9 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

 void ide_init (void)
 {
-	DECLARE_GLOBAL_DATA_PTR;

 #ifdef CONFIG_IDE_8xx_DIRECT
+	DECLARE_GLOBAL_DATA_PTR;
 	volatile immap_t *immr = (immap_t *)CFG_IMMR;
 	volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
 #endif
@@ -502,6 +503,7 @@ void ide_init (void)

 	WATCHDOG_RESET();

+#ifdef CONFIG_IDE_8xx_DIRECT
 	/* Initialize PIO timing tables */
 	for (i=0; i <= IDE_MAX_PIO_MODE; ++i) {
 	    pio_config_clk[i].t_setup  = PCMCIA_MK_CLKS(pio_config_ns[i].t_setup,
@@ -518,6 +520,7 @@ void ide_init (void)
 		    pio_config_ns[i].t_length, pio_config_clk[i].t_length,
 		    pio_config_ns[i].t_hold,   pio_config_clk[i].t_hold);
 	}
+#endif /* CONFIG_IDE_8xx_DIRECT */

 	/* Reset the IDE just to be sure.
 	 * Light LED's to show
@@ -528,11 +531,11 @@ void ide_init (void)
 #ifdef CONFIG_IDE_8xx_DIRECT
 	/* PCMCIA / IDE initialization for common mem space */
 	pcmp->pcmc_pgcrb = 0;
-#endif

 	/* start in PIO mode 0 - most relaxed timings */
 	pio_mode = 0;
 	set_pcmcia_timing (pio_mode);
+#endif /* CONFIG_IDE_8xx_DIRECT */

 	/*
 	 * Wait for IDE to get ready.
@@ -763,7 +766,7 @@ ide_outb(int dev, int port, unsigned char val)
 static void __inline__
 ide_outb(int dev, int port, unsigned char val)
 {
-	outb(val, port);
+	outb(val, ATA_CURR_BASE(dev)+port);
 }
 #endif	/* __PPC__ */

@@ -785,7 +788,7 @@ ide_inb(int dev, int port)
 static unsigned char __inline__
 ide_inb(int dev, int port)
 {
-	return inb(port);
+  return inb(ATA_CURR_BASE(dev)+port);
 }
 #endif	/* __PPC__ */

@@ -809,7 +812,13 @@ output_data_short(int dev, ulong *sect_buf, int words)
 	    *pbuf = 0;
 }
 # endif	/* CONFIG_AMIGAONEG3SE */
+#endif /* __PPC_ */

+/* We only need to swap data if we are running on a big endian cpu. */
+/* But Au1x00 cpu:s already swaps data in big endian mode! */
+#if defined(__LITTLE_ENDIAN) || defined(CONFIG_AU1X00)
+#define input_swap_data(x,y,z) input_data(x,y,z)
+#else
 static void
 input_swap_data(int dev, ulong *sect_buf, int words)
 {
@@ -821,9 +830,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
 		*dbuf++ = ld_le16(pbuf);
 	}
 }
-#else	/* ! __PPC__ */
-#define input_swap_data(x,y,z) input_data(x,y,z)
-#endif	/* __PPC__ */
+#endif	/* __LITTLE_ENDIAN || CONFIG_AU1X00 */


 #ifdef __PPC__
@@ -846,7 +853,7 @@ output_data(int dev, ulong *sect_buf, int words)
 static void
 output_data(int dev, ulong *sect_buf, int words)
 {
-	outsw(ATA_DATA_REG, sect_buf, words<<1);
+	outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1);
 }
 #endif	/* __PPC__ */

@@ -870,7 +877,7 @@ input_data(int dev, ulong *sect_buf, int words)
 static void
 input_data(int dev, ulong *sect_buf, int words)
 {
-	insw(ATA_DATA_REG, sect_buf, words << 1);
+	insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1);
 }

 #endif	/* __PPC__ */
@@ -1420,14 +1427,14 @@ input_data_shorts(int dev, ushort *sect_buf, int shorts)
 static void
 output_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-	outsw(ATA_DATA_REG, sect_buf, shorts);
+	outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts);
 }


 static void
 input_data_shorts(int dev, ushort *sect_buf, int shorts)
 {
-	insw(ATA_DATA_REG, sect_buf, shorts);
+	insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, shorts);
 }

 #endif	/* __PPC__ */
--- a/common/console.c
+++ b/common/console.c
@@ -365,10 +365,16 @@ int console_init_f (void)
 	DECLARE_GLOBAL_DATA_PTR;

 	gd->have_console = 1;
+
+#ifdef CONFIG_SILENT_CONSOLE
+	if (getenv("silent") != NULL)
+		gd->flags |= GD_FLG_SILENT;
+#endif
+
 	return (0);
 }

-#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN)
+#if defined(CFG_CONSOLE_IS_IN_ENV) || defined(CONFIG_SPLASH_SCREEN) || defined(CONFIG_SILENT_CONSOLE)
 /* search a device */
 device_t *search_device (int flags, char *name)
 {
@@ -488,8 +494,16 @@ int console_init_r (void)
 	int i, items = ListNumItems (devlist);

 #ifdef CONFIG_SPLASH_SCREEN
-	/* suppress all output if splash screen is enabled */
-	outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+	/* suppress all output if splash screen is enabled and we have
+	   a bmp to display                                            */
+	if (getenv("splashimage") != NULL)
+		outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
+#endif
+
+#ifdef CONFIG_SILENT_CONSOLE
+	/* Suppress all output if "silent" mode requested		*/
+	if (gd->flags & GD_FLG_SILENT)
+		outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
 #endif

 	/* Scan devices looking for input and output devices */
--- a/common/hush.c
+++ b/common/hush.c
@@ -313,7 +313,7 @@ struct variables *top_vars = &shell_ver;
 #else
 static int flag_repeat = 0;
 static int do_repeat = 0;
-static struct variables *top_vars ;
+static struct variables *top_vars = NULL ;
 #endif /*__U_BOOT__ */

 #define B_CHUNK (100)
@@ -3194,13 +3194,15 @@ static void u_boot_hush_reloc(void)

 int u_boot_hush_start(void)
 {
-	top_vars = malloc(sizeof(struct variables));
-	top_vars->name = "HUSH_VERSION";
-	top_vars->value = "0.01";
-	top_vars->next = 0;
-	top_vars->flg_export = 0;
-	top_vars->flg_read_only = 1;
-	u_boot_hush_reloc();
+	if (top_vars == NULL) {
+		top_vars = malloc(sizeof(struct variables));
+		top_vars->name = "HUSH_VERSION";
+		top_vars->value = "0.01";
+		top_vars->next = 0;
+		top_vars->flg_export = 0;
+		top_vars->flg_read_only = 1;
+		u_boot_hush_reloc();
+	}
 	return 0;
 }

--- a/common/lynxkdi.c
+++ b/common/lynxkdi.c
@@ -67,4 +67,3 @@ void lynxkdi_boot ( image_header_t *hdr )
 #endif

 #endif	/* CONFIG_LYNXKDI */
-
--- a/common/main.c
+++ b/common/main.c
@@ -193,6 +193,18 @@ static __inline__ int abortboot(int bootdelay)
 {
 	int abort = 0;

+#ifdef CONFIG_SILENT_CONSOLE
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		if (gd->flags & GD_FLG_SILENT) {
+			/* Restore serial console */
+			console_assign (stdout, "serial");
+			console_assign (stderr, "serial");
+		}
+	}
+#endif
+
 #ifdef CONFIG_MENUPROMPT
 	printf(CONFIG_MENUPROMPT, bootdelay);
 #else
@@ -207,13 +219,13 @@ static __inline__ int abortboot(int bootdelay)
 	if (bootdelay >= 0) {
 		if (tstc()) {	/* we got a key press	*/
 			(void) getc();  /* consume input	*/
-			printf ("\b\b\b 0\n");
-			return 1; 	/* don't auto boot	*/
+			printf ("\b\b\b 0");
+			abort = 1; 	/* don't auto boot	*/
 		}
 	}
 #endif

-	while (bootdelay > 0) {
+	while ((bootdelay > 0) && (!abort)) {
 		int i;

 		--bootdelay;
@@ -237,6 +249,21 @@ static __inline__ int abortboot(int bootdelay)

 	putc ('\n');

+#ifdef CONFIG_SILENT_CONSOLE
+	{
+		DECLARE_GLOBAL_DATA_PTR;
+
+		if (abort) {
+			/* permanently enable normal console output */
+			gd->flags &= ~(GD_FLG_SILENT);
+		} else if (gd->flags & GD_FLG_SILENT) {
+			/* Restore silent console */
+			console_assign (stdout, "nulldev");
+			console_assign (stderr, "nulldev");
+		}
+	}
+#endif
+
 	return abort;
 }
 # endif	/* CONFIG_AUTOBOOT_KEYED */
--- a/common/miiphyutil.c
+++ b/common/miiphyutil.c
@@ -169,4 +169,27 @@ int miiphy_duplex (unsigned char addr)
 	}
 }

+#ifdef CFG_FAULT_ECHO_LINK_DOWN
+/*****************************************************************************
+ *
+ * Determine link status
+ */
+int miiphy_link (unsigned char addr)
+{
+	unsigned short reg;
+
+	if (miiphy_read (addr, PHY_BMSR, &reg)) {
+		printf ("PHY_BMSR read failed, assuming no link\n");
+		return (0);
+	}
+
+	/* Determine if a link is active */
+	if ((reg & PHY_BMSR_LS) != 0) {
+		return (1);
+	} else {
+		return (0);
+	}
+}
+#endif
+
 #endif /* CONFIG_MII || (CONFIG_COMMANDS & CFG_CMD_MII) */
--- a/cpu/arm920t/usb_ohci.c
+++ b/cpu/arm920t/usb_ohci.c
@@ -51,8 +51,6 @@
 #define	OHCI_CONTROL_INIT \
 	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE

-#define OHCI_UNLINK_TIMEOUT	(CFG_HZ / 10)
-
 #define readl(a) (*((vu_long *)(a)))
 #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))

@@ -85,6 +83,10 @@ struct ohci_hcca *phcca;
 struct ohci_device ohci_dev;
 /* urb_priv */
 urb_priv_t urb_priv;
+/* RHSC flag */
+int got_rhsc;
+/* device which was disconnected */
+struct usb_device *devgone;

 /*-------------------------------------------------------------------------*/

@@ -155,14 +157,14 @@ static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffe

 	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
 			str,
-		 	sohci_get_current_frame_number (dev),
-		 	usb_pipedevice (pipe),
-		 	usb_pipeendpoint (pipe),
-		 	usb_pipeout (pipe)? 'O': 'I',
-		 	usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
-		 		(usb_pipecontrol (pipe)? "CTRL": "BULK"),
-		 	purb->actual_length,
-		 	transfer_len, dev->status);
+			sohci_get_current_frame_number (dev),
+			usb_pipedevice (pipe),
+			usb_pipeendpoint (pipe),
+			usb_pipeout (pipe)? 'O': 'I',
+			usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+				(usb_pipecontrol (pipe)? "CTRL": "BULK"),
+			purb->actual_length,
+			transfer_len, dev->status);
 #ifdef	OHCI_VERBOSE_DEBUG
 	if (!small) {
 		int i, len;
@@ -583,7 +585,7 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)

 	if (ed->state == ED_NEW) {
 		ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
-  		/* dummy td; end of td list for ed */
+		/* dummy td; end of td list for ed */
 		td = td_alloc (usb_dev);
 		ed->hwTailP = m32_swap (td);
 		ed->hwHeadP = ed->hwTailP;
@@ -667,13 +669,13 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
 	void *data;
 	int cnt = 0;
 	__u32 info = 0;
-  	unsigned int toggle = 0;
+	unsigned int toggle = 0;

 	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
-  	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-  		toggle = TD_T_TOGGLE;
+	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+		toggle = TD_T_TOGGLE;
 	} else {
-  		toggle = TD_T_DATA0;
+		toggle = TD_T_DATA0;
 		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
 	}
 	urb->td_cnt = 0;
@@ -729,11 +731,11 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
 static void dl_transfer_length(td_t * td)
 {
 	__u32 tdINFO, tdBE, tdCBP;
- 	urb_priv_t *lurb_priv = &urb_priv;
+	urb_priv_t *lurb_priv = &urb_priv;

 	tdINFO = m32_swap (td->hwINFO);
-  	tdBE   = m32_swap (td->hwBE);
-  	tdCBP  = m32_swap (td->hwCBP);
+	tdBE   = m32_swap (td->hwBE);
+	tdCBP  = m32_swap (td->hwCBP);


 	if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
@@ -757,7 +759,7 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 	__u32 td_list_hc;
 	td_t *td_rev = NULL;
 	td_t *td_list = NULL;
-  	urb_priv_t *lurb_priv = NULL;
+	urb_priv_t *lurb_priv = NULL;

 	td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
 	ohci->hcca->done_head = 0;
@@ -792,42 +794,42 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
 /* td done list */
 static int dl_done_list (ohci_t *ohci, td_t *td_list)
 {
-  	td_t *td_list_next = NULL;
+	td_t *td_list_next = NULL;
 	ed_t *ed;
 	int cc = 0;
 	int stat = 0;
 	/* urb_t *urb; */
 	urb_priv_t *lurb_priv;
- 	__u32 tdINFO, edHeadP, edTailP;
+	__u32 tdINFO, edHeadP, edTailP;

-  	while (td_list) {
-   		td_list_next = td_list->next_dl_td;
+	while (td_list) {
+		td_list_next = td_list->next_dl_td;

-  		lurb_priv = &urb_priv;
-  		tdINFO = m32_swap (td_list->hwINFO);
+		lurb_priv = &urb_priv;
+		tdINFO = m32_swap (td_list->hwINFO);

-   		ed = td_list->ed;
+		ed = td_list->ed;

-   		dl_transfer_length(td_list);
+		dl_transfer_length(td_list);

-  		/* error code of transfer */
-  		cc = TD_CC_GET (tdINFO);
+		/* error code of transfer */
+		cc = TD_CC_GET (tdINFO);
 		if (cc != 0) {
 			dbg("ConditionCode %#x", cc);
 			stat = cc_to_error[cc];
 		}

-  		if (ed->state != ED_NEW) {
-  			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
-  			edTailP = m32_swap (ed->hwTailP);
+		if (ed->state != ED_NEW) {
+			edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+			edTailP = m32_swap (ed->hwTailP);

 			/* unlink eds if they are not busy */
-     			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-     				ep_unlink (ohci, ed);
-     		}
+			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+				ep_unlink (ohci, ed);
+		}

-    		td_list = td_list_next;
-  	}
+		td_list = td_list_next;
+	}
 	return stat;
 }

@@ -849,9 +851,9 @@ static __u8 root_hub_dev_des[] =
 	0x00,       /*  __u16 idVendor; */
 	0x00,
 	0x00,       /*  __u16 idProduct; */
- 	0x00,
+	0x00,
 	0x00,       /*  __u16 bcdDevice; */
- 	0x00,
+	0x00,
 	0x00,       /*  __u8  iManufacturer; */
 	0x01,       /*  __u8  iProduct; */
 	0x00,       /*  __u8  iSerialNumber; */
@@ -870,7 +872,7 @@ static __u8 root_hub_config_des[] =
 	0x01,       /*  __u8  bConfigurationValue; */
 	0x00,       /*  __u8  iConfiguration; */
 	0x40,       /*  __u8  bmAttributes;
-                 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+		 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
 	0x00,       /*  __u8  MaxPower; */

 	/* interface */
@@ -888,9 +890,9 @@ static __u8 root_hub_config_des[] =
 	0x07,       /*  __u8  ep_bLength; */
 	0x05,       /*  __u8  ep_bDescriptorType; Endpoint */
 	0x81,       /*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
- 	0x03,       /*  __u8  ep_bmAttributes; Interrupt */
- 	0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 	0x00,
+	0x03,       /*  __u8  ep_bmAttributes; Interrupt */
+	0x02,       /*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
 	0xff        /*  __u8  ep_bInterval; 255 ms */
 };

@@ -952,8 +954,29 @@ static unsigned char root_hub_str_index1[] =

 /* request to virtual root hub */

-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		int transfer_len, struct devrequest *cmd)
+int rh_check_port_status(ohci_t *controller)
+{
+	__u32 temp, ndp, i;
+	int res;
+
+	res = -1;
+	temp = roothub_a (controller);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = roothub_portstatus (controller, i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+			(RH_PS_PESC | RH_PS_CSC)) &&
+			((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+		void *buffer, int transfer_len, struct devrequest *cmd)
 {
 	void * data = buffer;
 	int leni = transfer_len;
@@ -961,7 +984,7 @@ static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *
 	int stat = 0;
 	__u32 datab[4];
 	__u8 *data_buf = (__u8 *)datab;
- 	__u16 bmRType_bReq;
+	__u16 bmRType_bReq;
 	__u16 wValue;
 	__u16 wIndex;
 	__u16 wLength;
@@ -1153,7 +1176,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 	len = min_t(int, len, leni);
 	if (data != data_buf)
 	    memcpy (data, data_buf, len);
-  	dev->act_len = len;
+	dev->act_len = len;
 	dev->status = stat;

 #ifdef DEBUG
@@ -1178,6 +1201,12 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	int maxsize = usb_maxpacket(dev, pipe);
 	int timeout;

+	/* device pulled? Shortcut the action. */
+	if (devgone == dev) {
+		dev->status = USB_ST_CRC_ERR;
+		return 0;
+	}
+
 #ifdef DEBUG
 	urb_priv.actual_length = 0;
 	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
@@ -1197,7 +1226,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,

 	wait_ms(10);
 	/* ohci_dump_status(&gohci); */
-	
+
 	/* allow more time for a BULK device to react - some are slow */
 #define BULK_TO	 5000	/* timeout in milliseconds */
 	if (usb_pipetype (pipe) == PIPE_BULK)
@@ -1210,7 +1239,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		/* check whether the controller is done */
 		stat = hc_interrupt();
 		if (stat < 0) {
-			stat = 1;
+			stat = USB_ST_CRC_ERR;
 			break;
 		}
 		if (stat >= 0 && stat != 0xff) {
@@ -1220,13 +1249,35 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 		if (--timeout) {
 			wait_ms(1);
 		} else {
-			err("CTL:TIMEOUT");
-			stat = 1;
+			err("CTL:TIMEOUT ");
+			stat = USB_ST_CRC_ERR;
 			break;
 		}
 	}
+	/* we got an Root Hub Status Change interrupt */
+	if (got_rhsc) {
+#ifdef DEBUG
+		ohci_dump_roothub (&gohci, 1);
+#endif
+		got_rhsc = 0;
+		/* abuse timeout */
+		timeout = rh_check_port_status(&gohci);
+		if (timeout >= 0) {
+#if 0 /* this does nothing useful, but leave it here in case that changes */
+			/* the called routine adds 1 to the passed value */
+			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
+#endif
+			/*
+			 * XXX
+			 * This is potentially dangerous because it assumes
+			 * that only one device is ever plugged in!
+			 */
+			devgone = dev;
+		}
+	}
+
 	dev->status = stat;
-  	dev->act_len = transfer_len;
+	dev->act_len = transfer_len;

 #ifdef DEBUG
 	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
@@ -1264,10 +1315,12 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 			pipe);
 		return -1;
 	}
-	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum)
+	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
+		gohci.rh.dev = dev;
 		/* root hub - redirect */
 		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
 			setup);
+	}

 	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
 }
@@ -1309,7 +1362,7 @@ static int hc_reset (ohci_t *ohci)
 		ohci->slot_name,
 		readl (&ohci->regs->control));

-  	/* Reset USB (needed by some controllers) */
+	/* Reset USB (needed by some controllers) */
 	writel (0, &ohci->regs->control);

 	/* HC Reset requires max 10 us delay */
@@ -1332,8 +1385,8 @@ static int hc_reset (ohci_t *ohci)

 static int hc_start (ohci_t * ohci)
 {
-  	__u32 mask;
-  	unsigned int fminterval;
+	__u32 mask;
+	unsigned int fminterval;

 	ohci->disabled = 1;

@@ -1345,20 +1398,28 @@ static int hc_start (ohci_t * ohci)

 	writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */

-  	fminterval = 0x2edf;
+	fminterval = 0x2edf;
 	writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
 	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
 	writel (fminterval, &ohci->regs->fminterval);
 	writel (0x628, &ohci->regs->lsthresh);

- 	/* start controller operations */
- 	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+	/* start controller operations */
+	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
 	ohci->disabled = 0;
- 	writel (ohci->hc_control, &ohci->regs->control);
+	writel (ohci->hc_control, &ohci->regs->control);

-	/* Choose the interrupts we care about now, others later on demand */
-	mask = OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+	/* disable all interrupts */
+	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+			OHCI_INTR_OC | OHCI_INTR_MIE);
+	writel (mask, &ohci->regs->intrdisable);
+	/* clear all interrupts */
+	mask &= ~OHCI_INTR_MIE;
 	writel (mask, &ohci->regs->intrstatus);
+	/* Choose the interrupts we care about now  - but w/o MIE */
+	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+	writel (mask, &ohci->regs->intrenable);

 #ifdef	OHCI_USE_NPS
 	/* required for AMD-756 and some Mac platforms */
@@ -1386,7 +1447,7 @@ hc_interrupt (void)
 {
 	ohci_t *ohci = &gohci;
 	struct ohci_regs *regs = ohci->regs;
- 	int ints;
+	int ints;
 	int stat = -1;

 	if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
@@ -1397,6 +1458,10 @@ hc_interrupt (void)

 	/* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */

+	if (ints & OHCI_INTR_RHSC) {
+		got_rhsc = 1;
+	}
+
 	if (ints & OHCI_INTR_UE) {
 		ohci->disabled++;
 		err ("OHCI Unrecoverable Error, controller usb-%s disabled",
@@ -1469,17 +1534,17 @@ int usb_lowlevel_init(void)
 	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
 	S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();

-        /*
-         * Set the 48 MHz UPLL clocking. Values are taken from
-         * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-         */
-        clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
-        gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+	/*
+	 * Set the 48 MHz UPLL clocking. Values are taken from
+	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+	 */
+	clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
+	gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */

-        /*
-         * Enable USB host clock.
-         */
-        clk_power->CLKCON |= (1 << 4);
+	/*
+	 * Enable USB host clock.
+	 */
+	clk_power->CLKCON |= (1 << 4);

 	memset (&gohci, 0, sizeof (ohci_t));
 	memset (&urb_priv, 0, sizeof (urb_priv_t));
@@ -1503,7 +1568,7 @@ int usb_lowlevel_init(void)
 	}
 	ptd = gtd;
 	gohci.hcca = phcca;
-        memset (phcca, 0, sizeof (struct ohci_hcca));
+	memset (phcca, 0, sizeof (struct ohci_hcca));

 	gohci.disabled = 1;
 	gohci.sleeping = 0;
@@ -1515,8 +1580,8 @@ int usb_lowlevel_init(void)

 	if (hc_reset (&gohci) < 0) {
 		hc_release_ohci (&gohci);
-                /* Initialization failed */
-                clk_power->CLKCON &= ~(1 << 4);
+		/* Initialization failed */
+		clk_power->CLKCON &= ~(1 << 4);
 		return -1;
 	}

@@ -1527,8 +1592,8 @@ int usb_lowlevel_init(void)
 	if (hc_start (&gohci) < 0) {
 		err ("can't start usb-%s", gohci.slot_name);
 		hc_release_ohci (&gohci);
-                /* Initialization failed */
-                clk_power->CLKCON &= ~(1 << 4);
+		/* Initialization failed */
+		clk_power->CLKCON &= ~(1 << 4);
 		return -1;
 	}

--- a/cpu/arm920t/usb_ohci.h
+++ b/cpu/arm920t/usb_ohci.h
@@ -224,7 +224,6 @@ struct ohci_regs {
 #define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */


-
 /* Virtual Root HUB */
 struct virt_root_hub {
 	int devnum; /* Address of Root Hub endpoint */
--- a/cpu/arm926ejs/interrupts.c
+++ b/cpu/arm926ejs/interrupts.c
@@ -79,7 +79,6 @@ int disable_interrupts (void)
 #endif


-
 void bad_mode (void)
 {
 	panic ("Resetting CPU ...\n");
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -31,7 +31,6 @@
 */


-
 #include <config.h>
 #include <version.h>

@@ -144,7 +143,7 @@ reset:
 	msr	cpsr,r0


-	/* 
+	/*
 	 * turn off the watchdog, unlock/diable sequence
 	 */
 	mov	r1, #0xF5
@@ -154,9 +153,6 @@ reset:
 	strh	r1, [r0]


-
-
-
 	/*
 	 * mask all IRQs by setting all bits in the INTMR - default
 	 */
@@ -411,7 +407,7 @@ fiq:
 .globl reset_cpu
 reset_cpu:
 	ldr	r1, rstctl1	/* get clkm1 reset ctl */
-	mov	r3, #0x0	
+	mov	r3, #0x0
 	strh	r3, [r1]	/* clear it */
 	mov	r3, #0x8
 	strh	r3, [r1]	/* force dsp+arm reset */
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
wdenk	42d1f0394b	* Patches by Xianghua Xiao, 15 Oct 2003: - Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup	2003-10-15 23:53:47 +00:00
wdenk	2d5b561e2b	* Make sure HUSH is initialized for running auto-update scripts * Make 5200 reset command _really_ reset the board, without running any other code after it * Fix flash mapping and display on P3G4 board * Patch by Kyle Harris, 15 Jul 2003: - add support for Intel IXP425 CPU - add support for IXDP425 eval board	2003-10-14 19:43:55 +00:00
wdenk	f72da3406b	Added config option CONFIG_SILENT_CONSOLE. See doc/README.silent for more information	2003-10-10 10:05:42 +00:00
wdenk	5da627a424	* Patch by Steven Scholz, 10 Oct 2003 - Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003: - Endian swap ATA identity for all big endian CPUs, not just PPC - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize args to linux - add support for dbau1x00 board (MIPS32)	2003-10-09 20:09:04 +00:00
wdenk	15647dc7fd	* Patches by Thomas Lange, 09 Oct 2003: - fix cmd_ide.c for non ppc boards (read/write functions did not add ATA base address) - fix for shannon board - #ifdef CONFIG_IDE_8xx_DIRECT some otherwise unused code * Patch by Sangmoon Kim, 07 Oct 2003: add support for debris board	2003-10-09 19:00:25 +00:00
wdenk	a0ff7f2eda	* Patch by Martin Krause, 09 Oct 2003: Fixes for TRAB board - /board/trab/rs485.c: correct baudrate - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in udelay(); fix some timing problems with adc controller - /board/trab/trab_fkt.c: add new commands: gain, eeprom and power; modify commands: touch and buzzer * Disable CONFIG_SUPPORT_VFAT when used with CONFIG_AUTO_UPDATE (quick & dirty workaround for rogue pointer problem in get_vfatname()); Use direct function calls for auto_update instead of hush commands	2003-10-09 13:16:55 +00:00
wdenk	4a5517094d	* Patch by Scott McNutt, 04 Oct 2003: - add support for Altera Nios-32 CPU - add support for Nios Cyclone Development Kit (DK-1C20) * Patch by Steven Scholz, 29 Sep 2003: - A second parameter for bootm overwrites the load address for "Standalone Application" images. - bootm sets environment variable "filesize" to the resulting (uncompressed) data length for "Standalone Application" images when autostart is set to "no". Now you can do something like if bootm $fpgadata $some_free_ram ; then fpga load 0 $some_free_ram $filesize fi * Patch by Denis Peter, 25 Sept 2003: add support for the MIP405 Rev. C board	2003-10-08 23:26:14 +00:00
wdenk	54387ac931	* Patch by Yuli Barcohen, 25 Sep 2003: add support for Zephyr Engineering ZPC.1900 board * Patch by Anders Larsen, 23 Sep 2003: add CMD_PORTIO to CFG_CMD_NONSTD (commands in question are only implemented for the x86 architecture)	2003-10-08 22:45:44 +00:00
wdenk	fc3e2165ef	* Patch by Sangmoon Kim, 23 Sep 2003: fix pll_pci_to_mem_multiplier table for MPC8245 * Patch by Anders Larsen, 22 Sep 2003: enable timed autoboot on PXA * Patch by David M�ller, 22 Sep 2003: - add $(CFLAGS) to "-print-libgcc-filename" so compiler driver returns correct libgcc file path - "latency" reduction of busy-loop waiting to improve "U-Boot" boot time on s3c24x0 systems * Patch by Jon Diekema, 19 Sep 2003: - Add CFG_FAULT_ECHO_LINK_DOWN option to echo the inverted Ethernet link state to the fault LED. - In NetLoop, make the Fault LED reflect the link status. The link status gets updated on entry, and on timeouts.	2003-10-08 22:33:00 +00:00
wdenk	ef1464cc01	* Patch by Anders Larsen, 18 Sep 2003: allow mkimage to build and run on Cygwin-hosted systems * Patch by Frank M�ller, 18 Sep 2003: use bi_intfreq instead of bi_busfreq to compute fec_mii_speed in cpu/mpc8xx/fec.c * Patch by Pantelis Antoniou, 16 Sep 2003: add tool to compute fileds in the PLPRCR register for MPC86x	2003-10-08 22:14:02 +00:00
wdenk	d9a405aaf6	Use IH_TYPE_FILESYSTEM for TRAB "disk" images.	2003-10-07 20:01:55 +00:00
wdenk	147031aef1	Fix build problems under FreeBSD	2003-10-07 10:33:38 +00:00
wdenk	887b372f5d	Add generic filesystem image type	2003-10-06 22:00:45 +00:00
wdenk	fbe4b5cbde	* Update TRAB auto update code * Make fatload set filesize environment variable fix potential buffer overlow problem * enable basic / medium / high-end configurations for PPChameleonEVB board; fix NAND code * enable TFTP client code to specify to the server the desired timeout value (see RFC-2349)	2003-10-06 21:55:32 +00:00
dzu	bb65a31267	Improve SDRAM setup for TRAB board	2003-09-30 15:22:12 +00:00
dzu	88a1bfa8b8	Suppress all output with splashscreen configured only if "splashimage" is set	2003-09-30 15:11:43 +00:00
dzu	cad07371fc	* Fix problems with I2C support for mpc5200	2003-09-30 14:36:51 +00:00
dzu	ab209d5107	Fix problems with I2C support for mpc5200	2003-09-30 14:08:43 +00:00
dzu	87970ebeb5	Suppress all output with splashscreen configured only if "splashimage" is set	2003-09-29 21:55:54 +00:00
dzu	8a42eac744	* Adapt TRAB configuration and auto_update to new memory layout	2003-09-29 21:55:54 +00:00
dzu	91e940d9bc	Add configuration for wtk board	2003-09-25 22:32:40 +00:00
dzu	29127b6a23	Add support for the Sharp LQ065T9DR51U LCD display	2003-09-25 22:30:12 +00:00
wdenk	1d70468b03	"start" may be legitimately 0x0000	2003-09-19 08:29:25 +00:00
wdenk	c3d98ed9ca	Update MPC5200 port pin configuration for Linux CAN drivers.	2003-09-18 20:10:12 +00:00