Add support for IDS "NC650" board

* Add automatic update support for LWMON board
* Enable MSDOS/VFAT filesystem support for LWMON board * Clear Block Lock-Bits when erasing flash on LWMON board. * Fix return code of "fatload" command * Disable debugging for TQM5200 board
2026-06-09 13:16:40 +03:00 · 2004-08-28 22:45:57 +00:00 · 2004-08-28 21:09:14 +00:00 · 2004-08-04 21:56:49 +00:00 · 2004-08-02 23:39:03 +00:00 · 2004-08-02 23:22:59 +00:00
406 changed files with 45189 additions and 6798 deletions
--- a/382
+++ b/382
@@ -2,6 +2,388 @@
 Changes since U-Boot 1.1.1:
 ======================================================================

+* Add support for IDS "NC650" board
+
+* Add automatic update support for LWMON board
+
+* Clear Block Lock-Bits when erasing flash on LWMON board.
+
+* Fix return code of "fatload" command
+
+* Enable MSDOS/VFAT filesystem support for LWMON board
+
+* Patch by Martin Krause, 03 Aug 2004:
+  change timing for SM501 graphics controller on TQM5200 module
+
+* Patch by Mark Jonas, 13 July 2004:
+  - Total5200 LCD now run in little endian mode. Endianess conversion
+    is done in hardware.
+  - Removed last reference to "console" environment variable.
+
+* Patches by Lars Munch, 12 Jul 2004:
+  - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk
+    board specific
+  - split out the LXT971A PHY from ns_9750_eth.h
+  - split the dm9161 phy part out of at91rm9200_ether.c
+
+* Patch by Andreas Engel, 12 Jul 2004:
+  Replaced hardcoded PL011 clock frequency with config variable.
+  Fixed wrong CONFIG_CMD_DFL doc.
+
+* Patch by Thomas Viehweger, 09 Jun 2004:
+  make it possible to remove chpart when there is only one partition
+
+* Add support for console over UDP (compatible to Ingo Molnar's
+  netconsole patch under Linux)
+
+* Patch by Jon Loeliger, 16 Jul 2004:
+  - support larger DDR memories up to 2G on the PC8540/8560ADS and
+    STXGP3 boards
+  - Made MPC8540/8560ADS be 33Mhz PCI by default.
+  - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
+    and CONFIG_L2_INIT_RAM options.
+  - Refactor Local Bus initialization out of SDRAM setup.
+  - Re-implement new version of LBC11/DDR11 errata workarounds.
+  - Moved board specific PCI init parts out of CPU directory.
+  - Added TLB entry for PCI-1 IO Memory
+  - Updated README.mpc85xxads
+
+* Patch by Sascha Hauer, 28 Jun:
+  - add generic support for Motorola i.MX architecture
+  - add support for mx1ads, mx1fs2 and scb9328 boards
+
+* Patches by Marc Leeman, 23 Jul 2004:
+  - Add define for the PCI/Memory Buffer Configuration Register
+  - corrected comments in cpu/mpc824x/cpu_init.c
+
+* Add support for multiple serial interfaces
+  (for example to allow modem dial-in / dial-out)
+
+* Patch by Stefan Roese, 15 Jul 2004:
+  cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
+
+* Fix NSCU config; add ethernet wakeup code.
+
+* Add link for preloader for Motorola Coldfire to README.m68k
+
+* Patch by Michael Bendzick, 12 Jul 2004:
+  fix output formatting in drivers/cfi_flash.c
+
+* Patch by Mark Jonas, 02 Jul 2004:
+  Fix lowboot (again) on MPC5xxx
+
+* Patch by Curt Brune, 07 Jul 2004:
+  relocate exception vectors on arm720t if needed
+
+* Patch by George G. Davis, 06 Jul 2004:
+  - update mach-types.h to latest arm.linux.org.uk master list
+  - Set correct OMAP1610 bi_arch_number for build target
+
+* Patch by Curt Brune, 06 Jul 2004:
+  evb4510: add support for timer interrupt; cleanup
+
+* Patch by Dan Poirot, 06 Jul 2004:
+  Fix sbc8260 environment variables
+
+* Cleanup redundand "console" environment variable
+
+* Patch by Mark Jonas, 05 Jul 2004:
+  add support for the Total5100's and Total5200's LCD screen
+
+* Patches by Dan Eisenhut, 01 Jul 2004:
+  - README fixes.
+  - Move doc2000.h include to prevent compiler warning on some boards
+
+* Patch by Mark Jonas, 01 Jul 2004:
+  Added support for Total5100 and Total5200 (Rev.1 and Rev.2)
+  MGT5100 and MPC5200 based Freescale platforms.
+
+* Patch by Philippe Robin, 01 Jul 2004:
+  Add initialization for Integrator and versatile board files.
+
+* Patch by Hinko Kocevar, 01 Jun 2004:
+  Fix VFD FB allocation, add LCD FB allocation on ARM
+
+* Patch by Martin Krause, 30 Jun 2004:
+  Add support for TQM5200 board
+
+* Patch by Martin Krause, 29 Jun 2004:
+  Add loopw command: infinite write loop on address range
+
+* Patches by Yasushi Shoji, 29 Jun 2004:
+  - add empty include/asm-microblaze/processor.h
+  - add to CREDITS and MAINTAINERS
+  - add gd initialization
+  - add MicroBlaze and SUZAKU board to MAKEALL script
+  - add reset support for SUZAKU
+  - add flush_cache() for MicroBlaze
+  - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed
+    size flash memory on SUZAKU
+
+* Patch by Prakash Kumar, 27 Jun 2004:
+  Add support for the PXA250 based Intrinsyc Cerf board.
+
+* Patch by Yasushi Shoji, 27 Jun 2004:
+  fix comment in include/common.h
+
+* Rename SBC8560 into sbc8560 for consistency
+
+* Patch by Daniel Poirot, 24 Jun 2004:
+  Add support for Wind River's sbc8240 board
+
+* Patches by Yasushi Shoji, 26 Jun 2004:
+  - drivers/serial_xuartlite.c: fix "return 0" in void function
+  - add microblaze support to mkimage tool
+
+* Patch by Fred Klatt, 25 Jun 2004:
+  Add support for WindRiver's sbc8560 board
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004
+  Small Bugs fixes for "at91rm9200dk" board:
+  - Timing modifications for SPI DataFlash access
+  - Fix NAND flash detection bug
+
+* Patch by Nicolas Lacressonniere, 24 Jun 2004:
+  Add Support for Flash AT49BV6416 for AT91RM9200DK board
+
+* Patch by Jon Loeliger, 17 June 2004:
+  Completion of the 8540ADS/8560ADS updates:
+  Fix some PCI and Rapid I/O memory maps,
+  Initialize both TSEC 1 and 2,
+  Initialize SDRAM
+  Update MAINTAINER for 85xx boards and README.mpc85xxads
+
+* Patch by Yuli Barcohen, 16 Jun 2004:
+  Remove obsolete AdderII port which was superseded by unified
+  AdderII/Adder87x port
+
+* Patch by Ladislav Michl, 16 Jun 2004:
+  Fix gcc-3.3.3 warnings for smc91111.c
+
+* Patch by Stefan Roese, 02 Jul 2004:
+  - Fix bug in 405 ethernet driver; allocated data not cleared!
+  - Fix problem in 405 i2c driver; don't try to print without console!
+
+* Patch by Paul Ruhland, 11 Jun 2004:
+  Remove debug code from 'board/lpd7a40x/flash.c'
+
+* Patch by Andrea Marson, 11 Jun 2004:
+  Update for PPChameleon board:
+  - support for SysClk @ 25MHz
+  - support for Silicon Motion SM712 VGA controller
+  - some clean ups
+
+* Patches by Richard Woodruff, 10 Jun 2004:
+  - fix problems with examples/stubs.c for GCC >= 3.4
+  - fix problems with gd initialization
+
+* Patch by Curt Brune, 17 May 2004:
+  - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+  - Add support for ESPD-Inc. EVB4510 Board
+
+* Patch by Marc Leeman, 11 May 2004:
+  Fix for MPC8245 - reading PPC Memory from another device with the
+  PPC as PCI target device corrupts data due to interenal hardware
+  buffering.
+
+* Fix "cls" command when used with splash screen
+
+* Increase NFS download timeout (now 1 min - 10 sec is to short for a
+  slow download of a big image)
+
+* Add "cls" function to MPC823 LCD driver so we can reinitialize the
+  display even after showing a bitmap
+
+* Patch by Josef Wagner, 04 Jun 2004:
+  - DDR Ram support for PM520 (MPC5200)
+  - support for different flash types (PM520)
+  - USB / IDE / CF-Card / DiskOnChip support for PM520
+  - 8 bit boot rom support for PM520/CE520
+  - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
+  - I2C and RTC support for CPC45
+  - support of new flash type (28F160C3T) for CPC45
+
+* Fix flash parameters passed to Linux for PPChameleon board
+
+* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
+
+* Patch by Paul Ruhland, 10 Jun 2004:
+  fix support for Logic SDK-LH7A404 board and clean up the
+  LH7A404 register macros.
+
+* Patch by Matthew McClintock, 10 Jun 2004:
+  Modify code to select correct serial clock on Sandpoint8245
+
+* Patch by Robert Schwebel, 10 Jun 2004:
+  Add support for Intel K3 strata flash.
+
+* Patch by Thomas Brand, 10 Jun 2004:
+  Fix "loads" command on DK1S10 board
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+  Add support for 8MB flash SIMM and JFFS2 file system on
+  Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).
+
+* Patch by Yuli Barcohen, 09 Jun 2004:
+  Add support for Analogue&Micro Adder87x and the older AdderII board.
+
+* Patch by Ming-Len Wu, 09 Jun 2004:
+  Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board
+
+* Patch by Sam Song, 09 Jun 2004:
+  - Add support for RPXlite_DW board
+  - Update FLASH driver for 4*AM29DL323DB90VI
+  - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board
+
+* Patch by Mark Jonas, 08 June 2004:
+  - Make MPC5200 boards evaluate the SVR to print processor name and
+    version in checkcpu() (cpu/mpc5xxx/cpu.c).
+
+* Patch by Kai-Uwe Bloem, 06 May 2004:
+  Fix endianess problem in cramfs code
+
+* Patch by Tom Armistead, 04 Jun 2004:
+  Add support for MAX6900 RTC
+
+* Patches by Ladislav Michl, 03 Jun 2004:
+  - fix cfi_flash.c on LE systems
+  - let 'make mrproper' delete u-boot.img as well
+  - turn printf into debug in cfi_flash.c
+
+* Patch by Kurt Stremerch, 28 May 2004:
+  Add support for Exys XSEngine board
+
+* Patch by Martin Krause, 27 May 2004:
+  Fix a MPC5xxx I2C timing issue in i2c_probe().
+
+* Patch by Leif Lindholm, 27 May 2004:
+  Fix board_init_f() for dbau1x00 board.
+
+* Patch by Imre Deak, 26 May 2004:
+  On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3).
+  Set flash base accordingly, and decide whether to do or skip board
+  specific setup steps.
+
+* Patch by Josef Baumgartner, 26 May 2004:
+  Add missing define in include/asm-m68k/global_data.h
+
+* Patch by Josef Baumgartner, 25 May 2004:
+  Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c
+
+* Patch by Paul Ruhland, 24 May 2004:
+  fix SDRAM initialization for LPD7A400 board.
+
+* Patch by Jian Zhang, 20 May 2004:
+  add support for environment in NAND flash
+
+* Patch by Yuli Barcohen, 20 May 2004:
+  Add support for Interphase iSPAN boards.
+
+* Patches by Paul Ruhland, 17 May 2004:
+  - Add I/O functions to the smc91111 ethernet driver to support the
+    Logic LPD7A40x boards.
+  - Add support for the Logic Zoom LH7A40x based SDK board(s),
+    specifically the LPD7A400.
+
+* Patches by Robert Schwebel, 15 May 2004:
+  - call MAC address reading code also for SMSC91C111;
+  - make SMSC91C111 timeout configurable, remove duplicate code
+  - fix get_timer() for PXA
+  - update doc/README.JFFS2
+  - use "bootfile" env variable also for jffs2
+
+* Patch by Tolunay Orkun, 14 May 2004:
+  Add support for Cogent CSB472 board (8MB Flash Rev)
+
+* Patch by Thomas Viehweger, 14 May 2004:
+  - flash.h: more flash types added
+  - immap_8260.h: some bits added (useful for RMII)
+  - cmd_coninfo.c: typo corrected, printf -> puts
+  - reduced size by replacing spaces with tab
+
+* Patch by Robert Schwebel, 13 May 2004:
+  Add 'imgextract' command: extract one part of a multi file image.
+
+* Patches by Jon Loeliger, 11 May 2004:
+  Dynamically handle REV1 and REV2 MPC85xx parts.
+    (Jon Loeliger, 10-May-2004).
+  New consistent memory map and Local Access Window across MPC85xx line.
+  New CCSRBAR at 0xE000_0000 now.
+  Add RAPID I/O memory map.
+  New memory map in README.MPC85xxads
+    (Kumar Gala, 10-May-2004)
+  Better board and CPU identification on MPC85xx boards at boot.
+    (Jon Loeliger, 10-May-2004)
+  SDRAM clock control fixes on MPC8540ADS & MPC8560 boards.
+  Some configuration options for MPC8540ADS & MPC8560ADS cleaned up.
+    (Jim Robertson, 10-May-2004)
+  Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver.
+  Supports multiple PHYs.
+    (Andy Fleming, 10-May-2004)
+  Some README.MPC85xxads updates.
+    (Kumar Gala, 10-May-2004)
+  Copyright updates for "Freescale"
+    (Andy Fleming, 10-May-2004)
+
+* Patch by Stephen Williams, 11 May 2004:
+  Add flash support for ST M29W040B
+  Reduce JSE specific flash.c to remove dead code.
+
+* Patch by Markus Pietrek, 04 May 2004:
+  Fix clear_bss code for ARM systems (all except s3c44b0 which
+  doesn't clear BSS at all?)
+
+* Fix "ping" problem on INC-IP board. Strange problem:
+  Sometimes the store word instruction hangs while writing to one of
+  the Switch registers, but only if the next instruction is 16-byte
+  aligned. Moving the instruction into a separate function somehow
+  makes the problem go away.
+
+* Patch by Rishi Bhattacharya, 08 May 2004:
+  Add support for TI OMAP5912 OSK Board
+
+* Patch by Sam Song May, 07 May 2004:
+  Fix typo of UPM table for rmu board
+
+* Patch by Pantelis Antoniou, 05 May 2004:
+  - Intracom board update.
+  - Add Codec POST.
+
+* Add support for the second Ethernet interface for the 'PPChameleon'
+  board.
+
+* Patch by Dave Peverley, 30 Apr 2004:
+  Add support for OMAP730 Perseus2 Development board
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+  Fix flash chip-select (OR0) option register setting on FADS boards.
+
+* Patch by Alan J. Luse, 29 Apr 2004:
+  Report MII network speed and duplex setting properly when
+  auto-negotiate is not enabled.
+
+* Patch by Jarrett Redd, 29 Apr 2004:
+  Fix hang on reset on Ocotea board due to flash in wrong mode.
+
+* Patch by Dave Peverley, 29 Apr 2004:
+  add MAC address detection to smc91111 driver
+
+* Patch by David Müller, 28 Apr 2004:
+  fix typo in lib_arm/board.c
+
+* Patch by Tolunay Orkun, 20 Apr 2004:
+  - README update: add CONFIG_CSB272 and csb272_config
+  - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and
+    i2cfast environment variable
+
+* Patch by Yuli Barcohen, 19 Apr 2004:
+  - Rename DUET_ADS to MPC885ADS
+  - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY
+  - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY
+  - Clean up FADS family port to use the new defines
+
+* Fix PCI support on CPC45 board
+
 * Patch by Scott McNutt, 25 Apr 2004:
  Add Nios GDB/JTAG Console support:
  - Add stubs to support gdb via JTAG.
--- a/74
+++ b/74
@@ -38,6 +38,8 @@ N: Yuli Barcohen
 E: yuli@arabellasw.com
 D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
 D: Support for Zephyr Engineering ZPC.1900 board.
+D: Support for Interphase iSPAN boards.
+D: Support for Analogue&Micro Adder boards.
 W: http://www.arabellasw.com

 N: Jerry van Baren
@@ -73,6 +75,12 @@ N: Oliver Brown
 E: obrown@adventnetworks.com
 D: Port to the gw8260 board

+N: Curt Brune
+E: curt@cucy.com
+D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+D: Added support for ESPD-Inc. EVB4510 Board
+W: http://www.cucy.com
+
 N: Jonathan De Bruyne
 E: jonathan.debruyne@siemens.atea.be
 D: Port to Siemens IAD210 board
@@ -198,6 +206,15 @@ N: Yoo. Jonghoon
 E: yooth@ipone.co.kr
 D: Added port to the RPXlite board

+N: Mark Jonas
+E: mark.jonas@freescale.com
+D: Support for Freescale Total5200 platform
+W: http://www.mobilegt.com/
+
+N: Sam Song
+E: samsongshu@yahoo.com.cn
+D: Port to the RPXlite_DW board
+
 N: Brad Kemp
 E: Brad.Kemp@seranoa.com
 D: Port to Windriver ppmc8260 board
@@ -219,6 +236,10 @@ N: Bernhard Kuhn
 E: bkuhn@metrowerks.com
 D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards

+N: Prakash Kumar
+E: prakash@embedx.com
+D  Support for Intrinsyc CERF PXA250 board.
+
 N: Thomas Lange
 E: thomas@corelatus.se
 D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
@@ -242,6 +263,11 @@ N: Dan Malek
 E: dan@netx4.com
 D: FADSROM, the grandfather of all of this

+N: Andrea "llandre" Marson
+E: andrea.marson@dave-tech.it
+D: Port to PPChameleonEVB board
+W: www.dave-tech.it
+
 N: Reinhard Meyer
 E: r.meyer@emk-elektronik.de
 D: Port to EMK TOP860 Module
@@ -269,7 +295,7 @@ W: www.elinos.com

 N: Tolunay Orkun
 E: torkun@nextio.com
-D: Support for Cogent CSB272 board
+D: Support for Cogent CSB272 & CSB472 boards

 N: Keith Outwater
 E: keith_outwater@mvis.com
@@ -285,10 +311,20 @@ D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
 D: Support for PIP405 board
 D: Support for MIP405 board

+N: Dave Peverley
+E: dpeverley@mpc-data.co.uk
+W: http://www.mpc-data.co.uk
+D: OMAP730 P2 board support
+
 N: Bill Pitts
 E: wlp@mindspring.com
 D: BedBug embedded debugger code

+N: Daniel Poirot
+E: dan.poirot@windriver.com
+D: Support for the sbc8240 board
+W: http://www.windriver.com
+
 N: Stefan Roese
 E: stefan.roese@esd-electronics.com
 D: IBM PPC401/403/405GP Support; Windows environment support
@@ -297,6 +333,10 @@ N: Erwin Rol
 E: erwin@muffin.org
 D: boot support for RTEMS

+N: Paul Ruhland
+E: pruhland@rochester.rr.com
+D: Port to Logic Zoom LH7A40x SDK board(s)
+
 N: Neil Russell
 E: caret@c-side.com
 D: Author of LiMon-1.4.2, which contributed some ideas
@@ -313,6 +353,19 @@ N: Robert Schwebel
 E: r.schwebel@pengutronix.de
 D: Support for csb226, logodl and innokom boards (PXA2xx)

+N: Yasushi Shoji
+E: yashi@atmark-techno.com
+D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
+
+N: Kurt Stremerch
+E: kurt@exys.be
+D: Support for Exys XSEngine board
+
+N: Andrea Scian
+E: andrea.scian@dave-tech.it
+D: Port to B2 board
+W: www.dave-tech.it
+
 N: Rob Taylor
 E: robt@flyingpig.com
 D: Port to MBX860T and Sandpoint8240
@@ -333,13 +386,22 @@ N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions

+N: Christian Vejlbo
+E: christian.vejlbo@tellabs.com
+D: FADS860T ethernet support
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board

-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
+N: Ming-Len Wu
+E: minglen_wu@techware.com.tw
+D: Motorola MX1ADS board support
+W: http://www.techware.com.tw/
+
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.

 N: John Zhan
 E: zhanz@sinovee.com
@@ -349,7 +411,3 @@ N: Alex Zuepke
 E: azu@sysgo.de
 D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
 W: www.elinos.com
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
--- a/52
+++ b/52
@@ -27,6 +27,8 @@ Pantelis Antoniou <panto@intracom.gr>

 Yuli Barcohen <yuli@arabellasw.com>

+	Adder			MPC87x/MPC852T
+	ISPAN			MPC8260
 	MPC8260ADS		MPC826x/MPC827x/MPC8280
 	ZPC1900			MPC8265

@@ -56,13 +58,14 @@ Torsten Demke <torsten.demke@fci.com>

 Wolfgang Denk <wd@denx.de>

+	IceCube_5100		MGT5100
+	IceCube_5200		MPC5200
+
 	AMX860			MPC860
 	ETX094			MPC850
 	FPS850L			MPC850
 	FPS860L			MPC860
 	ICU862			MPC862
-	IceCube_5100		MGT5100
-	IceCube_5200		MPC5200
 	IP860			MPC860
 	IVML24			MPC860
 	IVML24_128		MPC860
@@ -72,6 +75,7 @@ Wolfgang Denk <wd@denx.de>
 	IVMS8_256		MPC860
 	LANTEC			MPC850
 	LWMON			MPC823
+	NC650			MPC852
 	R360MPI			MPC823
 	RMU			MPC850
 	RRvision		MPC823
@@ -163,10 +167,6 @@ Sangmoon Kim <dogoil@etinsys.com>

 	debris			MPC8245

-Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
-
-	ADDERII			MPC852T
-
 Nye Liu <nyet@zumanetworks.com>

 	ZUMA			MPC7xx_74xx
@@ -183,6 +183,10 @@ Eran Man <eran@nbase.co.il>

 	EVB64260_750CX		MPC750CX

+Andrea "llandre" Marson <andrea.marson@dave-tech.it>
+
+	PPChameleonEVB	PPC405EP
+
 Reinhard Meyer <r.meyer@emk-elektronik.de>

 	TOP860			MPC860T
@@ -193,7 +197,8 @@ Scott McNutt <smcnutt@artesyncp.com>
 	EBONY			PPC440GP

 Tolunay Orkun <torkun@nextio.com>
-	csb272			PPC4xx
+	csb272			PPC405GP
+	csb472			PPC405GP

 Keith Outwater <Keith_Outwater@mvis.com>

@@ -254,6 +259,11 @@ Rune Torgersen <runet@innovsys.com>

 	MPC8266ADS		MPC8266

+Josef Wagner <Wagner@Microsys.de>
+
+	CPC45			MPC8245
+	PM520			MPC5200
+
 Stephen Williams <steve@icarus.com>

 	JSE			PPC405GPr
@@ -262,7 +272,7 @@ John Zhan <zhanz@sinovee.com>

 	svm_sc8xx		MPC8xx

-Xianghua Xiao <x.xiao@motorola.com>
+Jon Loeliger <jdl@freescale.com>

 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
@@ -335,15 +345,26 @@ Gary Jennejohn <gj@denx.de>
 	smdk2400		ARM920T
 	trab			ARM920T

+Prakash Kumar <prakash@embedx.com>
+
+	cerf250			xscale
+
 Kshitij Gupta <kshitij@ti.com>

 	omap1510inn		ARM925T
 	omap1610inn		ARM926EJS

+Dave Peverley <dpeverley@mpc-data.co.uk>
+	omap730p2		ARM926EJS
+
 Nishant Kamat <nskamat@ti.com>

 	omap1610h2		ARM926EJS

+Rishi Bhattacharya <rishi@ti.com>
+
+	omap5912osk		ARM926EJS
+
 David Müller <d.mueller@elsoft.ch>

 	smdk2410		ARM920T
@@ -358,6 +379,10 @@ Robert Schwebel <r.schwebel@pengutronix.de>
 	csb226			xscale
 	innokom			xscale

+Andrea Scian <andrea.scian@dave-tech.it>
+
+	B2				ARM7TDMI (S3C44B0X)
+
 Alex Züpke <azu@sysgo.de>

 	lart			SA1100
@@ -405,6 +430,17 @@ Scott McNutt <smcnutt@psyent.com>

 	DK1C20			Nios-32

+#########################################################################
+# MicroBlaze Systems:							#
+#									#
+# Maintainer Name, Email Address					#
+#	Board			CPU					#
+#########################################################################
+
+Yasushi Shoji <yashi@atmark-techno.com>
+
+	SUZAKU			MicroBlaze
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################
--- a/81
+++ b/81
@@ -26,6 +26,7 @@ LIST_5xx="	\

 LIST_5xxx="	\
 	icecube_5100	icecube_5200	EVAL5200	PM520		\
+	Total5100	Total5200	Total5200_Rev2	TQM5200_AA	\
 "

 #########################################################################
@@ -33,22 +34,23 @@ LIST_5xxx="	\
 #########################################################################

 LIST_8xx="	\
-	AdderII		ADS860		AMX860		c2mon		\
-	CCM		cogent_mpc8xx	DUET_ADS	ESTEEM192E	\
-	ETX094		ELPT860		FADS823		FADS850SAR	\
-	FADS860T	FLAGADM		FPS850L		GEN860T		\
-	GEN860T_SC	GENIETV		GTH		hermes		\
-	IAD210		ICU862_100MHz	IP860		IVML24		\
-	IVML24_128	IVML24_256	IVMS8		IVMS8_128	\
-	IVMS8_256	KUP4K		KUP4X		LANTEC		\
-	lwmon		MBX		MBX860T		MHPC		\
-	MPC86xADS	MVS1		NETVIA		NETVIA_V2	\
-	NX823		pcu_e		QS823		QS850		\
-	QS860T		R360MPI		RBC823		rmu		\
-	RPXClassic	RPXlite		RRvision	SM850		\
-	SPD823TS	svm_sc8xx	SXNI855T	TOP860		\
-	TQM823L		TQM823L_LCD	TQM850L		TQM855L		\
-	TQM860L		v37		NETTA		NETPHONE	\
+	Adder87x	GENIETV		MBX860T		RBC823		\
+	AdderII		GTH		MHPC		rmu		\
+	ADS860		hermes		MPC86xADS	RPXClassic	\
+	AMX860		IAD210		MPC885ADS	RPXlite		\
+	c2mon		ICU862_100MHz	MVS1		RPXlite_DW	\
+	CCM		IP860		NETPHONE	RRvision	\
+	cogent_mpc8xx	IVML24		NETTA		SM850		\
+	ELPT860		IVML24_128	NETTA2		SPD823TS	\
+	ESTEEM192E	IVML24_256	NETTA_ISDN	svm_sc8xx	\
+	ETX094		IVMS8		NETVIA		SXNI855T	\
+	FADS823		IVMS8_128	NETVIA_V2	TOP860		\
+	FADS850SAR	IVMS8_256	NX823		TQM823L		\
+	FADS860T	KUP4K		pcu_e		TQM823L_LCD	\
+	FLAGADM		KUP4X		QS823		TQM850L		\
+	FPS850L		LANTEC		QS850		TQM855L		\
+	GEN860T		lwmon		QS860T		TQM860L		\
+	GEN860T_SC	MBX		R360MPI		v37		\
 "

 #########################################################################
@@ -59,13 +61,13 @@ LIST_4xx="	\
 	ADCIOP		AR405		ASH405		BUBINGA405EP	\
 	CANBT		CPCI405		CPCI4052	CPCI405AB	\
 	CPCI440		CPCIISER4	CRAYL1		csb272		\
-	DASA_SIM	DP405		DU405		EBONY		\
-	ERIC		EXBITGEN	HUB405		JSE		\
-	MIP405		MIP405T		ML2		ml300		\
-	OCOTEA		OCRTC		ORSG		PCI405		\
-	PIP405		PLU405		PMC405		PPChameleonEVB	\
-	VOH405		W7OLMC		W7OLMG		WALNUT405	\
-	XPEDITE1K							\
+	csb472		DASA_SIM	DP405		DU405		\
+	EBONY		ERIC		EXBITGEN	HUB405		\
+	JSE		MIP405		MIP405T		ML2		\
+	ml300		OCOTEA		OCRTC		ORSG		\
+	PCI405		PIP405		PLU405		PMC405		\
+	PPChameleonEVB	VOH405		W7OLMC		W7OLMG		\
+	WALNUT405	XPEDITE1K					\
 "

 #########################################################################
@@ -76,7 +78,7 @@ LIST_824x="	\
 	A3000		BMW		CPC45		CU824		\
 	debris		eXalion		MOUSSE		MUSENKI		\
 	MVBLUE		OXC		PN62		Sandpoint8240	\
-	Sandpoint8245	SL8245		utx8245				\
+	Sandpoint8245	SL8245		utx8245		sbc8240	\
 "

 #########################################################################
@@ -85,11 +87,11 @@ LIST_824x="	\

 LIST_8260="	\
 	atc		cogent_mpc8260	CPU86		ep8260		\
-	gw8260		hymod		IPHASE4539	MPC8260ADS	\
-	MPC8266ADS	MPC8272ADS	PM826		PM828		\
-	ppmc8260	PQ2FADS		RPXsuper	rsdproto	\
-	sacsng		sbc8260		SCM		TQM8260_AC	\
-	TQM8260_AD	TQM8260_AE	ZPC1900				\
+	gw8260		hymod		IPHASE4539	ISPAN		\
+	MPC8260ADS	MPC8266ADS	MPC8272ADS	PM826		\
+	PM828		ppmc8260	PQ2FADS		RPXsuper	\
+	rsdproto	sacsng		sbc8260		SCM		\
+	TQM8260_AC	TQM8260_AD	TQM8260_AE	ZPC1900		\
 "

 #########################################################################
@@ -97,7 +99,7 @@ LIST_8260="	\
 #########################################################################

 LIST_85xx="	\
-	MPC8540ADS	MPC8560ADS	stxgp3				\
+	MPC8540ADS	MPC8560ADS	sbc8560		stxgp3		\
 "

 #########################################################################
@@ -130,24 +132,24 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
 ## ARM7 Systems
 #########################################################################

-LIST_ARM7="B2 ep7312 impa7"
+LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"

 #########################################################################
 ## ARM9 Systems
 #########################################################################

 LIST_ARM9="	\
-	at91rm9200dk	integratorcp	integratorap			\
-	omap1510inn	omap1610h2	omap1610inn			\
-	smdk2400	smdk2410	trab				\
-	VCMA9		versatile					\
+	at91rm9200dk	integratorcp	integratorap 	lpd7a400	\
+	mx1ads		mx1fs2		omap1510inn	omap1610h2	\
+	omap1610inn	omap730p2	scb9328		smdk2400	\
+	smdk2410	trab		VCMA9		versatile	\
 "

 #########################################################################
 ## Xscale Systems
 #########################################################################

-LIST_pxa="cradle csb226 innokom lubbock wepep250 xm250"
+LIST_pxa="cerf250 cradle csb226 innokom lubbock wepep250 xm250 xsengine"

 LIST_ixp="ixdp425"

@@ -185,6 +187,12 @@ LIST_nios="	\
 	DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20			\
 "

+#########################################################################
+## MicroBlaze Systems
+#########################################################################
+
+LIST_microblaze="suzaku"
+
 #-----------------------------------------------------------------------

 #----- for now, just run PPC by default -----
@@ -209,6 +217,7 @@ do
 	case "$arg" in
 	ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
 	arm|SA|ARM7|ARM9|pxa|ixp| \
+	microblaze| \
 	mips| \
 	nios| \
 	x86|I486)
--- a/272
+++ b/272
@@ -249,27 +249,98 @@ icecube_5100_config:			unconfig
 		}
 	@./mkconfig -a IceCube ppc mpc5xxx icecube

+PM520_config \
+PM520_DDR_config \
+PM520_ROMBOOT_config \
+PM520_ROMBOOT_DDR_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring DDR,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
+		  echo "... DDR memory revision" ; \
+		}
+	@[ -z "$(findstring ROMBOOT,$@)" ] || \
+		{ echo "#define CONFIG_BOOT_ROM" >>include/config.h ; \
+		  echo "... booting from 8-bit flash" ; \
+		}
+	@./mkconfig -a PM520 ppc mpc5xxx pm520
+
 MINI5200_config	\
 EVAL5200_config	\
 TOP5200_config:	unconfig
 	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
 	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk

-PM520_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc5xxx pm520
+Total5100_config		\
+Total5200_config		\
+Total5200_lowboot_config	\
+Total5200_Rev2_config		\
+Total5200_Rev2_lowboot_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring 5100,$@)" ] || \
+		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
+		  echo "... with MGT5100 processor" ; \
+		}
+	@[ -z "$(findstring 5200,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
+		  echo "... with MPC5200 processor" ; \
+		}
+	@[ -n "$(findstring Rev,$@)" ] || \
+		{ echo "#define CONFIG_TOTAL5200_REV 1"	>>include/config.h ; \
+		  echo "... revision 1 board" ; \
+		}
+	@[ -z "$(findstring Rev2_,$@)" ] || \
+		{ echo "#define CONFIG_TOTAL5200_REV 2"	>>include/config.h ; \
+		  echo "... revision 2 board" ; \
+		}
+	@[ -z "$(findstring lowboot_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFE000000" >board/total5200/config.tmp ; \
+		  echo "... with lowboot configuration" ; \
+		}
+	@./mkconfig -a Total5200 ppc mpc5xxx total5200
+
+TQM5200_AA_config	\
+TQM5200_AB_config	\
+TQM5200_AC_config	\
+MiniFAP_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring MiniFAP,$@)" ] || \
+		{ echo "#define CONFIG_MINIFAP"	>>include/config.h ; \
+		  echo "#define CONFIG_TQM5200_AC"	>>include/config.h ; \
+		  echo "... TQM5200_AC on MiniFAP" ; \
+		}
+	@[ -z "$(findstring AA,$@)" ] || \
+		{ echo "#define CONFIG_TQM5200_AA"	>>include/config.h ; \
+		  echo "... with 4 MB Flash, 16 MB SDRAM, 32 kB EEPROM" ; \
+		}
+	@[ -z "$(findstring AB,$@)" ] || \
+		{ echo "#define CONFIG_TQM5200_AB"	>>include/config.h ; \
+		  echo "... with 64 MB Flash, 64 MB SDRAM, 32 kB EEPROM, 512 kB SRAM" ; \
+		  echo "... with Graphics Controller"; \
+		}
+	@[ -z "$(findstring AC,$@)" ] || \
+		{ echo "#define CONFIG_TQM5200_AC"	>>include/config.h ; \
+		  echo "... with 4 MB Flash, 128 MB SDRAM" ; \
+		  echo "... with Graphics Controller"; \
+		}
+	@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200

 #########################################################################
 ## MPC8xx Systems
 #########################################################################

-AdderII_config:	unconfig
-	@./mkconfig $(@:_config=) ppc mpc8xx adderII
+Adder_config    \
+Adder87x_config \
+AdderII_config  \
+	:		unconfig
+	$(if $(findstring AdderII,$@), \
+	@echo "#define CONFIG_MPC852T" > include/config.h)
+	@./mkconfig -a Adder ppc mpc8xx adder

 ADS860_config     \
-DUET_ADS_config   \
 FADS823_config    \
 FADS850SAR_config \
 MPC86xADS_config  \
+MPC885ADS_config  \
 FADS860T_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx fads

@@ -417,19 +488,53 @@ NETPHONE_config:	unconfig
 		 }
 	@./mkconfig -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone

-xtract_NETTA = $(subst _ISDN,,$(subst _config,,$1))
+xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))

+NETTA_ISDN_6412_SWAPHOOK_config \
+NETTA_ISDN_SWAPHOOK_config \
+NETTA_6412_SWAPHOOK_config \
+NETTA_SWAPHOOK_config \
+NETTA_ISDN_6412_config \
 NETTA_ISDN_config \
+NETTA_6412_config \
 NETTA_config:		unconfig
 	@ >include/config.h
-	@[ -z "$(findstring NETTA_config,$@)" ] || \
-		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
-		 }
-	@[ -z "$(findstring NETTA_ISDN_config,$@)" ] || \
+	@[ -z "$(findstring ISDN_,$@)" ] || \
 		 { echo "#define CONFIG_NETTA_ISDN 1" >>include/config.h ; \
 		 }
+	@[ -n "$(findstring ISDN_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_ISDN" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring 6412_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_6412 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring 6412_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_6412" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring SWAPHOOK_,$@)" ] || \
+		 { echo "#define CONFIG_NETTA_SWAPHOOK 1" >>include/config.h ; \
+		 }
+	@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
+		 { echo "#undef CONFIG_NETTA_SWAPHOOK" >>include/config.h ; \
+		 }
 	@./mkconfig -a $(call xtract_NETTA,$@) ppc mpc8xx netta

+xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
+
+NETTA2_V2_config \
+NETTA2_config:		unconfig
+	@ >include/config.h
+	@[ -z "$(findstring NETTA2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA2_VERSION 1" >>include/config.h ; \
+		 }
+	@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
+		 { echo "#define CONFIG_NETTA2_VERSION 2" >>include/config.h ; \
+		 }
+	@./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
+
+NC650_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8xx nc650
+
 NX823_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx nx823

@@ -457,6 +562,30 @@ RPXClassic_config:	unconfig
 RPXlite_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx RPXlite

+RPXlite_DW_64_config  		\
+RPXlite_DW_LCD_config 		\
+RPXlite_DW_64_LCD_config 	\
+RPXlite_DW_NVRAM_config		\
+RPXlite_DW_NVRAM_64_config      \
+RPXlite_DW_NVRAM_LCD_config	\
+RPXlite_DW_NVRAM_64_LCD_config  \
+RPXlite_DW_config:         unconfig
+	@ >include/config.h
+	@[ -z "$(findstring _64,$@)" ] || \
+		{ echo "#define RPXlite_64MHz"		>>include/config.h ; \
+		  echo "... with 64MHz system clock ..."; \
+		}
+	@[ -z "$(findstring _LCD,$@)" ] || \
+		{ echo "#define CONFIG_LCD"          	>>include/config.h ; \
+		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
+		  echo "... with LCD display ..."; \
+		}
+	@[ -z "$(findstring _NVRAM,$@)" ] || \
+		{ echo "#define  CFG_ENV_IS_IN_NVRAM" 	>>include/config.h ; \
+		  echo "... with ENV in NVRAM ..."; \
+		}
+	@./mkconfig -a RPXlite_DW ppc mpc8xx RPXlite_dw
+
 rmu_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8xx rmu

@@ -531,7 +660,7 @@ wtk_config:	unconfig
 #########################################################################
 ## PPC4xx Systems
 #########################################################################
-xtract_4xx = $(subst _MODEL_BA,,$(subst _MODEL_ME,,$(subst _MODEL_HI,,$(subst _config,,$1))))
+xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))

 ADCIOP_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx adciop esd
@@ -571,6 +700,9 @@ CRAYL1_config:	unconfig
 csb272_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx csb272

+csb472_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx csb472
+
 DASA_SIM_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd

@@ -628,10 +760,13 @@ PLU405_config:	unconfig
 PMC405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd

-PPChameleonEVB_MODEL_BA_config	\
-PPChameleonEVB_MODEL_ME_config	\
-PPChameleonEVB_MODEL_HI_config	\
-PPChameleonEVB_config:	unconfig
+PPChameleonEVB_config		\
+PPChameleonEVB_BA_25_config	\
+PPChameleonEVB_ME_25_config	\
+PPChameleonEVB_HI_25_config	\
+PPChameleonEVB_BA_33_config	\
+PPChameleonEVB_ME_33_config	\
+PPChameleonEVB_HI_33_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _MODEL_BA,$@)" ] || \
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 0" >>include/config.h ; \
@@ -645,6 +780,14 @@ PPChameleonEVB_config:	unconfig
 		{ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 2" >>include/config.h ; \
 		  echo "... HIGH-END model" ; \
 		}
+	@[ -z "$(findstring _25,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_25" >>include/config.h ; \
+		  echo " SysClk = 25MHz" ; \
+		}
+	@[ -z "$(findstring _33,$@)" ] || \
+		{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>include/config.h ; \
+		  echo " SysClk = 33MHz" ; \
+		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave

 VOH405_config:	unconfig
@@ -714,6 +857,9 @@ Sandpoint8240_config: unconfig
 Sandpoint8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sandpoint

+sbc8240_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x sbc8240
+
 SL8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x sl8245

@@ -755,6 +901,13 @@ hymod_config:	unconfig
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539

+ISPAN_config		\
+ISPAN_REVB_config:	unconfig
+	@if [ "$(findstring _REVB_,$@)" ] ; then \
+		echo "#define CFG_REV_B" > include/config.h ; \
+	fi
+	@./mkconfig -a ISPAN ppc mpc8260 ispan
+
 MPC8260ADS_config	\
 MPC8260ADS_33MHz_config	\
 MPC8260ADS_40MHz_config	\
@@ -909,15 +1062,27 @@ M5282EVB_config :		unconfig
 ## MPC85xx Systems
 #########################################################################

-MPC8540ADS_config:      unconfig
+MPC8540ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads

-MPC8560ADS_config:      unconfig
+MPC8560ADS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads

-stxgp3_config:      unconfig
+stxgp3_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3

+sbc8560_config \
+sbc8560_33_config \
+sbc8560_66_config:      unconfig
+	@if [ "$(findstring _66_,$@)" ] ; then \
+		echo "#define CONFIG_PCI_66"  >>include/config.h ; \
+		echo "... 66 MHz PCI" ; \
+	else \
+		>include/config.h ; \
+		echo "... 33 MHz PCI" ; \
+	fi
+	@./mkconfig -a sbc8560 ppc mpc85xx sbc8560
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -979,10 +1144,9 @@ shannon_config	:	unconfig

 xtract_trab = $(subst _bigram,,$(subst _bigflash,,$(subst _old,,$(subst _config,,$1))))

-xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
+xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$(subst _config,,$1))))

-SX1_config :		unconfig
-	@./mkconfig $(@:_config=) arm arm925t sx1
+xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))

 integratorcp_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorcp
@@ -990,18 +1154,45 @@ integratorcp_config :	unconfig
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap

-versatile_config :	unconfig
-	@./mkconfig $(@:_config=) arm arm926ejs versatile
+lpd7a400_config \
+lpd7a404_config:	unconfig
+	@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
+
+mx1ads_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t mx1ads
+
+mx1fs2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t mx1fs2

 omap1510inn_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm925t omap1510inn

+omap5912osk_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs omap5912osk
+
 omap1610inn_config \
 omap1610inn_cs0boot_config \
 omap1610inn_cs3boot_config \
+omap1610inn_cs_autoboot_config \
 omap1610h2_config \
 omap1610h2_cs0boot_config \
-omap1610h2_cs3boot_config :	unconfig
+omap1610h2_cs3boot_config \
+omap1610h2_cs_autoboot_config:	unconfig
+	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
+		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS0 boot"; \
+	elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \
+		echo "#define CONFIG_CS_AUTOBOOT" >> ./include/config.h ; \
+		echo "... configured for CS_AUTO boot"; \
+	else \
+		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
+		echo "... configured for CS3 boot"; \
+	fi;
+	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+
+omap730p2_config \
+omap730p2_cs0boot_config \
+omap730p2_cs3boot_config :	unconfig
 	@if [ "$(findstring _cs0boot_, $@)" ] ; then \
 		echo "#define CONFIG_CS0_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS0 boot"; \
@@ -1009,7 +1200,10 @@ omap1610h2_cs3boot_config :	unconfig
 		echo "#define CONFIG_CS3_BOOT" >> ./include/config.h ; \
 		echo "... configured for CS3 boot"; \
 	fi;
-	@./mkconfig -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn
+	@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
+
+scb9328_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t scb9328

 smdk2400_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2400
@@ -1017,6 +1211,9 @@ smdk2400_config	:	unconfig
 smdk2410_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t smdk2410

+SX1_config :		unconfig
+	@./mkconfig $(@:_config=) arm arm925t sx1
+
 # TRAB default configuration:	8 MB Flash, 32 MB RAM
 trab_config \
 trab_bigram_config \
@@ -1045,6 +1242,8 @@ trab_old_config:	unconfig
 VCMA9_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm920t vcma9 mpl

+versatile_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm926ejs versatile

 #########################################################################
 ## S3C44B0 Systems
@@ -1057,15 +1256,18 @@ B2_config	:	unconfig
 ## ARM720T Systems
 #########################################################################

-impa7_config	:	unconfig
-	@./mkconfig $(@:_config=) arm arm720t impa7
-
 ep7312_config	:	unconfig
 	@./mkconfig $(@:_config=) arm arm720t ep7312

+impa7_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm720t impa7
+
 modnet50_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t modnet50

+evb4510_config :	unconfig
+	@./mkconfig $(@:_config=) arm arm720t evb4510
+
 #########################################################################
 ## AT91RM9200 Systems
 #########################################################################
@@ -1077,6 +1279,9 @@ at91rm9200dk_config	:	unconfig
 ## XScale Systems
 #########################################################################

+cerf250_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa cerf250
+
 cradle_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa cradle

@@ -1101,6 +1306,9 @@ wepep250_config	:	unconfig
 xm250_config	:	unconfig
 	@./mkconfig $(@:_config=) arm pxa xm250

+xsengine_config :	unconfig
+	@./mkconfig $(@:_config=) arm pxa xsengine
+
 #========================================================================
 # i386
 #========================================================================
@@ -1270,10 +1478,10 @@ clean:
 	rm -f board/trab/trab_fkt

 clobber:	clean
-	find . -type f \
-		\( -name .depend -o -name '*.srec' -o -name '*.bin' \) \
-		-print \
-		| xargs rm -f
+	find . -type f \( -name .depend \
+		-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
+		-print0 \
+		| xargs -0 rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
 	rm -f u-boot u-boot.map $(ALL)
--- a/268
+++ b/268
@@ -242,7 +242,7 @@ The following options need to be configured:

 		MicroBlaze based CPUs:
 		----------------------
-		CONFIG_MICROBLZE
+		CONFIG_MICROBLAZE


 - Board Type:	Define exactly one of
@@ -250,51 +250,54 @@ The following options need to be configured:
 		PowerPC based boards:
 		---------------------

-		CONFIG_ADCIOP,		CONFIG_ADS860,		CONFIG_AMX860,
-		CONFIG_AR405,		CONFIG_BAB7xx,		CONFIG_c2mon,
-		CONFIG_CANBT,		CONFIG_CCM,		CONFIG_CMI,
-		CONFIG_cogent_mpc8260,	CONFIG_cogent_mpc8xx,	CONFIG_CPCI405,
-		CONFIG_CPCI4052,	CONFIG_CPCIISER4,	CONFIG_CPU86,
-		CONFIG_CRAYL1,		CONFIG_CU824,		CONFIG_DASA_SIM,
-		CONFIG_DB64360,		CONFIG_DB64460,		CONFIG_DU405,
-		CONFIG_DUET_ADS,	CONFIG_EBONY,		CONFIG_ELPPC,
-		CONFIG_ELPT860,		CONFIG_ep8260,		CONFIG_ERIC,
-		CONFIG_ESTEEM192E,	CONFIG_ETX094,		CONFIG_EVB64260,
-		CONFIG_FADS823,		CONFIG_FADS850SAR,	CONFIG_FADS860T,
-		CONFIG_FLAGADM,		CONFIG_FPS850L,		CONFIG_FPS860L,
-		CONFIG_GEN860T,		CONFIG_GENIETV,		CONFIG_GTH,
-		CONFIG_gw8260,		CONFIG_hermes,		CONFIG_hymod,
-		CONFIG_IAD210,		CONFIG_ICU862,		CONFIG_IP860,
-		CONFIG_IPHASE4539,	CONFIG_IVML24,		CONFIG_IVML24_128,
-		CONFIG_IVML24_256,	CONFIG_IVMS8,		CONFIG_IVMS8_128,
-		CONFIG_IVMS8_256,	CONFIG_JSE,		CONFIG_LANTEC,
-		CONFIG_lwmon,		CONFIG_MBX,		CONFIG_MBX860T,
-		CONFIG_MHPC,		CONFIG_MIP405,		CONFIG_MOUSSE,
-		CONFIG_MPC8260ADS,	CONFIG_MPC8540ADS,	CONFIG_MPC8560ADS,
-		CONFIG_MUSENKI,		CONFIG_MVS1,		CONFIG_NETPHONE,
-		CONFIG_NETTA,		CONFIG_NETVIA,		CONFIG_NX823,
-		CONFIG_OCRTC,		CONFIG_ORSG,		CONFIG_OXC,
-		CONFIG_PCI405,		CONFIG_PCIPPC2,		CONFIG_PCIPPC6,
-		CONFIG_pcu_e,		CONFIG_PIP405,		CONFIG_PM826,
-		CONFIG_ppmc8260,	CONFIG_QS823,		CONFIG_QS850,
-		CONFIG_QS860T,		CONFIG_RBC823,		CONFIG_RPXClassic,
-		CONFIG_RPXlite,		CONFIG_RPXsuper,	CONFIG_rsdproto,
-		CONFIG_sacsng,		CONFIG_Sandpoint8240,	CONFIG_Sandpoint8245,
-		CONFIG_sbc8260,		CONFIG_SM850,		CONFIG_SPD823TS,
-		CONFIG_STXGP3,		CONFIG_SXNI855T,	CONFIG_TQM823L,
-		CONFIG_TQM8260,		CONFIG_TQM850L,		CONFIG_TQM855L,
-		CONFIG_TQM860L,		CONFIG_TTTech,		CONFIG_UTX8245,
-		CONFIG_V37,		CONFIG_W7OLMC,		CONFIG_W7OLMG,
-		CONFIG_WALNUT405,	CONFIG_ZPC1900,		CONFIG_ZUMA,
+		CONFIG_ADCIOP		CONFIG_GEN860T		CONFIG_PCI405
+		CONFIG_ADS860		CONFIG_GENIETV		CONFIG_PCIPPC2
+		CONFIG_AMX860		CONFIG_GTH		CONFIG_PCIPPC6
+		CONFIG_AR405		CONFIG_gw8260		CONFIG_pcu_e
+		CONFIG_BAB7xx		CONFIG_hermes		CONFIG_PIP405
+		CONFIG_c2mon		CONFIG_hymod		CONFIG_PM826
+		CONFIG_CANBT		CONFIG_IAD210		CONFIG_ppmc8260
+		CONFIG_CCM		CONFIG_ICU862		CONFIG_QS823
+		CONFIG_CMI		CONFIG_IP860		CONFIG_QS850
+		CONFIG_cogent_mpc8260	CONFIG_IPHASE4539	CONFIG_QS860T
+		CONFIG_cogent_mpc8xx	CONFIG_IVML24		CONFIG_RBC823
+		CONFIG_CPCI405		CONFIG_IVML24_128	CONFIG_RPXClassic
+		CONFIG_CPCI4052		CONFIG_IVML24_256	CONFIG_RPXlite
+		CONFIG_CPCIISER4	CONFIG_IVMS8		CONFIG_RPXsuper
+		CONFIG_CPU86		CONFIG_IVMS8_128	CONFIG_rsdproto
+		CONFIG_CRAYL1		CONFIG_IVMS8_256	CONFIG_sacsng
+		CONFIG_CSB272		CONFIG_JSE		CONFIG_Sandpoint8240
+		CONFIG_CU824		CONFIG_LANTEC		CONFIG_Sandpoint8245
+		CONFIG_DASA_SIM		CONFIG_lwmon		CONFIG_sbc8260
+		CONFIG_DB64360		CONFIG_MBX		CONFIG_sbc8560
+		CONFIG_DB64460		CONFIG_MBX860T		CONFIG_SM850
+		CONFIG_DU405		CONFIG_MHPC		CONFIG_SPD823TS
+		CONFIG_DUET_ADS		CONFIG_MIP405		CONFIG_STXGP3
+		CONFIG_EBONY		CONFIG_MOUSSE		CONFIG_SXNI855T
+		CONFIG_ELPPC		CONFIG_MPC8260ADS	CONFIG_TQM823L
+		CONFIG_ELPT860		CONFIG_MPC8540ADS	CONFIG_TQM8260
+		CONFIG_ep8260		CONFIG_MPC8560ADS	CONFIG_TQM850L
+		CONFIG_ERIC		CONFIG_MUSENKI		CONFIG_TQM855L
+		CONFIG_ESTEEM192E	CONFIG_MVS1		CONFIG_TQM860L
+		CONFIG_ETX094		CONFIG_NETPHONE		CONFIG_TTTech
+		CONFIG_EVB64260		CONFIG_NETTA		CONFIG_UTX8245
+		CONFIG_FADS823		CONFIG_NETVIA		CONFIG_V37
+		CONFIG_FADS850SAR	CONFIG_NX823		CONFIG_W7OLMC
+		CONFIG_FADS860T		CONFIG_OCRTC		CONFIG_W7OLMG
+		CONFIG_FLAGADM		CONFIG_ORSG		CONFIG_WALNUT405
+		CONFIG_FPS850L		CONFIG_OXC		CONFIG_ZPC1900
+		CONFIG_FPS860L					CONFIG_ZUMA

 		ARM based boards:
 		-----------------

-		CONFIG_AT91RM9200DK,		CONFIG_DNP1110,		CONFIG_EP7312,
-		CONFIG_H2_OMAP1610,		CONFIG_HHP_CRADLE,	CONFIG_IMPA7,
-		CONFIG_INNOVATOROMAP1510,   CONFIG_INNOVATOROMAP1610,	CONFIG_LART,
-		CONFIG_LUBBOCK,			CONFIG_SHANNON,		CONFIG_SMDK2400,
-		CONFIG_SMDK2410,		CONFIG_TRAB,		CONFIG_VCMA9,
+		CONFIG_AT91RM9200DK,		CONFIG_CERF250,		CONFIG_DNP1110,
+		CONFIG_EP7312,			CONFIG_H2_OMAP1610,	CONFIG_HHP_CRADLE,
+		CONFIG_IMPA7,		CONFIG_INNOVATOROMAP1510,	CONFIG_INNOVATOROMAP1610,
+		CONFIG_LART,			CONFIG_LPD7A400		CONFIG_LUBBOCK,
+		CONFIG_OSK_OMAP5912,		CONFIG_SHANNON,		CONFIG_P2_OMAP730,
+		CONFIG_SMDK2400,		CONFIG_SMDK2410,	CONFIG_TRAB,
+		CONFIG_VCMA9

 		MicroBlaze based boards:
 		------------------------
@@ -377,6 +380,27 @@ The following options need to be configured:
 		expect it to be in bytes, others in MB.
 		Define CONFIG_MEMSIZE_IN_BYTES to make it in bytes.

+- Serial Ports:
+		CFG_PL010_SERIAL
+
+		Define this if you want support for Amba PrimeCell PL010 UARTs.
+
+		CFG_PL011_SERIAL
+
+		Define this if you want support for Amba PrimeCell PL011 UARTs.
+
+		CONFIG_PL011_CLOCK
+
+		If you have Amba PrimeCell PL011 UARTs, set this variable to
+		the clock speed of the UARTs.
+
+		CONFIG_PL01x_PORTS
+
+		If you have Amba PrimeCell PL010 or PL011 UARTs on your board,
+		define this to a list of base addresses for each (supported)
+		port. See e.g. include/configs/versatile.h
+
+
 - Console Interface:
 		Depending on board, define exactly one serial port
 		(like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2,
@@ -538,22 +562,23 @@ The following options need to be configured:
 		CFG_CMD_ASKENV	* ask for env variable
 		CFG_CMD_AUTOSCRIPT Autoscript Support
 		CFG_CMD_BDI	  bdinfo
-		CFG_CMD_BEDBUG	  Include BedBug Debugger
+		CFG_CMD_BEDBUG	* Include BedBug Debugger
 		CFG_CMD_BMP	* BMP support
+		CFG_CMD_BSP	* Board specific commands
 		CFG_CMD_BOOTD	  bootd
-		CFG_CMD_CACHE	  icache, dcache
+		CFG_CMD_CACHE	* icache, dcache
 		CFG_CMD_CONSOLE	  coninfo
 		CFG_CMD_DATE	* support for RTC, date/time...
-		CFG_CMD_DHCP	  DHCP support
+		CFG_CMD_DHCP	* DHCP support
 		CFG_CMD_DIAG	* Diagnostics
 		CFG_CMD_DOC	* Disk-On-Chip Support
-		CFG_CMD_DTT	  Digital Therm and Thermostat
+		CFG_CMD_DTT	* Digital Therm and Thermostat
 		CFG_CMD_ECHO	* echo arguments
 		CFG_CMD_EEPROM	* EEPROM read/write support
-		CFG_CMD_ELF	  bootelf, bootvx
+		CFG_CMD_ELF	* bootelf, bootvx
 		CFG_CMD_ENV	  saveenv
 		CFG_CMD_FDC	* Floppy Disk Support
-		CFG_CMD_FAT	  FAT partition support
+		CFG_CMD_FAT	* FAT partition support
 		CFG_CMD_FDOS	* Dos diskette Support
 		CFG_CMD_FLASH	  flinfo, erase, protect
 		CFG_CMD_FPGA	  FPGA device initialization support
@@ -564,16 +589,16 @@ The following options need to be configured:
 		CFG_CMD_IMLS	  List all found images
 		CFG_CMD_IMMAP	* IMMR dump support
 		CFG_CMD_IRQ	* irqinfo
-		CFG_CMD_ITEST	* Integer/string test of 2 values
+		CFG_CMD_ITEST	  Integer/string test of 2 values
 		CFG_CMD_JFFS2	* JFFS2 Support
 		CFG_CMD_KGDB	* kgdb
 		CFG_CMD_LOADB	  loadb
 		CFG_CMD_LOADS	  loads
 		CFG_CMD_MEMORY	  md, mm, nm, mw, cp, cmp, crc, base,
-				  loop, mtest
+				  loop, loopw, mtest
 		CFG_CMD_MISC	  Misc functions like sleep etc
-		CFG_CMD_MMC	  MMC memory mapped support
-		CFG_CMD_MII	  MII utility commands
+		CFG_CMD_MMC	* MMC memory mapped support
+		CFG_CMD_MII	* MII utility commands
 		CFG_CMD_NAND	* NAND support
 		CFG_CMD_NET	  bootp, tftpboot, rarpboot
 		CFG_CMD_PCI	* pciinfo
@@ -582,7 +607,7 @@ The following options need to be configured:
 		CFG_CMD_PORTIO	* Port I/O
 		CFG_CMD_REGINFO * Register dump
 		CFG_CMD_RUN	  run command in env variable
-		CFG_CMD_SAVES	  save S record dump
+		CFG_CMD_SAVES	* save S record dump
 		CFG_CMD_SCSI	* SCSI Support
 		CFG_CMD_SDRAM	* print SDRAM configuration information
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
@@ -594,13 +619,13 @@ The following options need to be configured:
 		-----------------------------------------------
 		CFG_CMD_ALL	all

-		CFG_CMD_DFL	Default configuration; at the moment
+		CONFIG_CMD_DFL	Default configuration; at the moment
 				this is includes all commands, except
 				the ones marked with "*" in the list
 				above.

 		If you don't define CONFIG_COMMANDS it defaults to
-		CFG_CMD_DFL in include/cmd_confdefs.h. A board can
+		CONFIG_CMD_DFL in include/cmd_confdefs.h. A board can
 		override the default settings in the respective
 		include file.

@@ -650,6 +675,7 @@ The following options need to be configured:
 		CONFIG_RTC_DS1337	- use Maxim, Inc. DS1337 RTC
 		CONFIG_RTC_DS1338	- use Maxim, Inc. DS1338 RTC
 		CONFIG_RTC_DS164x	- use Dallas DS164x RTC
+		CONFIG_RTC_MAX6900	- use Maxim, Inc. MAX6900 RTC

 		Note that if the RTC uses I2C, then the I2C interface
 		must also be configured. See I2C Support, below.
@@ -739,6 +765,20 @@ The following options need to be configured:
 			CONFIG_LAN91C96_USE_32_BIT
 			Define this to enable 32 bit addressing

+		CONFIG_DRIVER_SMC91111
+		Support for SMSC's LAN91C111 chip
+
+			CONFIG_SMC91111_BASE
+			Define this to hold the physical address
+			of the device (I/O space)
+
+			CONFIG_SMC_USE_32_BIT
+			Define this if data bus is 32 bits
+
+			CONFIG_SMC_USE_IOFUNCS
+			Define this to use i/o functions instead of macros
+			(some hardware wont work with macros)
+
 - USB Support:
 		At the moment only the UHCI host controller is
 		supported (PIP405, MIP405, MPC5200); define
@@ -765,6 +805,24 @@ The following options need to be configured:
 		enabled with CFG_CMD_MMC. The MMC driver also works with
 		the FAT fs. This is enabled with CFG_CMD_FAT.

+- Journaling Flash filesystem support:
+		CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
+		CONFIG_JFFS2_NAND_DEV
+		Define these for a default partition on a NAND device
+
+		CFG_JFFS2_FIRST_SECTOR,
+		CFG_JFFS2_FIRST_BANK, CFG_JFFS2_NUM_BANKS
+		Define these for a default partition on a NOR device
+
+		CFG_JFFS_CUSTOM_PART
+		Define this to create an own partition. You have to provide a
+		function struct part_info* jffs2_part_info(int part_num)
+
+		If you define only one JFFS2 partition you may also want to
+		#define CFG_JFFS_SINGLE_PART    1
+		to disable the command chpart. This is the default when you
+		have not defined a custom partition
+
 - Keyboard Support:
 		CONFIG_ISA_KEYBOARD

@@ -878,7 +936,7 @@ The following options need to be configured:
 		If this option is set, the environment is checked for
 		a variable "splashimage". If found, the usual display
 		of logo, copyright and system information on the LCD
-		is supressed and the BMP image at the address
+		is suppressed and the BMP image at the address
 		specified in "splashimage" is loaded instead. The
 		console is redirected to the "nulldev", too. This
 		allows for a "silent" boot where a splash screen is
@@ -895,6 +953,32 @@ The following options need to be configured:
 		the malloc area (as defined by CFG_MALLOC_LEN) should
 		be at least 4MB.

+- MII/PHY support:
+		CONFIG_PHY_ADDR
+
+		The address of PHY on MII bus.
+
+		CONFIG_PHY_CLOCK_FREQ (ppc4xx)
+
+		The clock frequency of the MII bus
+
+		CONFIG_PHY_GIGE
+
+		If this option is set, support for speed/duplex
+		detection of Gigabit PHY is included.
+
+		CONFIG_PHY_RESET_DELAY
+
+		Some PHY like Intel LXT971A need extra delay after
+		reset before any MII register access is possible.
+		For such PHY, set this option to the usec delay
+		required. (minimum 300usec for LXT971A)
+
+		CONFIG_PHY_CMD_DELAY (ppc4xx)
+
+		Some PHY like Intel LXT971A need extra delay after
+		command issued before MII status register can be read
+
 - Ethernet address:
 		CONFIG_ETHADDR
 		CONFIG_ETH2ADDR
@@ -1129,6 +1213,12 @@ The following options need to be configured:
 		custom i2c_init_board() routine in boards/xxx/board.c
 		is run early in the boot sequence.

+		CONFIG_I2CFAST (PPC405GP|PPC405EP only)
+
+		This option enables configuration of bi_iic_fast[] flags
+		in u-boot bd_info structure based on u-boot environment
+		variable "i2cfast". (see also i2cfast)
+
 - SPI Support:	CONFIG_SPI

 		Enables SPI driver (so far only tested with
@@ -1779,6 +1869,16 @@ to save the current settings.
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.

+- CFG_ENV_IS_IN_NAND:
+
+	Define this if you have a NAND device which you want to use
+	for the environment.
+
+	- CFG_ENV_OFFSET:
+	- CFG_ENV_SIZE:
+
+	  These two #defines specify the offset and size of the environment
+	  area within the first NAND device.

 - CFG_SPI_INIT_OFFSET

@@ -1993,6 +2093,10 @@ Low Level (hardware related) configuration options:
 		and crc32 is the correct crc32 which the
 		area should have.

+- CONFIG_LOOPW
+		Add the "loopw" memory command. This only takes effect if
+		the memory commands are activated globally (CFG_CMD_MEM).
+
 Building the Software:
 ======================

@@ -2020,27 +2124,30 @@ is done by typing:
 where "NAME_config" is the name of one of the existing
 configurations; the following names are supported:

-	ADCIOP_config		ADS860_config		AR405_config
-	at91rm9200dk_config	CANBT_config		cmi_mpc5xx_config
-	cogent_common_config	cogent_mpc8260_config	cogent_mpc8xx_config
-	CPCI405_config		CPCIISER4_config	CU824_config
-	DUET_ADS_config		EBONY_config		ELPT860_config
-	ESTEEM192E_config	ETX094_config		FADS823_config
-	FADS850SAR_config	FADS860T_config		FPS850L_config
-	FPS860L_config		GEN860T_config		GENIETV_config
-	GTH_config		hermes_config		hymod_config
-	IP860_config		IVML24_config		IVMS8_config
-	JSE_config		LANTEC_config		lwmon_config
-	MBX860T_config		MBX_config		MPC8260ADS_config
-	MPC8540ADS_config	MPC8560ADS_config	NETVIA_config
-	omap1510inn_config	omap1610h2_config	omap1610inn_config
-	pcu_e_config		PIP405_config		QS823_config
-	QS850_config		QS860T_config		RPXlite_config
-	RPXsuper_config		rsdproto_config		Sandpoint8240_config
-	sbc8260_config		SM850_config		SPD823TS_config
-	stxgp3_config		SXNI855T_config		TQM823L_config
-	TQM850L_config		TQM855L_config		TQM860L_config
-	WALNUT405_config	ZPC1900_config
+	ADCIOP_config		FPS860L_config		omap730p2_config
+	ADS860_config		GEN860T_config		pcu_e_config
+	AR405_config		GENIETV_config		PIP405_config
+	at91rm9200dk_config	GTH_config		QS823_config
+	CANBT_config		hermes_config		QS850_config
+	cmi_mpc5xx_config	hymod_config		QS860T_config
+	cogent_common_config	IP860_config		RPXlite_config
+	cogent_mpc8260_config	IVML24_config		RPXlite_DW_config
+	cogent_mpc8xx_config	IVMS8_config		RPXsuper_config
+	CPCI405_config		JSE_config		rsdproto_config
+	CPCIISER4_config	LANTEC_config		Sandpoint8240_config
+	csb272_config		lwmon_config		sbc8260_config
+	CU824_config		MBX860T_config		sbc8560_33_config
+	DUET_ADS_config		MBX_config		sbc8560_66_config
+	EBONY_config		MPC8260ADS_config	SM850_config
+	ELPT860_config		MPC8540ADS_config	SPD823TS_config
+	ESTEEM192E_config	MPC8560ADS_config	stxgp3_config
+	ETX094_config		NETVIA_config		SXNI855T_config
+	FADS823_config		omap1510inn_config	TQM823L_config
+	FADS850SAR_config	omap1610h2_config	TQM850L_config
+	FADS860T_config		omap1610inn_config	TQM855L_config
+	FPS850L_config		omap5912osk_config	TQM860L_config
+							WALNUT405_config
+							ZPC1900_config

 Note: for some board special configuration names may exist; check if
      additional information is available from the board vendor; for
@@ -2162,6 +2269,7 @@ iminfo	- print header information for application image
 coninfo - print console devices and informations
 ide	- IDE sub-system
 loop	- infinite loop on address range
+loopw	- infinite write loop on address range
 mtest	- simple RAM test
 icache	- enable or disable instruction cache
 dcache	- enable or disable data cache
@@ -2221,6 +2329,12 @@ Some configuration options can be set using Environment Variables:
 		  This can be used to load and uncompress arbitrary
 		  data.

+  i2cfast	- (PPC405GP|PPC405EP only)
+		  if set to 'y' configures Linux I2C driver for fast
+		  mode (400kHZ). This environment variable is used in
+		  initialization code. So, for changes to be effective
+		  it must be saved and board must be reset.
+
  initrd_high	- restrict positioning of initrd images:
 		  If this variable is not set, initrd images will be
 		  copied to the highest possible address in RAM; this
--- a/board/AtmarkTechno/suzaku/suzaku.c
+++ b/board/AtmarkTechno/suzaku/suzaku.c
@@ -22,8 +22,11 @@
 * MA 02111-1307 USA
 */

-#include <common.h>
+/* This is a board specific file.  It's OK to include board specific
+ * header files */
+#include <asm/suzaku.h>

 void do_reset(void)
 {
+	*((unsigned long *)(MICROBLAZE_SYSREG_BASE_ADDR)) = MICROBLAZE_SYSREG_RECONFIGURE;
 }
--- a/board/RPXlite_dw/Makefile
+++ b/board/RPXlite_dw/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2003
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
--- a/board/RPXlite_dw/README
+++ b/board/RPXlite_dw/README
@@ -0,0 +1,96 @@
+
+After following the step of Yoo. Jonghoon and Wolfgang Denk,
+I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
+
+There are three differences between the Yoo-ported RPXlite and the RPXlite_DW.
+
+Board(in U-BOOT)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
+RPXlite				RPXlite CW		850	16MB	4MB
+RPXlite_DW			RPXlite DW		823e	64MB	16MB
+
+This fireware is specially coded for EmbeddedPlanet Co. Software Development
+Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
+
+It has the following three features:
+
+1. 64MHz/48MHz system frequence setting options.
+The default setting is 48MHz.To get a 64MHz u-boot,just add
+'64' in make command,like
+
+make RPXlite_DW_64_config
+make all
+
+2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM
+
+The default environment parameter is stored in FLASH because it is a common choice for
+environment parameter.So I make NVRAM as backup parameter storeage.The reason why I
+didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter
+home.Because of the possibility of using two firewares on this board,I didn't
+'disturb' EEPROM.To get NVRAM support,you may use the following build command:
+
+make RPXlite_DW_NVRAM_config
+make all
+
+3. LCD panel support
+
+To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of
+the fact that once you build this support and program it to FLASH,you should make sure
+you put workable kernel and ramdisk at the right place in FLASH or through NFS.
+Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this
+function is used for deployment and demo only.Pls look before you leap.
+
+To get a LCD support u-boot,you can do the following:
+
+make RPXlite_DW_LCD_config
+make all
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The basic make commands could be:
+
+make RPXlite_DW_config
+make RPXlite_DW_64_config
+make RPXlite_DW_LCD_config
+make RPXlite_DW_NVRAM_config
+
+BTW,you can combine the above features together and get a workable u-boot to meet your need.
+For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type:
+
+make RPXlite_DW_NVRAM_64_LCD_config
+make all
+
+So other combining make commands could be:
+
+make RPXlite_DW_NVRAM_64_config
+make RPXlite_DW_NVRAM_LCD_config
+make RPXlite_DW_64_LCD_config
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The boot process by "make RPXlite_DW_config" could be:
+
+U-Boot 1.1.1 (Jun  8 2004 - 11:16:30)
+
+CPU:   PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
+Board: RPXlite_DW
+DRAM:  64 MB
+FLASH: 16 MB
+*** Warning - bad CRC, using default environment
+
+In:    serial
+Out:   serial
+Err:   serial
+Net:   SCC ETHERNET
+u-boot>
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
+I would particually thank Wolfgang Denk for his nice help.
+
+Enjoy,
+
+Sam Song, samsongshu@yahoo.com.cn
+Institute of Electrical Machinery and Controls
+Shanghai University
+
+June 8,2004
--- a/board/RPXlite_dw/RPXlite_dw.c
+++ b/board/RPXlite_dw/RPXlite_dw.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2004
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Sam Song
+ * U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW
+ * Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz
+ * with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75.
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/* ------------------------------------------------------------------------- */
+static long int dram_size (long int, long int *, long int);
+/* ------------------------------------------------------------------------- */
+
+#define	_NOT_USED_	0xFFFFCC25
+
+const uint sdram_table[] =
+{
+	/*
+	 * Single Read. (Offset 00h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_,
+
+	/*
+	 * Burst Read. (Offset 08h in UPMA RAM)
+	 */
+	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
+	0x01FFCC20, 0x1FF74C20, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Single Write. (Offset 18h in UPMA RAM)
+	 */
+	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35,
+	_NOT_USED_,
+
+	/*
+	 * Burst Write. (Offset 20h in UPMA RAM)
+	 */
+	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
+	0x01FFFC24, 0x1FF74C25, /* last */
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_,
+
+	/*
+	 * Refresh. (Offset 30h in UPMA RAM)
+	 */
+	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
+	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
+	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
+	/* INIT sequence RAM WORDS
+	 * SDRAM Initialization (offset 0x36 in UPMA RAM)
+	 * The above definition uses the remaining space
+	 * to establish an initialization sequence,
+	 * which is executed by a RUN command.
+	 * The sequence is COMMAND INHIBIT(NOP),Precharge,
+	 * Load Mode Register,NOP,Auto Refresh.
+	 */
+
+	/*
+	 * Exception. (Offset 3Ch in UPMA RAM)
+	 */
+	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
+};
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: RPXlite_DW\n") ;
+	return (0) ;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size9;
+
+	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+	/* Refresh clock prescalar */
+	memctl->memc_mptpr = CFG_MPTPR ;
+
+	memctl->memc_mar  = 0x00000088;
+
+	/* Map controller banks 1 to the SDRAM bank */
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_BR1_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	/*Disable Periodic timer A. */
+
+ 	udelay(200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr  = 0x80002236; /* SDRAM bank 0 - refresh twice */
+
+	udelay(1);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	/*Enable Periodic timer A */
+
+	udelay (1000);
+
+	 /* Check Bank 0 Memory Size
+	  * try 9 column mode
+	  */
+
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+
+	udelay (1000);
+
+	return (size9);
+}
+
+void rpxlite_init (void)
+{
+	/* Enable NVRAM */
+	*((uchar *) BCSR0) |= BCSR0_ENNVRAM;
+}
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+static long int dram_size (long int mamr_value, long int *base,
+			   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size (base, maxsize));
+}
--- a/board/RPXlite_dw/config.mk
+++ b/board/RPXlite_dw/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# RPXlite dw boards : lite_dw
+#
+
+TEXT_BASE = 0xff000000
--- a/board/RPXlite_dw/flash.c
+++ b/board/RPXlite_dw/flash.c
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-Boot port on RPXlite board
+ *
+ * Some of flash control words are modified. (from 2x16bit device
+ * to 4x8bit device)
+ * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
+ * are not tested.
+ *
+ * (?) Does an RPXLite board which
+ * 	does not use AM29LV800 flash memory exist ?
+ *	I don't know...
+ */
+
+/* Yes,Yoo.They do use other FLASH for the board.
+ *
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-Boot port on RPXlite DW version board
+ *
+ * By now,it uses 4 AM29DL323DB90VI devices(4x8bit).
+ * The total FLASH has 16MB(4x4MB).
+ * I just made some necessary changes on the basis of Wolfgang and Yoo's job.
+ *
+ * June 8, 2004 */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+/*-----------------------------------------------------------------------
+ * Functions   vu_long : volatile unsigned long IN include/common.h
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 ;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* If Monitor is in the cope of FLASH,then
+	 * protect this area by default in case for
+	 * other occupation. [SAM] */
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_BASE,
+		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+	flash_info[0].size = size_b0;
+	return (size_b0);
+}
+
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000);
+		}
+	} else {
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+}
+
+void flash_print_info  (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:	printf ("AMD ");		break;
+	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+				break;
+	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+				break;
+	case FLASH_AMDL323B:    printf ("AM29DL323B (32 Mbit, bottom boot sector)\n");
+				break;
+	/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM]  */
+	default:		printf ("Unknown Chip Type\n");
+				break;
+	}
+	printf ("  Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+	short i;
+	ulong value;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0xAAA] = 0x00AA00AA ;
+	addr[0x555] = 0x00550055 ;
+	addr[0xAAA] = 0x00900090 ;
+
+	value = addr[0] ;
+	switch (value & 0x00FF00FF) {
+	case AMD_MANUFACT:             		/* AMD_MANUFACT=0x00010001 in flash.h. */
+		info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h.*/
+		break;
+	case FUJ_MANUFACT:
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);			/* no or unknown flash	*/
+	}
+
+	value = addr[2] ;			/* device ID		*/
+	switch (value & 0x00FF00FF) {
+	case (AMD_ID_LV400T & 0x00FF00FF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV400B & 0x00FF00FF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00100000;
+		break;				/* => 1 MB		*/
+	case (AMD_ID_LV800T & 0x00FF00FF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00200000;
+		break;				/* => 2 MB		*/
+	case (AMD_ID_LV800B & 0x00FF00FF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00400000;	/* Size doubled by yooth */
+		break;				/* => 4 MB		 */
+	case (AMD_ID_LV160T & 0x00FF00FF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_LV160B & 0x00FF00FF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00400000;
+		break;				/* => 4 MB		*/
+	case (AMD_ID_DL323B & 0x00FF00FF):
+		info->flash_id += FLASH_AMDL323B;
+		info->sector_count = 71;
+		info->size = 0x01000000;
+		break;                          /* => 16 MB(4x4MB)  */
+	/* AMD_ID_DL323B= 0x22532253  FLASH_AMDL323B= 0x0013
+	 * AMD_ID_DL323B could be found in <flash.h>.[SAM]
+	 * So we could get : flash_id = 0x00000013.
+	 * The first four-bit represents VEDOR ID,leaving others for FLASH ID. */
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);			/* => no or unknown flash */
+
+	}
+	/* set up sector start address table */
+	if (info->flash_id & FLASH_BTYPE) {
+	/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
+	 * it means bottom boot flash. GOOD IDEA! [SAM]
+	 */
+
+	/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00008000;
+		info->start[2] = base + 0x00010000;
+		info->start[3] = base + 0x00018000;
+		info->start[4] = base + 0x00020000;
+		info->start[5] = base + 0x00028000;
+		info->start[6] = base + 0x00030000;
+		info->start[7] = base + 0x00038000;
+
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i-7) * 0x00040000) ;
+		}
+	} else {
+		/* set sector offsets for top boot block type		*/
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00010000;
+		info->start[i--] = base + info->size - 0x00018000;
+		info->start[i--] = base + info->size - 0x00020000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00040000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned long *)(info->start[i]);
+		/* info->protect[i] = addr[4] & 1 ; */
+		/* Mask it for disorder FLASH protection **[Sam]** */
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (volatile unsigned long *)info->start[0];
+
+		*addr = 0xF0F0F0F0;	/* reset bank */
+	}
+	return (info->size);
+}
+
+int	flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	vu_long *addr = (vu_long*)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0x80808080;
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_long *)(info->start[sect]) ;
+			addr[0] = 0x30303030 ;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay (1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer (0);
+	last  = start;
+	addr = (vu_long *)(info->start[l_sect]);
+	while ((addr[0] & 0x80808080) != 0x80808080) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf ("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc ('.');
+			last = now;
+		}
+	}
+
+DONE:
+	/* reset to read mode */
+	addr = (vu_long *)info->start[0];
+	addr[0] = 0xF0F0F0F0;	/* reset bank */
+
+	printf (" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i=0, cp=wp; i<l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+		for (; i<4 && cnt>0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt==0 && i<4; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *)cp);
+		}
+
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i=0; i<4; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_word(info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp  += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i<4; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *)cp);
+	}
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+	vu_long *addr = (vu_long *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0xAAA] = 0xAAAAAAAA;
+	addr[0x555] = 0x55555555;
+	addr[0xAAA] = 0xA0A0A0A0;
+
+	*((vu_long *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
--- a/board/RPXlite_dw/u-boot.lds
+++ b/board/RPXlite_dw/u-boot.lds
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
@@ -57,17 +57,15 @@ SECTIONS
    /* the sector layout of our flash chips!	XXX FIXME XXX	*/

    cpu/mpc8xx/start.o	(.text)
-/*
-    cpu/mpc8xx/start.o	(.text)
    common/dlmalloc.o	(.text)
    lib_ppc/ppcstring.o	(.text)
    lib_generic/vsprintf.o	(.text)
    lib_generic/crc32.o		(.text)
    lib_generic/zlib.o		(.text)
-
+/* XXX ?
    . = env_offset;
-    common/environment.o(.text)
 */
+    common/environment.o(.text)

    *(.text)
    *(.fixup)
@@ -86,7 +84,7 @@ SECTIONS
  .dtors     : { *(.dtors)   }

  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
+  . = (. + 0x00FF) & 0xFFFFFF00;
  _erotext = .;
  PROVIDE (erotext = .);
  .reloc   :
@@ -136,11 +134,6 @@ SECTIONS
   *(.bss)
   *(COMMON)
  }
-  . = ALIGN(256 * 1024);
-  .ppcenv	:
-  {
-    common/environment.o (.ppcenv)
-  }
  _end = . ;
  PROVIDE (end = .);
 }
--- a/board/RPXlite_dw/u-boot.lds.debug
+++ b/board/RPXlite_dw/u-boot.lds.debug
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mpc8xx/start.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/vsprintf.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    . = env_offset;
+    common/environment.o(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/adder/Makefile
+++ b/board/adder/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/adder/adder.c
+++ b/board/adder/adder.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+/*
+ * SDRAM is single Samsung K4S643232F-T70 chip.
+ * Minimal CPU frequency is 40MHz.
+ */
+static uint sdram_table[] = {
+	/* Single read	(offset 0x00 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
+	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
+
+	/* Burst read	(offset 0x08 in UPM RAM) */
+	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
+	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
+	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
+
+	/* Single write (offset 0x18 in UPM RAM) */
+	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
+	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Burst write	(offset 0x20 in UPM RAM) */
+	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Refresh	(offset 0x30 in UPM RAM) */
+	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
+	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+
+	/* Exception	(offset 0x3C in UPM RAM) */
+	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
+};
+
+long int initdram (int board_type)
+{
+	long int msize = CFG_SDRAM_SIZE;
+	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
+
+	/* Configure SDRAM refresh */
+	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
+
+	memctl->memc_mamr = (94 << 24) | CFG_MAMR;
+	memctl->memc_mar  = 0x0;
+	udelay(200);
+
+	/* Run precharge from location 0x15 */
+	memctl->memc_mcr = 0x80002115;
+	udelay(200);
+
+	/* Run 8 refresh cycles */
+	memctl->memc_mcr = 0x80002830;
+	udelay(200);
+
+	memctl->memc_mar = 0x88;
+	udelay(200);
+
+	/* Run MRS pattern from location 0x16 */
+	memctl->memc_mcr = 0x80002116;
+	udelay(200);
+
+	return msize;
+}
+
+int checkboard( void )
+{
+	puts("Board: Adder");
+#if defined(CONFIG_MPC885_FAMILY)
+	puts("87x\n");
+#elif defined(CONFIG_MPC866_FAMILY)
+	puts("II\n");
+#endif
+
+	return 0;
+}
--- a/board/adder/config.mk
+++ b/board/adder/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Analogue&Micro Adder boards family
+#
+TEXT_BASE = 0xFE000000
--- a/board/adder/u-boot.lds
+++ b/board/adder/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp        : { *(.interp)		}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)	}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)	}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)	}
+  .rela.got      : { *(.rela.got)	}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)	}
+  .rela.bss      : { *(.rela.bss)	}
+  .rel.plt       : { *(.rel.plt)	}
+  .rela.plt      : { *(.rela.plt)	}
+  .init          : { *(.init)		}
+  .plt           : { *(.plt)		}
+  .text          :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
--- a/board/adderII/adderII.c
+++ b/board/adderII/adderII.c
@@ -1,189 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <config.h>
-#include <mpc8xx.h>
-
-/*
- * Check Board Identity:
- */
-
-int checkboard( void )
-{
-	puts("Board: ");
-	puts("AdderII(MPC852T)\n" );
-
-  	return 0;
-}
-
-#if defined( CONFIG_SDRAM_50MHZ )
-
-/******************************************************************************
-** for chip Samsung K4S643232F - T70
-** this table is for 32-50MHz operation
-*******************************************************************************/
-
-#define SDRAM_MPTPRVALUE 	0x0200
-
-#define SDRAM_MAMRVALUE0 	0x00802114   /* refresh at 32MHz */
-#define SDRAM_MAMRVALUE1 	0x00802118
-
-#define SDRAM_OR1VALUE   	0xff800e00
-#define SDRAM_BR1VALUE   	0x00000081
-
-#define SDRAM_MARVALUE		94
-
-#define SDRAM_MCRVALUE0  	0x80808105
-#define SDRAM_MCRVALUE1  	0x80808130
-
-const uint sdram_table[] = {
-
-	/* single read   (offset 0x00 in upm ram) */
-       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
-       	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
-	/* burst read    (offset 0x08 in upm ram) */
-       	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
-       	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
-       	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
-       	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
-	/* single write  (offset 0x18 in upm ram) */
-       	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
-       	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* burst write   (offset 0x20 in upm ram) */
-       	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-       	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* refresh       (offset 0x30 in upm ram) */
-       	0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-       	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
-       	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* exception     (offset 0x3C in upm ram) */
-       	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-};
-
-#else
-#error SDRAM not correctly configured
-#endif
-
-int _initsdram (uint base, uint noMbytes)
-{
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	if (noMbytes != 8) {
-		return -1;
-	}
-
-	upmconfig (UPMA, (uint *) sdram_table,
-		   sizeof (sdram_table) / sizeof (uint));
-
-	memctl->memc_mptpr = SDRAM_MPTPRVALUE;
-
-	/* Configure the refresh (mostly).  This needs to be
-	 * based upon processor clock speed and optimized to provide
-	 * the highest level of performance.  For multiple banks,
-	 * this time has to be divided by the number of banks.
-	 * Although it is not clear anywhere, it appears the
-	 * refresh steps through the chip selects for this UPM
-	 * on each refresh cycle.
-	 * We have to be careful changing
-	 * UPM registers after we ask it to run these commands.
-	 */
-
-	memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
-	memctl->memc_mar = 0x0;
-	udelay (200);
-
-	/* Now run the precharge/nop/mrs commands.
-	 */
-	memctl->memc_mcr = 0x80002115;
-	udelay (200);
-
-	/* Run 8 refresh cycles */
-	memctl->memc_mcr = 0x80002380;
-	udelay (200);
-
-	memctl->memc_mar = 0x88;
-	udelay (200);
-
-	memctl->memc_mcr = 0x80002116;
-	udelay (200);
-
-	memctl->memc_or1 = SDRAM_OR1VALUE;
-	memctl->memc_br1 = SDRAM_BR1VALUE | base;
-
-	return 0;
-}
-
-void _sdramdisable( void )
-{
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	memctl->memc_br1 = 0x00000000;
-
-	/* maybe we should turn off upma here or something */
-}
-
-int initsdram (uint base, uint * noMbytes)
-{
-	uint m = 8;
-
-	*noMbytes = m;
-
-	if (!_initsdram (base, m)) {
-		return 0;
-	} else {
-		_sdramdisable ();
-		return -1;
-	}
-}
-
-long int initdram (int board_type)
-{
-	/* AdderII: has 8MB SDRAM */
-	uint sdramsz;
-	uint m = 0;
-
-	if (!initsdram (0x00000000, &sdramsz)) {
-		m += sdramsz;
-	} else {
-		return -1;
-	}
-	return (m << 20);
-}
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX not an actual SDRAM test */
-	printf ("Test: 8MB SDRAM\n");
-
-	return (0);
-}
--- a/board/adderII/flash.c
+++ b/board/adderII/flash.c
@@ -1,501 +0,0 @@
-/*
- * (C) Copyright 2000-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-/******************************************************************************
-** Notes: AM29LV320DB - 90EI ( 32 Mbit device )
-** Sectors - Eight 8 Kb sector
-** 	   - Sixty three 64 Kb sector
-** Bottom boot sector
-******************************************************************************/
-#include <common.h>
-#include <mpc8xx.h>
-
-
-/******************************************************************************
-**	Defines
-******************************************************************************/
-#ifdef CONFIG_ADDERII
-
-#define ADDR0	0x0555
-#define ADDR1	0x02AA
-#define FLASH_WORD_SIZE unsigned short
-
-#endif
-
-#if defined( CFG_ENV_IS_IN_FLASH )
-# ifndef  CFG_ENV_ADDR
-#  define CFG_ENV_ADDR  ( CFG_FLASH_BASE + CFG_ENV_OFFSET )
-# endif
-# ifndef  CFG_ENV_SIZE
-#  define CFG_ENV_SIZE  CFG_ENV_SECT_SIZE
-# endif
-# ifndef  CFG_ENV_SECT_SIZE
-#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
-# endif
-#endif
-
-/******************************************************************************
-**	Global Parameters
-******************************************************************************/
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
-
-/******************************************************************************
-**	Function Prototypes
-******************************************************************************/
-static ulong flash_get_size( vu_long *addr, flash_info_t *info );
-
-static int write_word( flash_info_t *info, ulong dest, ulong data );
-
-static void flash_get_offsets( ulong base, flash_info_t *info );
-
-int wait_for_DQ7( flash_info_t *info, int sect );
-
-/******************************************************************************
-** Function :	flash_init
-** Param    :   void
-** Notes    :   Initializes the Flash Chip
-******************************************************************************/
-ulong flash_init (void)
-{
-	ulong size_b0 = -1;
-	int i;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	/* Set Flash to unknown */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Get the Flash Bank Size */
-
-	size_b0 = flash_get_size ((vu_long *) (CFG_FLASH_BASE),
-				  &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## UNKNOWN Flash on Bank 0 - Size = 0x%08lx = %ldMB\n",
-			size_b0, size_b0 >> 20);
-	}
-
-	/* Remap Flash according to size detected  */
-	memctl->memc_or0 = 0xFF800774;
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-
-	/* Setup Flash Sector Offsets */
-
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
-
-	/* Monitor Protection ON - default */
-
-#if ( CFG_MONITOR_BASE >= CFG_FLASH_BASE  )
-	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-		       (CFG_MONITOR_BASE + monitor_flash_len - 1),
-		       &flash_info[0]);
-#endif
-
-	/* Protect Environment Variables */
-#ifdef CFG_ENV_IS_IN_FLASH
-	flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR,
-		       (CFG_ENV_ADDR + CFG_ENV_SIZE - 1), &flash_info[0]);
-#endif
-
-	return size_b0;
-}
-
-/******************************************************************************
-** Function : flash_get_offsets
-** Param    : ulong base, flash_into_t *info
-** Notes    :
-******************************************************************************/
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	return;
-}
-
-
-/******************************************************************************
-** Function : flash_print_info
-** Param    : flash_info_t
-** Notes    :
-******************************************************************************/
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Missing or unknown flash type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:
-		printf ("AMD ");
-		break;
-	case FLASH_MAN_FUJ:
-		printf ("FUJITSU ");
-		break;
-	case FLASH_MAN_BM:
-		printf ("BRIGHT MICRO ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM320B:
-		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n", info->size >> 20,
-		info->sector_count);
-	printf ("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/******************************************************************************
-** Function : flash_get_size
-** Param    : vu_long *addr, flash_info_t *info
-** Notes    :
-******************************************************************************/
-static ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
-	short i;
-	FLASH_WORD_SIZE manu_id, dev_id;
-	ulong base = (ulong) addr;
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
-	/* Write Auto Select Command and read Manufacturer's ID and Dev ID */
-
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA;
-	addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555;
-	addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090;
-
-	manu_id = addr2[0];
-
-	switch (manu_id) {
-	case (FLASH_WORD_SIZE) AMD_MANUFACT:
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		break;
-	}
-
-	/* Read Device Id */
-	dev_id = addr2[1];
-
-	switch (dev_id) {
-	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;	/* 8 - boot sec + 63 normal */
-		info->size = 0x400000;	/* 4MByte */
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	/* Set up sector start Addresses */
-
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block
-		 ** Eight 8 Kb Boot sectors
-		 ** Sixty Three 64Kb sectors
-		 */
-		for (i = 0; i < 8; i++) {
-			info->start[i] = base + (i * 0x00002000);
-		}
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-		}
-	}
-
-	/* Reset To read mode */
-
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (ulong *) info->start[0];
-		*addr = 0xF0F0F0F0;
-	}
-	return (info->size);
-}
-
-/*******************************************************************************
-** Function : flash_erase
-** Param    : flash_info_t *info, int s_first, int s_last
-** Notes    :
-******************************************************************************/
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
-	volatile FLASH_WORD_SIZE *addr2;
-	int flag, prot, sect, l_sect;
-	int i;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
-
-			if ((info->flash_id & FLASH_VENDMASK) ==
-			    FLASH_MAN_SST) {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				for (i = 0; i < 50; i++)
-					udelay (1000);	/* wait 1 ms */
-			} else {
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			}
-			l_sect = sect;
-			/*
-			 * Wait for each sector to complete, it's more
-			 * reliable.  According to AMD Spec, you must
-			 * issue all erase commands within a specified
-			 * timeout.  This has been seen to fail, especially
-			 * if printf()s are included (for debug)!!
-			 */
-			wait_for_DQ7 (info, sect);
-		}
-	}
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-int wait_for_DQ7 (flash_info_t * info, int sect)
-{
-	ulong start, now, last;
-	volatile FLASH_WORD_SIZE *addr =
-		(FLASH_WORD_SIZE *) (info->start[sect]);
-
-	start = get_timer (0);
-	last = start;
-	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
-	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return -1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {
-			putc ('.');
-			last = now;
-		}
-	}
-	return 0;
-}
-
-
-/******************************************************************************
-** Function : write_buff
-** Param    : flash_info_t *info, uchar *src, ulong addr, ulong cnt
-** Notes    :
-******************************************************************************/
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	/* get lower word aligned address */
-	wp = (addr & ~3);
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-
-/******************************************************************************
-** Function : write_word
-** Param    : flash_info_t *info, ulong dest, ulong data
-** Notes    :
-******************************************************************************/
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE *addr2 =
-		(FLASH_WORD_SIZE *) (info->start[0]);
-	volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
-	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int i;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((volatile FLASH_WORD_SIZE *) dest) &
-	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
-		return (2);
-	}
-
-	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
-		int flag;
-
-		/* Disable interrupts which might cause a timeout here */
-		flag = disable_interrupts ();
-
-		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
-		addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts ();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
--- a/board/at91rm9200dk/Makefile
+++ b/board/at91rm9200dk/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	:= at91rm9200dk.o flash.o
+OBJS	:= at91rm9200dk.o at45.o dm9161.o flash.o
 SOBJS	:=

 $(LIB):	$(OBJS) $(SOBJS)
--- a/board/at91rm9200dk/at45.c
+++ b/board/at91rm9200dk/at45.c
@@ -25,7 +25,14 @@
 #ifdef CONFIG_HAS_DATAFLASH
 #include <dataflash.h>

-#define SPI_CLK 5000000
+#define AT91C_SPI_CLK	10000000	/* Max Value = 10MHz to be compliant to
+the Continuous Array Read function */
+
+/* AC Characteristics */
+/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
+#define DATAFLASH_TCSS	(0xC << 16)
+#define DATAFLASH_TCHS	(0x1 << 24)
+
 #define AT91C_TIMEOUT_WRDY			200000
 #define AT91C_SPI_PCS0_SERIAL_DATAFLASH		0xE     /* Chip Select 0 : NPCS0 %1110 */
 #define AT91C_SPI_PCS3_DATAFLASH_CARD		0x7     /* Chip Select 3 : NPCS3 %0111 */
@@ -50,9 +57,11 @@ void AT91F_SpiInit(void) {
 	AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;

 	/* Configure CS0 and CS3 */
-	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8);
+	*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);

-	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8);
+	*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
+	DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);

 }

--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -102,6 +102,10 @@ void nand_init (void)
 	*AT91C_PIOB_PER = AT91C_PIO_PB1;	/* enable direct output enable */
 	*AT91C_PIOB_ODR = AT91C_PIO_PB1;	/* disable output */

+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
 	if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1)
 		printf ("  No SmartMedia card inserted\n");
 #ifdef DEBUG
--- a/board/at91rm9200dk/dm9161.c
+++ b/board/at91rm9200dk/dm9161.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2003
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <at91rm9200_net.h>
+#include <net.h>
+#include <dm9161.h>
+
+#ifdef CONFIG_DRIVER_ETHER
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ *	dm9161_IsPhyConnected
+ * Description:
+ *	Reads the 2 PHY ID registers
+ * Arguments:
+ *	p_mac - pointer to AT91S_EMAC struct
+ * Return value:
+ *	TRUE - if id read successfully
+ *	FALSE- if error
+ */
+static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
+{
+	unsigned short Id1, Id2;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
+		((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
+		return TRUE;
+
+	return FALSE;
+}
+
+/*
+ * Name:
+ *	dm9161_GetLinkSpeed
+ * Description:
+ *	Link parallel detection status of MAC is checked and set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to MAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
+{
+	unsigned short stat1, stat2;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
+		return FALSE;
+
+	if (!(stat1 & DM9161_LINK_STATUS))	/* link status up? */
+		return FALSE;
+
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
+		return FALSE;
+
+	if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
+		/*set Emac for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) {
+		/*set MII for 100BaseTX and Half Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_SPD;
+		return TRUE;
+	}
+
+	if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
+		/*set MII for 10BaseT and Half Duplex  */
+		p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	dm9161_InitPhy
+ * Description:
+ *	MAC starts checking its link by using parallel detection and
+ *	Autonegotiation and the same is set in the MAC configuration registers
+ * Arguments:
+ *	p_mac - pointer to struct AT91S_EMAC
+ * Return value:
+ *	TRUE - if link status set succesfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
+{
+	UCHAR ret = TRUE;
+	unsigned short IntValue;
+
+	at91rm9200_EmacEnableMDIO (p_mac);
+
+	if (!dm9161_GetLinkSpeed (p_mac)) {
+		/* Try another time */
+		ret = dm9161_GetLinkSpeed (p_mac);
+	}
+
+	/* Disable PHY Interrupts */
+	at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
+	/* clear FDX, SPD, Link, INTR masks */
+	IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK |
+		      DM9161_LINK_MASK | DM9161_INTR_MASK);
+	at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
+	at91rm9200_EmacDisableMDIO (p_mac);
+
+	return (ret);
+}
+
+
+/*
+ * Name:
+ *	dm9161_AutoNegotiate
+ * Description:
+ *	MAC Autonegotiates with the partner status of same is set in the
+ *	MAC configuration registers
+ * Arguments:
+ *	dev - pointer to struct net_device
+ * Return value:
+ *	TRUE - if link status set successfully
+ *	FALSE - if link status not set
+ */
+static UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
+{
+	unsigned short value;
+	unsigned short PhyAnar;
+	unsigned short PhyAnalpar;
+
+	/* Set dm9161 control register */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	value &= ~DM9161_AUTONEG;	/* remove autonegotiation enable */
+	value |= DM9161_ISOLATE;	/* Electrically isolate PHY */
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/* Set the Auto_negotiation Advertisement Register */
+	/* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
+	PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
+		  DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
+		return FALSE;
+
+	/* Read the Control Register     */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+	/* Restart Auto_negotiation  */
+	value |= DM9161_RESTART_AUTONEG;
+	if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
+		return FALSE;
+
+	/*check AutoNegotiate complete */
+	udelay (10000);
+	at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
+	if (!(value & DM9161_AUTONEG_COMP))
+		return FALSE;
+
+	/* Get the AutoNeg Link partner base page */
+	if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
+		return FALSE;
+
+	if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
+		/*set MII for 100BaseTX and Full Duplex  */
+		p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
+		return TRUE;
+	}
+
+	if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
+		/*set MII for 10BaseT and Full Duplex  */
+		p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
+				~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
+				| AT91C_EMAC_FD;
+		return TRUE;
+	}
+	return FALSE;
+}
+
+
+/*
+ * Name:
+ *	at91rm92000_GetPhyInterface
+ * Description:
+ *	Initialise the interface functions to the PHY
+ * Arguments:
+ *	None
+ * Return value:
+ *	None
+ */
+void at91rm92000_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+	p_phyops->Init = dm9161_InitPhy;
+	p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
+	p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
+	p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
+}
+
+#endif	/* CONFIG_COMMANDS & CFG_CMD_NET */
+
+#endif	/* CONFIG_DRIVER_ETHER */
--- a/board/at91rm9200dk/flash.c
+++ b/board/at91rm9200dk/flash.c
@@ -42,20 +42,22 @@ typedef struct OrgDef
 /* Flash Organizations */
 OrgDef OrgAT49BV16x4[] =
 {
-	{ 8, 8*1024 }, /* 8 * 8kBytes sectors */
-	{ 2, 32*1024 }, /* 2 * 32kBytes sectors */
-	{ 30, 64*1024 } /* 30 * 64kBytes sectors */
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{  2, 32*1024 },	/*   2 * 32 kBytes sectors */
+	{ 30, 64*1024 },	/*  30 * 64 kBytes sectors */
 };

 OrgDef OrgAT49BV16x4A[] =
 {
-	{ 8, 8*1024 }, /* 8 * 8kBytes sectors */
-	{ 31, 64*1024 } /* 31 * 64kBytes sectors */
+	{  8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 31, 64*1024 },	/*  31 * 64 kBytes sectors */
 };

-
-#define FLASH_BANK_SIZE 0x200000	/* 2 MB */
-#define MAIN_SECT_SIZE  0x10000		/* 64 KB */
+OrgDef OrgAT49BV6416[] =
+{
+	{   8,  8*1024 },	/*   8 *  8 kBytes sectors */
+	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
+};

 flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];

@@ -73,13 +75,11 @@ flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
 #define CMD_ERASE_CONFIRM	0x0030
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
+#define CMD_SECTOR_UNLOCK	0x0070

 #define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
 #define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))

-#define IDENT_FLASH_ADDR1	(*(volatile u16 *)(CFG_FLASH_BASE + (0x0000555<<1)))
-#define IDENT_FLASH_ADDR2	(*(volatile u16 *)(CFG_FLASH_BASE + (0x0000AAA<<1)))
-
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
 #define BIT_PROGRAM_ERROR	0x0020
@@ -95,17 +95,17 @@ void flash_identification (flash_info_t * info)
 {
 	volatile u16 manuf_code, device_code, add_device_code;

-	IDENT_FLASH_ADDR1 = FLASH_CODE1;
-	IDENT_FLASH_ADDR2 = FLASH_CODE2;
-	IDENT_FLASH_ADDR1 = ID_IN_CODE;
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_IN_CODE;

 	manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
 	device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
 	add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));

-	IDENT_FLASH_ADDR1 = FLASH_CODE1;
-	IDENT_FLASH_ADDR2 = FLASH_CODE2;
-	IDENT_FLASH_ADDR1 = ID_OUT_CODE;
+	MEM_FLASH_ADDR1 = FLASH_CODE1;
+	MEM_FLASH_ADDR2 = FLASH_CODE2;
+	MEM_FLASH_ADDR1 = ID_OUT_CODE;

 	/* Vendor type */
 	info->flash_id = ATM_MANUFACT & FLASH_VENDMASK;
@@ -117,14 +117,36 @@ void flash_identification (flash_info_t * info)
 			(ATM_ID_BV1614A & FLASH_TYPEMASK)) {
 			info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK;
 			printf ("AT49BV1614A (16Mbit)\n");
+		} else {				/* AT49BV1614 Flash */
+			info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
+			printf ("AT49BV1614 (16Mbit)\n");
 		}

-	} else {				/* AT49BV1614 Flash */
-		info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK;
-		printf ("AT49BV1614 (16Mbit)\n");
+	} else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) {
+		info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK;
+		printf ("AT49BV6416 (64Mbit)\n");
 	}
 }

+ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks)
+{
+	int i, nb_sectors = 0;
+
+	for (i=0; i<nb_blocks; i++){
+		nb_sectors += pOrgDef[i].sector_number;
+	}
+
+	return nb_sectors;
+}
+
+void flash_unlock_sector(flash_info_t * info, unsigned int sector)
+{
+	volatile u16 *addr = (volatile u16 *) (info->start[sector]);
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	*addr = CMD_SECTOR_UNLOCK;
+}
+

 ulong flash_init (void)
 {
@@ -140,23 +162,29 @@ ulong flash_init (void)

 		flash_identification (&flash_info[i]);

-		flash_info[i].size = FLASH_BANK_SIZE;
-
 		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
 			(ATM_ID_BV1614 & FLASH_TYPEMASK)) {
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);

 			pOrgDef = OrgAT49BV16x4;
 			flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef);
-		} else {			/* AT49BV1614A Flash */
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT - 1;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT - 1);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV1614A & FLASH_TYPEMASK)){	/* AT49BV1614A Flash */

 			pOrgDef = OrgAT49BV16x4A;
 			flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef);
+		} else if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			pOrgDef = OrgAT49BV6416;
+			flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef);
+		} else {
+			flash_nb_blocks = 0;
+			pOrgDef = OrgAT49BV16x4;
 		}

+		flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks);
+		memset (flash_info[i].protect, 0, flash_info[i].sector_count);
+
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -164,15 +192,26 @@ ulong flash_init (void)

 		sector = 0;
 		start_address = flashbase;
+		flash_info[i].size = 0;

 		for (j = 0; j < flash_nb_blocks; j++) {
 			for (k = 0; k < pOrgDef[j].sector_number; k++) {
 				flash_info[i].start[sector++] = start_address;
 				start_address += pOrgDef[j].sector_size;
+				flash_info[i].size += pOrgDef[j].sector_size;
 			}
 		}

 		size += flash_info[i].size;
+
+		if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			(ATM_ID_BV6416 & FLASH_TYPEMASK)){	/* AT49BV6416 Flash */
+
+			/* Unlock all sectors at reset */
+			for (j=0; j<flash_info[i].sector_count; j++){
+				flash_unlock_sector(&flash_info[i], j);
+			}
+		}
 	}

 	/* Protect binary boot image */
@@ -215,6 +254,9 @@ void flash_print_info (flash_info_t * info)
 	case (ATM_ID_BV1614A & FLASH_TYPEMASK):
 		printf ("AT49BV1614A (16Mbit)\n");
 		break;
+	case (ATM_ID_BV6416 & FLASH_TYPEMASK):
+		printf ("AT49BV6416 (64Mbit)\n");
+		break;
 	default:
 		printf ("Unknown Chip Type\n");
 		goto Done;
@@ -234,7 +276,7 @@ void flash_print_info (flash_info_t * info)
 	}
 	printf ("\n");

-  Done:
+Done:	;
 }

 /*-----------------------------------------------------------------------
--- a/board/cerf250/Makefile
+++ b/board/cerf250/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cerf250.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/cerf250/cerf250.c
+++ b/board/cerf250/cerf250.c
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of cerf PXA Board */
+	gd->bd->bi_arch_number = 139;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa0000100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}
--- a/board/cerf250/config.mk
+++ b/board/cerf250/config.mk
@@ -0,0 +1,5 @@
+#
+# Cerf board with PXA250 cpu
+#
+#
+TEXT_BASE = 0xa3080000
--- a/board/cerf250/flash.c
+++ b/board/cerf250/flash.c
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/* Board support for 1 or 2 flash devices */
+#define FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH		ushort
+#define FLASH_PORT_WIDTHV		vu_short
+#define SWAP(x)               __swab16(x)
+#else
+#define FLASH_PORT_WIDTH		ulong
+#define FLASH_PORT_WIDTHV		vu_long
+#define SWAP(x)               __swab32(x)
+#endif
+
+#define FPW	   FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info);
+static int write_data (flash_info_t *info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			flash_get_size ((FPW *) PHYS_FLASH_2, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_2, &flash_info[i]);
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0] );
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] );
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (FPW *addr, flash_info_t *info)
+{
+	volatile FPW value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = (FPW) 0x00AA00AA;
+	addr[0x2AAA] = (FPW) 0x00550055;
+	addr[0x5555] = (FPW) 0x00900090;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[1];			/* device ID        */
+
+	switch (value) {
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x02000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x00500050;	/* clear status register cmd.   */
+			*addr = 0x00FF00FF;	/* resest to read mode          */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#else
+	wp = (addr & ~3);
+	port_width = 4;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, SWAP (data)));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t *info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}
--- a/board/cerf250/memsetup.S
+++ b/board/cerf250/memsetup.S
@@ -0,0 +1,411 @@
+/*
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/memsetup.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+DRAM_SIZE:  .long   CFG_DRAM_SIZE
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc  p15,0,\reg,c2,c0,0
+   mov  \reg,\reg
+   sub  pc,pc,#4
+   .endm
+
+
+/*
+ * 	Memory setup
+ */
+
+.globl memsetup
+memsetup:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,  [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,	[r0]
+
+	ldr		r0,	=PSSR				/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,	[r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface                                          */
+	/*                                                                  */
+	/* The sequence below is based on the recommended init steps        */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.                                                      */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
+	/*         clocks to settle. Only necessary after hard reset...     */
+	/*         FIXME: can be optimized later                            */
+	/* ---------------------------------------------------------------- */
+
+	ldr		r3,	=OSCR			/* reset the OS Timer Count to zero */
+	mov 	r2,	#0
+	str 	r2,	[r3]
+	ldr 	r4,	=0x300				/* really 0x2E1 is about 200usec,   */
+							/* so 0x300 should be plenty        */
+1:
+	ldr 	r2,	[r3]
+	cmp 	r4,	r2
+	bgt 	1b
+
+mem_init:
+
+	ldr  	r1,	=MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller        */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type                       */
+
+	/* MSC0: nCS(0,1)                                                   */
+	ldr  	r2,	=CFG_MSC0_VAL
+	str  	r2,	[r1, #MSC0_OFFSET]
+	ldr  	r2,	[r1, #MSC0_OFFSET]	/* read back to ensure      */
+						/* that data latches        */
+	/* MSC1: nCS(2,3)                                                   */
+	ldr  	r2,	=CFG_MSC1_VAL
+	str  	r2,	[r1, #MSC1_OFFSET]
+	ldr  	r2,	[r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)                                                   */
+	ldr  	r2,	=CFG_MSC2_VAL
+	str  	r2,	[r1, #MSC2_OFFSET]
+	ldr  	r2,	[r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface                               */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register                             */
+	ldr  	r2,	=CFG_MECR_VAL
+	str  	r2,	[r1, #MECR_OFFSET]
+	ldr	 	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing                             */
+	ldr  	r2,	=CFG_MCMEM0_VAL
+	str  	r2,	[r1, #MCMEM0_OFFSET]
+	ldr	 	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing                             */
+	ldr  	r2,	=CFG_MCMEM1_VAL
+	str  	r2,	[r1, #MCMEM1_OFFSET]
+	ldr	 	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
+	ldr  	r2,	=CFG_MCATT0_VAL
+	str  	r2,	[r1, #MCATT0_OFFSET]
+	ldr	 	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
+	ldr  	r2, =CFG_MCATT1_VAL
+	str  	r2, [r1, #MCATT1_OFFSET]
+	ldr	 	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
+	ldr  	r2, =CFG_MCIO0_VAL
+	str  	r2, [r1, #MCIO0_OFFSET]
+	ldr	 	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
+	ldr  	r2, =CFG_MCIO1_VAL
+	str  	r2, [r1, #MCIO1_OFFSET]
+	ldr	 	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
+	/* ---------------------------------------------------------------- */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set     */
+	/* this to power on defaults + DRI field, set SDRAM clocks free running */
+
+	ldr  	r3, =CFG_MDREFR_VAL
+	ldr  	r2, =0xFFF
+	and  	r3, r3,  r2
+
+	ldr	 	r0,	[r1, #MDREFR_OFFSET]
+	bic	 	r0, r0, r2
+	bic	 	r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
+	orr	 	r0, r0, r3
+
+	str		r0,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits               */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of      */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.                                                    */
+
+	/* FIXME: we use async mode for now                                 */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM                                         */
+	/* ---------------------------------------------------------------- */
+
+	/* set MDREFR according to user define with exception of a few bits */
+
+	ldr     r4, =CFG_MDREFR_VAL
+	ldr		r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
+					MDREFR_K2RUN |MDREFR_K2DB2)
+	and		r4, r4, r2
+	bic		r0,	r0,	r2
+	orr		r0, r0, r4
+
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+	/* Step 4b: de-assert MDREFR:SLFRSH.                                */
+
+	bic		r0, r0,	#(MDREFR_SLFRSH)
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
+
+	ldr     r4, =CFG_MDREFR_VAL
+	ldr		r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
+					MDREFR_K1FREE | MDREFR_K2FREE)
+	and		r4, r4, r2
+	orr		r0, r0, r4
+	str     r0, [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
+	ldr     r0, [r1, #MDREFR_OFFSET]
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*          configure but not enable each SDRAM partition pair.     */
+
+	ldr		r4,	=CFG_MDCNFG_VAL
+	bic		r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic		r4, r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
+	ldr     r4, [r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
+	/*          100..200 µsec.                                          */
+
+	ldr 	r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov 	r2, #0
+	str 	r2, [r3]
+	ldr 	r4, =0x300			/* really 0x2E1 is about 200usec,   */
+						/* so 0x300 should be plenty        */
+1:
+	ldr 	r2, [r3]
+	cmp 	r4, r2
+	bgt 	1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
+	/*          attempting non-burst read or write accesses to disabled */
+	/*          SDRAM, as commonly specified in the power up sequence   */
+	/*          documented in SDRAM data sheets. The address(es) used   */
+	/*          for this purpose must not be cacheable.                 */
+
+	ldr		r3,	=CFG_DRAM_BASE
+.rept 8
+	str		r2,	[r3]
+.endr
+
+	/* Step 4g: Write MDCNFG with enable bits asserted                  */
+	/*          (MDCNFG:DEx set to 1).                                  */
+
+	ldr     r3, [r1, #MDCNFG_OFFSET]
+	orr	r3,	r3,	#(MDCNFG_DE0|MDCNFG_DE1)
+	str     r3, [r1, #MDCNFG_OFFSET]
+
+	/* Step 4h: Write MDMRS.                                            */
+
+	ldr     r2, =CFG_MDMRS_VAL
+	str     r2, [r1, #MDMRS_OFFSET]
+
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller            */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov     r1, #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr     r2, =ICLR
+	str     r1, [r2]
+
+	ldr     r2, =ICMR	/* mask all interrupts at the controller    */
+	str     r1, [r2]
+
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation                                             */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off ALL on-chip peripheral clocks for re-configuration      */
+	/* Note: See label 'ENABLECLKS' for the re-enabling                 */
+	ldr     r1, =CKEN
+	mov     r2, #0
+	str     r2, [r1]
+
+
+	/* default value in case no valid rotary switch setting is found    */
+	ldr     r2, =(CCCR_L27|CCCR_M2|CCCR_N10)  /* DEFAULT: {200/200/100} */
+
+	/* ... and write the core clock config register                     */
+	ldr     r1, =CCCR
+	str     r2, [r1]
+
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager             */
+
+	ldr     r1, =OSCC
+	mov     r2, #OSCC_OON
+	str     r2, [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL         */
+	/* has settled.                                                     */
+60:
+	ldr     r2, [r1]
+	ands    r2, r2, #1
+	beq     60b
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/*                                                                  */
+	/* ---------------------------------------------------------------- */
+
+	/* Save SDRAM size */
+    ldr     r1, =DRAM_SIZE
+	str   	r8, [r1]
+
+	/* Interrupt init: Mask all interrupts                              */
+    ldr		r0,	=ICMR /* enable no sources */
+	mov 	r1,	#0
+    str 	r1,	[r0]
+
+	/* FIXME */
+
+#define NODEBUG
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov		r0,#0
+	mcr		p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr		p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr		p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov		r0,#0x80000000
+	mcr		p14,0,r0,c10,c0,0  /* dcsr */
+
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End memsetup                                                     */
+	/* ---------------------------------------------------------------- */
+
+endmemsetup:
+
+    mov     pc,	lr
--- a/board/cerf250/u-boot.lds
+++ b/board/cerf250/u-boot.lds
@@ -21,23 +21,35 @@
 * MA 02111-1307 USA
 */

-/****************************************************************************
- * FLASH Memory Map as used by FADS Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
- * | MON8xx code           | 0xFE00_0100     Reset Vector
- * +-----------------------+ 0xFE0?_????
- * | (unused)              |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +-----------------------+
- * | 			   |
- * +=======================+
- * | 			   |
- * | ...                   |
- *****************************************************************************/
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/cpc45/cpc45.c
+++ b/board/cpc45/cpc45.c
@@ -25,6 +25,7 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 #include <pci.h>
+#include <i2c.h>

 int sysControlDisplay(int digit, uchar ascii_code);
 extern void Plx9030Init(void);
@@ -49,7 +50,7 @@ int checkboard(void)
 	ulong busfreq  = get_bus_freq(0);
 	char  buf[32];

-	printf("CPC45 ");
+	puts ("CPC45  ");
 /*
 	printf("Revision %d ", revision);
 */
@@ -58,46 +59,134 @@ int checkboard(void)
 	return 0;
 }

-long int initdram(int board_type)
+long int initdram (int board_type)
 {
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
+	int m, row, col, bank, i, ref;
+	unsigned long start, end;
+	uint32_t mccr1, mccr2;
+	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+	uint8_t mber = 0;
+	unsigned int tmp;

-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
+	if (i2c_reg_read (0x50, 2) != 0x04)
+		return 0;	/* Memory type */

-	return (size);
+	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
+	row = i2c_reg_read (0x50, 3);	/* # of rows */
+	col = i2c_reg_read (0x50, 4);	/* # of columns */
+	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
+	ref  = i2c_reg_read (0x50, 12);	/* refresh rate / type */
+
+	CONFIG_READ_WORD(MCCR1, mccr1);
+	mccr1 &= 0xffff0000;
+
+	CONFIG_READ_WORD(MCCR2, mccr2);
+	mccr2 &= 0xffff0000;
+
+	start = CFG_SDRAM_BASE;
+	end = start + (1 << (col + row + 3) ) * bank - 1;
+
+	for (i = 0; i < m; i++) {
+		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+		if (i < 4) {
+			msar1  |= ((start >> 20) & 0xff) << i * 8;
+			emsar1 |= ((start >> 28) & 0xff) << i * 8;
+			mear1  |= ((end >> 20) & 0xff) << i * 8;
+			emear1 |= ((end >> 28) & 0xff) << i * 8;
+		} else {
+			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
+			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
+			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+		}
+		mber |= 1 << i;
+		start += (1 << (col + row + 3) ) * bank;
+		end += (1 << (col + row + 3) ) * bank;
+	}
+	for (; i < 8; i++) {
+		if (i < 4) {
+			msar1  |= 0xff << i * 8;
+			emsar1 |= 0x30 << i * 8;
+			mear1  |= 0xff << i * 8;
+			emear1 |= 0x30 << i * 8;
+		} else {
+			msar2  |= 0xff << (i-4) * 8;
+			emsar2 |= 0x30 << (i-4) * 8;
+			mear2  |= 0xff << (i-4) * 8;
+			emear2 |= 0x30 << (i-4) * 8;
+		}
+	}
+
+	switch(ref) {
+		case 0x00:
+		case 0x80:
+			tmp = get_bus_freq(0) / 1000000 * 15625 / 1000 - 22;
+			break;
+		case 0x01:
+		case 0x81:
+			tmp = get_bus_freq(0) / 1000000 * 3900 / 1000 - 22;
+			break;
+		case 0x02:
+		case 0x82:
+			tmp = get_bus_freq(0) / 1000000 * 7800 / 1000 - 22;
+			break;
+		case 0x03:
+		case 0x83:
+			tmp = get_bus_freq(0) / 1000000 * 31300 / 1000 - 22;
+			break;
+		case 0x04:
+		case 0x84:
+			tmp = get_bus_freq(0) / 1000000 * 62500 / 1000 - 22;
+			break;
+		case 0x05:
+		case 0x85:
+			tmp = get_bus_freq(0) / 1000000 * 125000 / 1000 - 22;
+			break;
+		default:
+			tmp = 0x512;
+			break;
+	}
+
+	CONFIG_WRITE_WORD(MCCR1, mccr1);
+	CONFIG_WRITE_WORD(MCCR2, tmp << MCCR2_REFINT_SHIFT);
+	CONFIG_WRITE_WORD(MSAR1, msar1);
+	CONFIG_WRITE_WORD(EMSAR1, emsar1);
+	CONFIG_WRITE_WORD(MEAR1, mear1);
+	CONFIG_WRITE_WORD(EMEAR1, emear1);
+	CONFIG_WRITE_WORD(MSAR2, msar2);
+	CONFIG_WRITE_WORD(EMSAR2, emsar2);
+	CONFIG_WRITE_WORD(MEAR2, mear2);
+	CONFIG_WRITE_WORD(EMEAR2, emear2);
+	CONFIG_WRITE_BYTE(MBER, mber);
+
+	return (1 << (col + row + 3) ) * bank * m;
 }

+
 /*
 * Initialize PCI Devices, report devices found.
 */
-#ifndef CONFIG_PCI_PNP

-static struct pci_config_table pci_sandpoint_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
+static struct pci_config_table pci_cpc45_config_table[] = {
+#ifndef CONFIG_PCI_PNP
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0F, PCI_ANY_ID,
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 				       PCI_ENET0_MEMADDR,
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0D, PCI_ANY_ID,
+	  pci_cfgfunc_config_device, { PCI_PLX9030_IOADDR,
+				       PCI_PLX9030_MEMADDR,
+				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+#endif /*CONFIG_PCI_PNP*/
 	{ }
 };
-#endif
-

 struct pci_controller hose = {
 #ifndef CONFIG_PCI_PNP
-	config_table: pci_sandpoint_config_table,
+	config_table: pci_cpc45_config_table,
 #endif
 };

@@ -108,6 +197,9 @@ void pci_init_board(void)
 	/* init PCI_to_LOCAL Bus BRIDGE */
 	Plx9030Init();

+	/* Clear Display */
+	DISP_CWORD = 0x0;
+
 	sysControlDisplay(0,' ');
 	sysControlDisplay(1,'C');
 	sysControlDisplay(2,'P');
@@ -130,16 +222,14 @@ void pci_init_board(void)
 * RETURNS: NA
 */

-int sysControlDisplay
-    (
-    int digit, 			/* number of digit 0..7 */
-    uchar ascii_code		/* ASCII code */
-    )
+int sysControlDisplay (int digit,	/* number of digit 0..7 */
+		       uchar ascii_code	/* ASCII code */
+		      )
 {
 	if ((digit < 0) || (digit > 7))
 		return (-1);

-	*((volatile uchar*)(DISP_CHR_RAM + digit)) = ascii_code;
+	*((volatile uchar *) (DISP_CHR_RAM + digit)) = ascii_code;

 	return (0);
 }
--- a/board/cpc45/flash.c
+++ b/board/cpc45/flash.c
@@ -41,12 +41,12 @@
 #define MAIN_SECT_SIZE  0x40000
 #define PARAM_SECT_SIZE 0x8000

-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

-static int write_data (flash_info_t *info, ulong dest, ulong *data);
-static void write_via_fpu(vu_long *addr, ulong *data);
-static __inline__ unsigned long get_msr(void);
-static __inline__ void set_msr(unsigned long msr);
+static int write_data (flash_info_t * info, ulong dest, ulong * data);
+static void write_via_fpu (vu_long * addr, ulong * data);
+static __inline__ unsigned long get_msr (void);
+static __inline__ void set_msr (unsigned long msr);

 /*---------------------------------------------------------------------*/
 #undef	DEBUG_FLASH
@@ -62,102 +62,132 @@ static __inline__ void set_msr(unsigned long msr);
 /*-----------------------------------------------------------------------
 */

-unsigned long flash_init(void)
+unsigned long flash_init (void)
 {
-    int i, j;
-    ulong size = 0;
-    uchar tempChar;
+	int i, j;
+	ulong size = 0;
+	uchar tempChar;
+	vu_long *tmpaddr;

-   /* Enable flash writes on CPC45 */
+	/* Enable flash writes on CPC45 */

-    tempChar = BOARD_CTRL;
+	tempChar = BOARD_CTRL;

-    tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);
+	tempChar |= (B_CTRL_FWPT_1 | B_CTRL_FWRE_1);

-    tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);
+	tempChar &= ~(B_CTRL_FWPT_0 | B_CTRL_FWRE_0);

-    BOARD_CTRL = tempChar;
+	BOARD_CTRL = tempChar;
+
+	__asm__ volatile ("sync\n eieio");
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+
+		addr[0] = 0x00900090;
+
+		__asm__ volatile ("sync\n eieio");
+
+		udelay (100);
+
+		DEBUGF ("Flash bank # %d:\n"
+			"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
+			"\tDevice ID @ 0x%08lX: 0x%08lX\n",
+			i,
+			(ulong) (&addr[0]), addr[0],
+			(ulong) (&addr[2]), addr[2]);


-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-	vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+		if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
+		    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T)) {

-	addr[0] = 0x00900090;
+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160F3T & FLASH_TYPEMASK);

-	DEBUGF ("Flash bank # %d:\n"
-		"\tManuf. ID @ 0x%08lX: 0x%08lX\n"
-		"\tDevice ID @ 0x%08lX: 0x%08lX\n",
-		i,
-		(ulong)(&addr[0]), addr[0],
-		(ulong)(&addr[2]), addr[2]);
+		} else if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT)
+			 && (addr[2] == addr[3])
+			 && (addr[2] == INTEL_ID_28F160C3T)) {

+			flash_info[i].flash_id =
+				(FLASH_MAN_INTEL & FLASH_VENDMASK) |
+				(INTEL_ID_28F160C3T & FLASH_TYPEMASK);

-	if ((addr[0] == addr[1]) && (addr[0] == INTEL_MANUFACT) &&
-	    (addr[2] == addr[3]) && (addr[2] == INTEL_ID_28F160F3T))
-	{
-
-	    flash_info[i].flash_id = (FLASH_MAN_INTEL & FLASH_VENDMASK) |
-				     (INTEL_ID_28F160F3T & FLASH_TYPEMASK);
-
-	} else {
-	    flash_info[i].flash_id = FLASH_UNKNOWN;
-	    addr[0] = 0xFFFFFFFF;
-	    goto Done;
-	}
-
-	DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
-
-	addr[0] = 0xFFFFFFFF;
-
-	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
-	for (j = 0; j < flash_info[i].sector_count; j++) {
-		if (j > 30) {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
-						 i * FLASH_BANK_SIZE +
-						 (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE;
 		} else {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
-						 i * FLASH_BANK_SIZE +
-						 j * MAIN_SECT_SIZE;
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			addr[0] = 0xFFFFFFFF;
+			goto Done;
 		}
-	}
-	size += flash_info[i].size;
-    }

-    /* Protect monitor and environment sectors
-     */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+		DEBUGF ("flash_id = 0x%08lX\n", flash_info[i].flash_id);
+
+		addr[0] = 0xFFFFFFFF;
+
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j > 30) {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					(MAIN_SECT_SIZE * 31) + (j -
+								 31) *
+					PARAM_SECT_SIZE;
+			} else {
+				flash_info[i].start[j] = CFG_FLASH_BASE +
+					i * FLASH_BANK_SIZE +
+					j * MAIN_SECT_SIZE;
+			}
+		}
+
+		/* unlock sectors, if 160C3T */
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			tmpaddr = (vu_long *) flash_info[i].start[j];
+
+			if ((flash_info[i].flash_id & FLASH_TYPEMASK) ==
+			    (INTEL_ID_28F160C3T & FLASH_TYPEMASK)) {
+				tmpaddr[0] = 0x00600060;
+				tmpaddr[0] = 0x00D000D0;
+				tmpaddr[1] = 0x00600060;
+				tmpaddr[1] = 0x00D000D0;
+			}
+		}
+
+		size += flash_info[i].size;
+
+		addr[0] = 0x00FF00FF;
+		addr[1] = 0x00FF00FF;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
-	      &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[1]);
 #else
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
-	      &flash_info[0]);
-#endif
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[0]);
 #endif

 #if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
 #if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_ENV_ADDR,
-	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-	      &flash_info[1]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
 #else
-    flash_protect(FLAG_PROTECT_SET,
-	      CFG_ENV_ADDR,
-	      CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-	      &flash_info[0]);
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
 #endif
 #endif

 Done:
-    return size;
+	return size;
 }

 /*-----------------------------------------------------------------------
@@ -179,6 +209,11 @@ void flash_print_info (flash_info_t * info)
 	case (INTEL_ID_28F160F3T & FLASH_TYPEMASK):
 		printf ("28F160F3T (16Mbit)\n");
 		break;
+
+	case (INTEL_ID_28F160C3T & FLASH_TYPEMASK):
+		printf ("28F160C3T (16Mbit)\n");
+		break;
+
 	default:
 		printf ("Unknown Chip Type 0x%04x\n", i);
 		goto Done;
@@ -186,7 +221,7 @@ void flash_print_info (flash_info_t * info)
 	}

 	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
+		info->size >> 20, info->sector_count);

 	printf ("  Sector Start Addresses:");
 	for (i = 0; i < info->sector_count; i++) {
@@ -194,7 +229,7 @@ void flash_print_info (flash_info_t * info)
 			printf ("\n   ");
 		}
 		printf (" %08lX%s", info->start[i],
-				info->protect[i] ? " (RO)" : "     ");
+			info->protect[i] ? " (RO)" : "     ");
 	}
 	printf ("\n");

@@ -205,7 +240,7 @@ Done:
 /*-----------------------------------------------------------------------
 */

-int	flash_erase (flash_info_t *info, int s_first, int s_last)
+int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 	int flag, prot, sect;
 	ulong start, now, last;
@@ -229,33 +264,32 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 	}

 	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
+	for (sect = s_first; sect <= s_last; ++sect) {
 		if (info->protect[sect]) {
 			prot++;
 		}
 	}

 	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
 	} else {
 		printf ("\n");
 	}

 	start = get_timer (0);
-	last  = start;
+	last = start;
 	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
+	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			vu_long *addr = (vu_long *)(info->start[sect]);
+			vu_long *addr = (vu_long *) (info->start[sect]);

 			DEBUGF ("Erase sect %d @ 0x%08lX\n",
-				sect, (ulong)addr);
+				sect, (ulong) addr);

 			/* Disable interrupts which might cause a timeout
 			 * here.
 			 */
-			flag = disable_interrupts();
+			flag = disable_interrupts ();

 			addr[0] = 0x00500050;	/* clear status register */
 			addr[0] = 0x00200020;	/* erase setup */
@@ -267,23 +301,23 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)

 			/* re-enable interrupts if necessary */
 			if (flag)
-				enable_interrupts();
+				enable_interrupts ();

 			/* wait at least 80us - let's wait 1 ms */
 			udelay (1000);

 			while (((addr[0] & 0x00800080) != 0x00800080) ||
-			       ((addr[1] & 0x00800080) != 0x00800080) ) {
-				if ((now=get_timer(start)) >
-					   CFG_FLASH_ERASE_TOUT) {
+			       ((addr[1] & 0x00800080) != 0x00800080)) {
+				if ((now = get_timer (start)) >
+				    CFG_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
-					addr[0] = 0x00B000B0; /* suspend erase */
-					addr[0] = 0x00FF00FF; /* to read mode  */
+					addr[0] = 0x00B000B0;	/* suspend erase */
+					addr[0] = 0x00FF00FF;	/* to read mode  */
 					return 1;
 				}

 				/* show that we're waiting */
-				if ((now - last) > 1000) {  /* every second  */
+				if ((now - last) > 1000) {	/* every second  */
 					putc ('.');
 					last = now;
 				}
@@ -306,7 +340,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)

 #define	FLASH_WIDTH	8	/* flash bus width in bytes */

-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong wp, cp, msr;
 	int l, rc, i;
@@ -315,16 +349,16 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	ulong *datal = &data[1];

 	DEBUGF ("Flash write_buff: @ 0x%08lx, src 0x%08lx len %ld\n",
-		addr, (ulong)src, cnt);
+		addr, (ulong) src, cnt);

 	if (info->flash_id == FLASH_UNKNOWN) {
 		return 4;
 	}

-	msr = get_msr();
-	set_msr(msr | MSR_FP);
+	msr = get_msr ();
+	set_msr (msr | MSR_FP);

-	wp = (addr & ~(FLASH_WIDTH-1));	/* get lower aligned address */
+	wp = (addr & ~(FLASH_WIDTH - 1));	/* get lower aligned address */

 	/*
 	 * handle unaligned start bytes
@@ -335,39 +369,35 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 		for (i = 0, cp = wp; i < l; i++, cp++) {
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}

-			*datal = (*datal << 8) | (*(uchar *)cp);
+			*datal = (*datal << 8) | (*(uchar *) cp);
 		}
 		for (; i < FLASH_WIDTH && cnt > 0; ++i) {
-			char tmp;
-
-			tmp = *src;
-
-			src++;
+			char tmp = *src++;

 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}

 			*datal = (*datal << 8) | tmp;
-
-			--cnt; ++cp;
+			--cnt;
+			++cp;
 		}

 		for (; cnt == 0 && i < FLASH_WIDTH; ++i, ++cp) {
 			if (i >= 4) {
 				*datah = (*datah << 8) |
-						((*datal & 0xFF000000) >> 24);
+					((*datal & 0xFF000000) >> 24);
 			}

-			*datal = (*datah << 8) | (*(uchar *)cp);
+			*datal = (*datah << 8) | (*(uchar *) cp);
 		}

-		if ((rc = write_data(info, wp, data)) != 0) {
-			set_msr(msr);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
 			return (rc);
 		}

@@ -378,19 +408,19 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 * handle FLASH_WIDTH aligned part
 	 */
 	while (cnt >= FLASH_WIDTH) {
-		*datah = *(ulong *)src;
-		*datal = *(ulong *)(src + 4);
-		if ((rc = write_data(info, wp, data)) != 0) {
-			set_msr(msr);
+		*datah = *(ulong *) src;
+		*datal = *(ulong *) (src + 4);
+		if ((rc = write_data (info, wp, data)) != 0) {
+			set_msr (msr);
 			return (rc);
 		}
-		wp  += FLASH_WIDTH;
+		wp += FLASH_WIDTH;
 		cnt -= FLASH_WIDTH;
 		src += FLASH_WIDTH;
 	}

 	if (cnt == 0) {
-		set_msr(msr);
+		set_msr (msr);
 		return (0);
 	}

@@ -399,31 +429,28 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 	 */
 	*datah = *datal = 0;
 	for (i = 0, cp = wp; i < FLASH_WIDTH && cnt > 0; ++i, ++cp) {
-		char tmp;
-
-		tmp = *src;
-
-		src++;
+		char tmp = *src++;

 		if (i >= 4) {
-			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
 		}

 		*datal = (*datal << 8) | tmp;
-
 		--cnt;
 	}

 	for (; i < FLASH_WIDTH; ++i, ++cp) {
 		if (i >= 4) {
-			*datah = (*datah << 8) | ((*datal & 0xFF000000) >> 24);
+			*datah = (*datah << 8) | ((*datal & 0xFF000000) >>
+						  24);
 		}

-		*datal = (*datal << 8) | (*(uchar *)cp);
+		*datal = (*datal << 8) | (*(uchar *) cp);
 	}

-	rc = write_data(info, wp, data);
-	set_msr(msr);
+	rc = write_data (info, wp, data);
+	set_msr (msr);

 	return (rc);
 }
@@ -434,32 +461,32 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 * 1 - write timeout
 * 2 - Flash not erased
 */
-static int write_data (flash_info_t *info, ulong dest, ulong *data)
+static int write_data (flash_info_t * info, ulong dest, ulong * data)
 {
-	vu_long *addr = (vu_long *)dest;
+	vu_long *addr = (vu_long *) dest;
 	ulong start;
 	int flag;

 	/* Check if Flash is (sufficiently) erased */
 	if (((addr[0] & data[0]) != data[0]) ||
-	    ((addr[1] & data[1]) != data[1]) ) {
+	    ((addr[1] & data[1]) != data[1])) {
 		return (2);
 	}
 	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
+	flag = disable_interrupts ();

-	addr[0] = 0x00400040;		/* write setup */
-	write_via_fpu(addr, data);
+	addr[0] = 0x00400040;	/* write setup */
+	write_via_fpu (addr, data);

 	/* re-enable interrupts if necessary */
 	if (flag)
-		enable_interrupts();
+		enable_interrupts ();

 	start = get_timer (0);

 	while (((addr[0] & 0x00800080) != 0x00800080) ||
-	       ((addr[1] & 0x00800080) != 0x00800080) ) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	       ((addr[1] & 0x00800080) != 0x00800080)) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
 			addr[0] = 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -472,22 +499,24 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data)

 /*-----------------------------------------------------------------------
 */
-static void write_via_fpu(vu_long *addr, ulong *data)
+static void write_via_fpu (vu_long * addr, ulong * data)
 {
-	__asm__ __volatile__ ("lfd  1, 0(%0)" : : "r" (data));
-	__asm__ __volatile__ ("stfd 1, 0(%0)" : : "r" (addr));
+	__asm__ __volatile__ ("lfd  1, 0(%0)"::"r" (data));
+	__asm__ __volatile__ ("stfd 1, 0(%0)"::"r" (addr));
 }
+
 /*-----------------------------------------------------------------------
 */
-static __inline__ unsigned long get_msr(void)
+static __inline__ unsigned long get_msr (void)
 {
-    unsigned long msr;
+	unsigned long msr;

-    __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
-    return msr;
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
 }

-static __inline__ void set_msr(unsigned long msr)
+static __inline__ void set_msr (unsigned long msr)
 {
-    __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
 }
--- a/board/csb472/Makefile
+++ b/board/csb472/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+#OBJS	= $(BOARD).o flash.o
+#OBJS	= $(BOARD).o strataflash.o
+OBJS	= $(BOARD).o
+
+SOBJS	= init.o
+
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/csb472/config.mk
+++ b/board/csb472/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2004
+# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Cogent CSB472 board
+#
+
+LDFLAGS += $(LINKER_UNDEFS)
+
+TEXT_BASE := 0xFFFC0000
+#TEXT_BASE := 0x00100000
+
+PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <405gp_enet.h>
+
+/*
+ * board_early_init_f: do early board initialization
+ *
+ */
+int board_early_init_f(void)
+{
+   /*-------------------------------------------------------------------------+
+   | Interrupt controller setup for the Walnut board.
+   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
+   |       IRQ 16    405GP internally generated; active low; level sensitive
+   |       IRQ 17-24 RESERVED
+   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
+   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
+   |       IRQ 27 (EXT IRQ 2) Not Used
+   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
+   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
+   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
+   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
+   | Note for Walnut board:
+   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
+   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
+   |       interrupt. The FPGA must be read to determine which device
+   |       caused the interrupt. The default setting of the FPGA clears
+   |
+   +-------------------------------------------------------------------------*/
+
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+	mtdcr (uicer, 0x00000000);   /* disable all ints */
+	mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
+	mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
+	mtdcr (uictr, 0x10000000);   /* set int trigger levels */
+	mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
+	mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+
+	mtebc (epcr, 0xa8400000);   /* EBC always driven */
+
+	return 0; /* success */
+}
+
+/*
+ * checkboard: identify/verify the board we are running
+ *
+ * Remark: we just assume it is correct board here!
+ *
+ */
+int checkboard(void)
+{
+	printf("BOARD: Cogent CSB472\n");
+
+	return 0; /* success */
+}
+
+/*
+ * initram: Determine the size of mounted DRAM
+ *
+ * Size is determined by reading SDRAM configuration registers as
+ * configured by initialization code
+ *
+ */
+long initdram (int board_type)
+{
+	ulong tot_size;
+	ulong bank_size;
+	ulong tmp;
+
+	tot_size = 0;
+
+	mtdcr (memcfga, mem_mb0cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb1cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb2cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	mtdcr (memcfga, mem_mb3cf);
+	tmp = mfdcr (memcfgd);
+	if (tmp & 0x00000001) {
+		bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
+		tot_size += bank_size;
+	}
+
+	return tot_size;
+}
+
+/*
+ * last_stage_init: final configurations (such as PHY etc)
+ *
+ */
+int last_stage_init(void)
+{
+	/* initialize the PHY */
+	miiphy_reset(CONFIG_PHY_ADDR);
+	miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
+			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);	/* AUTO neg */
+	miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08);	/* LEDs     */
+
+	return 0; /* success */
+}
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -0,0 +1,212 @@
+/******************************************************************************
+ *
+ *	 This source code has been made available to you by IBM on an AS-IS
+ *	 basis.	 Anyone receiving this source is licensed under IBM
+ *	 copyrights to use it in any way he or she deems fit, including
+ *	 copying it, modifying it, compiling it, and redistributing it either
+ *	 with or without modifications.	 No license under IBM patents or
+ *	 patent applications is to be implied by the copyright license.
+ *
+ *	 Any user of this software should understand that IBM cannot provide
+ *	 technical support for this software and will not be responsible for
+ *	 any consequences resulting from the use of this software.
+ *
+ *	 Any person who transfers this source code or any derivative work
+ *	 must include the IBM copyright notice, this paragraph, and the
+ *	 preceding two paragraphs in the transferred software.
+ *
+ *	 COPYRIGHT   I B M   CORPORATION 1995
+ *	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ *****************************************************************************/
+#include <config.h>
+#include <ppc4xx.h>
+
+#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#define LI32(reg,val) \
+	addis   reg,0,val@h;\
+	ori     reg,reg,val@l
+
+#define WDCR_EBC(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   ebccfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   ebccfgd,r4
+
+#define WDCR_SDRAM(reg,val) \
+	addi    r4,0,reg;\
+	mtdcr   memcfga,r4;\
+	addis   r4,0,val@h;\
+	ori     r4,r4,val@l;\
+	mtdcr   memcfgd,r4
+
+/******************************************************************************
+ * Function:	ext_bus_cntlr_init
+ *
+ * Description:	Configures EBC Controller and a few basic chip selects.
+ *
+ *		CS0 is setup to get the Boot Flash out of the addresss range
+ *		so that we may setup a stack.  CS7 is setup so that we can
+ *		access and reset the hardware watchdog.
+ *
+ *		IMPORTANT: For pass1 this code must run from
+ *		cache since you can not reliably change a peripheral banks
+ *		timing register (pbxap) while running code from that bank.
+ *		For ex., since we are running from ROM on bank 0, we can NOT
+ *		execute the code that modifies bank 0 timings from ROM, so
+ *		we run it from cache.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	ext_bus_cntlr_init
+	.type	ext_bus_cntlr_init, @function
+ext_bus_cntlr_init:
+	mflr	r0
+	/********************************************************************
+	 * Prefetch entire ext_bus_cntrl_init function into the icache.
+	 * This is necessary because we are going to change the same CS we
+	 * are executing from.  Otherwise a CPU lockup may occur.
+	 *******************************************************************/
+	bl	..getAddr
+..getAddr:
+	mflr	r3			/* get address of ..getAddr */
+
+	/* Calculate number of cache lines for this function */
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	mtctr	r4
+..ebcloop:
+	icbt	r0, r3			/* prefetch cache line for addr in r3*/
+	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	bdnz	..ebcloop		/* continue for $CTR cache lines */
+
+	/********************************************************************
+	 * Delay to ensure all accesses to ROM are complete before changing
+	 * bank 0 timings. 200usec should be enough.
+	 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
+	 *******************************************************************/
+	addis	r3, 0, 0x0
+	ori	r3, r3, 0xA000		/* wait 200us from reset */
+	mtctr	r3
+..spinlp:
+	bdnz	..spinlp		/* spin loop */
+
+	/********************************************************************
+	 * SETUP CPC0_CR0
+	 *******************************************************************/
+	LI32(r4, 0x00c01030)
+	mtdcr	cntrl0, r4
+
+	/********************************************************************
+	 * Setup CPC0_CR1: Change PCIINT signal to PerWE
+	 *******************************************************************/
+	mfdcr	r4, cntrl1
+	ori	r4, r4, 0x4000
+	mtdcr	cntrl1, r4
+
+	/********************************************************************
+	 * Setup External Bus Controller (EBC).
+	 *******************************************************************/
+	WDCR_EBC(epcr, 0xd84c0000)
+	/********************************************************************
+	 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb0ap, 0x03055200)*/
+	/*WDCR_EBC(pb0ap, 0x04055200)*/
+	WDCR_EBC(pb0ap, 0x08055200)
+	WDCR_EBC(pb0cr, 0xff87a000)
+	/********************************************************************
+	 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
+	 *******************************************************************/
+	/*WDCR_EBC(pb3ap, 0x07869200)*/
+	WDCR_EBC(pb3ap, 0x04055200)
+	WDCR_EBC(pb3cr, 0xff01c000)
+	/********************************************************************
+	 * Memory Bank 1,2,4-7 (Unused) initialization
+	 *******************************************************************/
+	WDCR_EBC(pb1ap, 0)
+	WDCR_EBC(pb1cr, 0)
+	WDCR_EBC(pb2ap, 0)
+	WDCR_EBC(pb2cr, 0)
+	WDCR_EBC(pb4ap, 0)
+	WDCR_EBC(pb4cr, 0)
+	WDCR_EBC(pb5ap, 0)
+	WDCR_EBC(pb5cr, 0)
+	WDCR_EBC(pb6ap, 0)
+	WDCR_EBC(pb6cr, 0)
+	WDCR_EBC(pb7ap, 0)
+	WDCR_EBC(pb7cr, 0)
+
+	/* We are all done */
+	mtlr	r0			/* Restore link register */
+	blr				/* Return to calling function */
+.Lfe0:	.size	ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
+/* end ext_bus_cntlr_init() */
+
+/******************************************************************************
+ * Function:	sdram_init
+ *
+ * Description:	Configures SDRAM memory banks.
+ *
+ * Notes:	Does NOT use the stack.
+ *****************************************************************************/
+	.section ".text"
+	.align	2
+	.globl	sdram_init
+	.type	sdram_init, @function
+sdram_init:
+
+	/*
+	 * Disable memory controller to allow
+	 * values to be changed.
+	 */
+	WDCR_SDRAM(mem_mcopt1, 0x00000000)
+
+	/*
+	 * Configure Memory Banks
+	 */
+	WDCR_SDRAM(mem_mb0cf, 0x00062001)
+	WDCR_SDRAM(mem_mb1cf, 0x00000000)
+	WDCR_SDRAM(mem_mb2cf, 0x00000000)
+	WDCR_SDRAM(mem_mb3cf, 0x00000000)
+
+	/*
+	 * Set up SDTR1 (SDRAM Timing Register)
+	 */
+	WDCR_SDRAM(mem_sdtr1, 0x00854009)
+
+	/*
+	 * Set RTR (Refresh Timing Register)
+	 */
+	WDCR_SDRAM(mem_rtr,   0x10000000)
+	/* WDCR_SDRAM(mem_rtr,   0x05f00000) */
+
+	/********************************************************************
+	 * Delay to ensure 200usec have elapsed since reset. Assume worst
+	 * case that the core is running 200Mhz:
+	 *	  200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
+	 *******************************************************************/
+	addis   r3, 0, 0x0000
+	ori     r3, r3, 0xA000		/* Wait >200us from reset */
+	mtctr   r3
+..spinlp2:
+	bdnz    ..spinlp2		/* spin loop */
+
+	/********************************************************************
+	 * Set memory controller options reg, MCOPT1.
+	 *******************************************************************/
+	WDCR_SDRAM(mem_mcopt1,0x80800000)
+
+..sdri_done:
+	blr				/* Return to calling function */
+.Lfe1:	.size	sdram_init,.Lfe1-sdram_init
+/* end sdram_init() */
--- a/board/csb472/u-boot.lds
+++ b/board/csb472/u-boot.lds
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  .resetvec 0xFFFFFFFC :
+  {
+    *(.resetvec)
+  } = 0xffff
+
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/ppc4xx/start.o	(.text)
+    board/csb472/init.o	(.text)
+    cpu/ppc4xx/kgdb.o	(.text)
+    cpu/ppc4xx/traps.o	(.text)
+    cpu/ppc4xx/interrupts.o	(.text)
+    cpu/ppc4xx/serial.o	(.text)
+    cpu/ppc4xx/cpu_init.o	(.text)
+    cpu/ppc4xx/speed.o	(.text)
+    cpu/ppc4xx/405gp_enet.o	(.text)
+    common/dlmalloc.o	(.text)
+    lib_generic/crc32.o		(.text)
+
+    lib_ppc/extable.o	(.text)
+    lib_ppc/board.o	(.text)
+    lib_generic/zlib.o	(.text)
+/*    . = env_offset;*/
+/*    common/environment.o(.text)*/
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -31,26 +31,9 @@

 /* ------------------------------------------------------------------------- */

-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
 /* Prototypes */
 int gunzip(void *, int, unsigned char *, int *);

-
 int board_early_init_f (void)
 {
 	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
@@ -60,13 +43,13 @@ int board_early_init_f (void)
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
 	 * IRQ 16    405GP internally generated; active low; level sensitive
 	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
+	 * IRQ 25 (EXT IRQ 0)
+	 * IRQ 26 (EXT IRQ 1)
+	 * IRQ 27 (EXT IRQ 2)
+	 * IRQ 28 (EXT IRQ 3)
+	 * IRQ 29 (EXT IRQ 4)
+	 * IRQ 30 (EXT IRQ 5)
+	 * IRQ 31 (EXT IRQ 6)
 	 */
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
@@ -84,11 +67,9 @@ int board_early_init_f (void)
 #else
 	mtebc (epcr, 0x28400000); /* ebc in high-z */
 #endif
-
 	return 0;
 }

-
 /* ------------------------------------------------------------------------- */

 int misc_init_f (void)
@@ -96,11 +77,15 @@ int misc_init_f (void)
 	return 0;  /* dummy implementation */
 }

+extern flash_info_t flash_info[];	/* info for FLASH chips */

 int misc_init_r (void)
 {
-#if 0 /* test-only */
 	DECLARE_GLOBAL_DATA_PTR;
+
+	/* adjust flash start and size as well as the offset */
+	gd->bd->bi_flashstart = 0 - flash_info[0].size;
+	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
 #if 0
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
@@ -177,7 +162,6 @@ int misc_init_r (void)
 	udelay(1000); /* wait 1ms */
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */
-
 #endif

 #if 0
@@ -192,12 +176,9 @@ int misc_init_r (void)
 	*duart0_mcr = 0x08;
 	*duart1_mcr = 0x08;
 #endif
-#endif
-
 	return (0);
 }

-
 /*
 * Check Board Identity:
 */
@@ -266,8 +247,13 @@ nand_init(void)
 {
 	ulong totlen = 0;

-#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) || \
+/*
+	The HI model is equipped with a large block NAND chip not supported yet
+	by U-Boot
    (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+*/
+
+#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
 	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
 	totlen += nand_probe (CFG_NAND0_BASE);
 #endif	/* CONFIG_PPCHAMELEON_MODULE_ME, CONFIG_PPCHAMELEON_MODULE_HI */
@@ -278,3 +264,39 @@ nand_init(void)
 	printf ("%4lu MB\n", totlen >>20);
 }
 #endif
+
+#ifdef CONFIG_CFB_CONSOLE
+# ifdef CONFIG_CONSOLE_EXTRA_INFO
+# include <video_fb.h>
+extern GraphicDevice smi;
+
+void video_get_info_str (int line_number, char *info)
+{
+	uint pvr = get_pvr ();
+
+	/* init video info strings for graphic console */
+	switch (line_number) {
+	case 1:
+		switch (pvr) {
+		case PVR_405EP_RB:
+			sprintf (info, " IBM PowerPC 405EP Rev. B");
+			break;
+		default:
+			sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
+			break;
+		}
+		return;
+	case 2:
+		sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
+		return;
+	case 3:
+		sprintf (info, " %s", smi.modeIdent);
+		return;
+	}
+
+	/* no more info lines */
+	*info = 0;
+	return;
+}
+# endif	/* CONFIG_CONSOLE_EXTRA_INFO */
+#endif	/* CONFIG_CFB_CONSOLE */
--- a/board/dave/PPChameleonEVB/flash.c
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -44,12 +44,15 @@ unsigned long flash_init (void)
 #ifdef __DEBUG_START_FROM_SRAM__
 	return CFG_DUMMY_FLASH_SIZE;
 #else
-	unsigned long size_b0;
+	unsigned long size;
 	int i;
 	uint pbcr;
-	unsigned long base_b0;
+	unsigned long base;
 	int size_val = 0;

+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+	debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
+
 	/* Init: no FLASHes known */
 	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
@@ -57,22 +60,26 @@ unsigned long flash_init (void)

 	/* Static FLASH Bank configuration here - FIXME XXX */

-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+	debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
+	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);

 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
+			size, size<<20);
 	}

+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+
 	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
+	flash_get_offsets (-size, &flash_info[0]);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);

 	/* Re-do sizing to get full correct info */
 	mtdcr(ebccfga, pb0cr);
 	pbcr = mfdcr(ebccfgd);
 	mtdcr(ebccfga, pb0cr);
-	base_b0 = -size_b0;
-	switch (size_b0) {
+	base = -size;
+	switch (size) {
 	case 1 << 20:
 		size_val = 0;
 		break;
@@ -89,8 +96,9 @@ unsigned long flash_init (void)
 		size_val = 4;
 		break;
 	}
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
+	pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
 	mtdcr(ebccfgd, pbcr);
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);

 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
@@ -98,8 +106,9 @@ unsigned long flash_init (void)
 			    0xffffffff,
 			    &flash_info[0]);

-	flash_info[0].size = size_b0;
+	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
+	flash_info[0].size  = size;

-	return (size_b0);
+	return (size);
 #endif
 }
--- a/board/dave/common/flash.c
+++ b/board/dave/common/flash.c
@@ -220,6 +220,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
 	ulong base = (ulong)addr;
 	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;

+	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
+
 	/* Write auto select command: read Manufacturer ID */
 	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
 	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -104,17 +104,17 @@ int checkboard (void)
 		      CFG_PCMCIA_ATTR_BASE, /* Hi */
 		      0x3D000017,           /* Lo0 */
 		      0x3D200017);          /* Lo1 */
-#endif
+#endif	/* 0 */
 	write_one_tlb(22,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
 		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
 		      0x3E000017,           /* Lo0 */
 		      0x3E200017);          /* Lo1 */
+#endif	/* CONFIG_IDE_PCMCIA */

 	/* Release reset of ethernet PHY chips */
 	/* Always do this, because linux does not know about it */
 	*phy = 3;

 	return 0;
-#endif
 }
--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@@ -250,10 +250,6 @@ int misc_init_r (void)
 		 eerev.etheraddr[4], eerev.etheraddr[5]);
 	setenv ("ethaddr", buf);

-	/* set serial console as default */
-	if ((ptr = getenv ("console")) == NULL)
-		setenv ("console", "serial");
-
 	/* print actual board identification */
 	printf ("Ident: %s  Ser %s  Rev %c%c\n",
 		eerev.board, (char *) &eerev.serial,
--- a/board/evb4510/Makefile
+++ b/board/evb4510/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= evb4510.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/evb4510/config.mk
+++ b/board/evb4510/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+# Curt Brune <curt@cucy.com>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x007d0000
--- a/board/evb4510/evb4510.c
+++ b/board/evb4510/evb4510.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+#ifdef CONFIG_EVB4510
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	icache_enable();
+
+	/* address for the kernel command line */
+	gd->bd->bi_boot_params = 0x800;
+
+	/* enable board LEDs for output */
+	PUT_REG( REG_IOPDATA, 0x0);
+	PUT_REG( REG_IOPMODE, 0xFFFF);
+	PUT_REG( REG_IOPDATA, 0xFF);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+#if CONFIG_NR_DRAM_BANKS == 2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+#endif
+	return 0;
+}
+
+#endif
--- a/board/evb4510/flash.c
+++ b/board/evb4510/flash.c
@@ -0,0 +1,540 @@
+/*
+ *
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <flash.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+typedef enum {
+	FLASH_DEV_U9_512KB = 0,
+	FLASH_DEV_U7_2MB = 1
+} FLASH_DEV;
+
+#define FLASH_DQ7		(0x80)
+#define FLASH_DQ5		(0x20)
+
+#define PROG_ADDR		(0xAAA)
+#define SETUP_ADDR		(0xAAA)
+#define ID_ADDR			(0xAAA)
+#define UNLOCK_ADDR1		(0xAAA)
+#define UNLOCK_ADDR2		(0x555)
+
+#define UNLOCK_CMD1		(0xAA)
+#define UNLOCK_CMD2		(0x55)
+#define ERASE_SUSPEND_CMD	(0xB0)
+#define ERASE_RESUME_CMD	(0x30)
+#define RESET_CMD		(0xF0)
+#define ID_CMD			(0x90)
+#define SELECT_CMD		(0x90)
+#define CHIPERASE_CMD		(0x10)
+#define BYPASS_CMD		(0x20)
+#define SECERASE_CMD		(0x30)
+#define PROG_CMD		(0xa0)
+#define SETUP_CMD		(0x80)
+
+#if 0
+#define WRITE_UNLOCK(addr) { \
+	PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \
+	PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \
+}
+
+/* auto select command */
+#define CMD_ID(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, ID_CMD); \
+}
+
+#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, RESET_CMD); \
+}
+
+#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( addr, SECERASE_CMD);
+
+#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+	WRITE_UNLOCK(base); \
+	PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD);
+
+/* prepare for bypass programming */
+#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \
+	PUT__U8( addr + ID_ADDR, 0x20); \
+}
+
+/* terminate bypass programming */
+#define CMD_BYPASS_RESET(addr) { \
+	PUT__U8(addr, 0x90); \
+	PUT__U8(addr, 0x00); \
+}
+#endif
+
+inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		PUT__U8 (base + 0xAAA, 0xAA);
+		PUT__U8 (base + 0x555, 0x55);
+		break;
+	case FLASH_DEV_U9_512KB:
+		PUT__U8 (base + 0x555, 0xAA);
+		PUT__U8 (base + 0x2AA, 0x55);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SELECT_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SELECT_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, RESET_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, RESET_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (addr, SECERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, SETUP_CMD);
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base, CHIPERASE_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base)
+{
+	switch (dev) {
+	case FLASH_DEV_U7_2MB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0xAAA, BYPASS_CMD);
+		break;
+	case FLASH_DEV_U9_512KB:
+		FLASH_CMD_UNLOCK (dev, base);
+		PUT__U8 (base + 0x555, BYPASS_CMD);
+		break;
+	}
+}
+
+inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base)
+{
+	PUT__U8 (base, SELECT_CMD);
+	PUT__U8 (base, 0x0);
+}
+
+/* poll for flash command completion */
+static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut)
+{
+	u32 done = 0;
+	ulong t0;
+
+	u16 error = 0;
+	volatile u16 flashData;
+
+	data = data & 0xFF;
+	t0 = get_timer (0);
+	while (get_timer (t0) < timeOut) {
+		/*	for( i = 0; i < POLL_LOOPS; i++) { */
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+
+		/*  FLASH_DQ7 = Data? */
+		if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) {
+			done = 1;
+			break;
+		}
+
+		/*  Check Timeout (FLASH_DQ5==1) */
+		if (flashData & FLASH_DQ5) {
+			/*  Read the Data */
+			flashData = GET__U8 (addr);
+
+			/*  FLASH_DQ7 = Data? */
+			if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) {
+				printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n");
+				error = ERR_PROG_ERROR;
+			}
+			FLASH_CMD_RESET (dev, addr);
+			done = 1;
+			break;
+		}
+		/*  spin delay */
+		udelay (10);
+	}
+
+
+	/*  error update */
+	if (!done) {
+		printf ("_flash_poll(): Timeout\n");
+		error = ERR_TIMOUT;
+	}
+
+	/*  Check the data */
+	if (!error) {
+		/*  Read the Data */
+		flashData = GET__U8 (addr);
+		if (flashData != data) {
+			error = ERR_PROG_ERROR;
+			printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n",
+				flashData, data);
+		}
+	}
+
+	return error;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int _flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+	int sect, prot = 0;
+
+	for (sect = s_first; sect <= s_last; sect++)
+		if (info->protect[sect]) {
+			printf ("  Flash sector %d protected.\n", sect);
+			prot++;
+		}
+	return prot;
+}
+
+static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId)
+{
+
+	u32 baseAddr = base | CACHE_DISABLE_MASK;
+	u8 vendorId, deviceId;
+
+	/*	printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */
+
+	/* Send auto select command and read manufacturer info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+	vendorId = GET__U8 (baseAddr);
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* Send auto select command and read device info */
+	FLASH_CMD_SELECT (dev, baseAddr);
+
+	if (dev == FLASH_DEV_U7_2MB) {
+		deviceId = GET__U8 (baseAddr + 2);
+	} else if (dev == FLASH_DEV_U9_512KB) {
+		deviceId = GET__U8 (baseAddr + 1);
+	} else {
+		return 0;
+	}
+
+	FLASH_CMD_RESET (dev, baseAddr);
+
+	/* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n",
+		vendorId, deviceId);
+	 */
+
+	return (vendorId == venId) && (deviceId == devId);
+
+}
+
+/******************************************************************************
+ *
+ * Public u-boot interface functions below
+ *
+ *****************************************************************************/
+
+/***************************************************************************
+ *
+ * Flash initialization
+ *
+ * This board has two banks of flash, but the base addresses depend on
+ * how the board is jumpered.
+ *
+ * The two flash types are:
+ *
+ *   AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB
+ *
+ *   AMD Am29LV040B  (512KB)  sectors: 8x64KB
+ *****************************************************************************/
+
+unsigned long flash_init (void)
+{
+	flash_info_t *info;
+	u16 i;
+	u32 flashtest;
+	s16 amd160 = -1;
+	u32 amd160base = 0;
+
+#if CFG_MAX_FLASH_BANKS == 2
+	s16 amd040 = -1;
+	u32 amd040base = 0;
+#endif
+
+	/* configure PHYS_FLASH_1 */
+	if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) {
+		amd160 = 0;
+		amd160base = PHYS_FLASH_1;
+#if CFG_MAX_FLASH_BANKS == 1
+	}
+#else
+		if (_detectFlash
+		    (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) {
+			amd040 = 1;
+			amd040base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	} else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) {
+		amd040 = 0;
+		amd040base = PHYS_FLASH_1;
+		if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) {
+			amd160 = 1;
+			amd160base = PHYS_FLASH_2;
+		} else {
+			printf (__FUNCTION__
+				"(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+				PHYS_FLASH_2);
+		}
+	}
+#endif
+	else {
+		printf (__FUNCTION__
+			"(): Unable to detect PHYS_FLASH_1: 0x%08x\n",
+			PHYS_FLASH_1);
+	}
+
+	/* Configure AMD Am29LV160DB (2MB) */
+	info = &flash_info[amd160];
+	info->flash_id = FLASH_DEV_U7_2MB;
+	info->sector_count = 35;
+	info->size = 2 * 1024 * 1024;	/* 2MB */
+	/* 1*16K Boot Block
+	   2*8K Parameter Block
+	   1*32K Small Main Block */
+	info->start[0] = amd160base;
+	info->start[1] = amd160base + 0x4000;
+	info->start[2] = amd160base + 0x6000;
+	info->start[3] = amd160base + 0x8000;
+	for (i = 1; i < info->sector_count; i++)
+		info->start[3 + i] = amd160base + i * (64 * 1024);
+
+	for (i = 0; i < info->sector_count; i++) {
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd160base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+
+	/*
+	 * protect monitor and environment sectors in 2MB flash
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       amd160base, amd160base + monitor_flash_len - 1, info);
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info);
+
+#if CFG_MAX_FLASH_BANKS == 2
+	/* Configure AMD Am29LV040B (512KB) */
+	info = &flash_info[amd040];
+	info->flash_id = FLASH_DEV_U9_512KB;
+	info->sector_count = 8;
+	info->size = 512 * 1024;	/* 512KB, 8 x 64KB */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = amd040base + i * (64 * 1024);
+		/* Write auto select command sequence and query sector protection */
+		FLASH_CMD_SELECT (info->flash_id,
+				  info->start[i] | CACHE_DISABLE_MASK);
+		flashtest =
+			GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK));
+		FLASH_CMD_RESET (info->flash_id,
+				 amd040base | CACHE_DISABLE_MASK);
+		info->protect[i] = (flashtest & 0x0001);
+	}
+#endif
+
+	return flash_info[0].size
+#if CFG_MAX_FLASH_BANKS == 2
+		+ flash_info[1].size
+#endif
+		;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_DEV_U7_2MB) {
+		printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n");
+	} else if (info->flash_id == FLASH_DEV_U9_512KB) {
+		printf ("AMD Am29LV040B	 (512KB) 8x64KB\n");
+	} else {
+		printf ("Unknown flash_id ...\n");
+		return;
+	}
+
+	printf ("  Size: %ld KB in %d Sectors\n",
+		info->size >> 10, info->sector_count);
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 4) == 0)
+			printf ("\n   ");
+		printf (" S%02d @ 0x%08lX%s", i,
+			info->start[i], info->protect[i] ? " !" : "  ");
+	}
+	printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	u16 i, error = 0;
+
+	printf ("\n");
+
+	/* check flash protection bits */
+	if (_flash_check_protection (info, s_first, s_last)) {
+		printf ("  Flash erase aborted due to protected sectors\n");
+		return ERR_PROTECTED;
+	}
+
+	if ((s_first < info->sector_count) && (s_first <= s_last)) {
+		for (i = s_first; i <= s_last && !error; i++) {
+			printf ("  Erasing Sector %d @ 0x%08lx ... ", i,
+				info->start[i]);
+			/* bypass the cache to access the flash memory */
+			FLASH_CMD_ERASE_SEC (info->flash_id,
+					     (info->
+					      start[0] | CACHE_DISABLE_MASK),
+					     (info->
+					      start[i] | CACHE_DISABLE_MASK));
+			/* look for sector to become 0xFF after erase */
+			error = _flash_poll (info->flash_id,
+					     info->
+					     start[i] | CACHE_DISABLE_MASK,
+					     0xFF, CFG_FLASH_ERASE_TOUT);
+			FLASH_CMD_RESET (info->flash_id,
+					 (info->
+					  start[0] | CACHE_DISABLE_MASK));
+			printf ("done\n");
+			if (error) {
+				break;
+			}
+		}
+	} else
+		error = ERR_INVAL;
+
+	return error;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	u16 error = 0, i;
+	u32 n;
+	u8 *bp, *bps;
+
+	/*  Write Setup */
+	/* bypass the cache to access the flash memory */
+	FLASH_CMD_UNLOCK_BYPASS (info->flash_id,
+				 (info->start[0] | CACHE_DISABLE_MASK));
+
+	/*  Write the Data to Flash */
+
+	bp = (u8 *) (addr | CACHE_DISABLE_MASK);
+	bps = (u8 *) src;
+
+	for (n = 0; n < cnt && !error; n++, bp++, bps++) {
+
+		if (!(n % (cnt / 15))) {
+			printf (".");
+		}
+
+		/*  write the flash command for flash memory */
+		*bp = 0xA0;
+
+		/*  Write the data */
+		*bp = *bps;
+
+		/*  Check if the write is done */
+		for (i = 0; i < 0xff; i++);
+		error = _flash_poll (info->flash_id, (u32) bp, *bps,
+				     CFG_FLASH_WRITE_TOUT);
+		if (error) {
+			return error;
+		}
+	}
+
+	/*  Reset the Flash Mode to read */
+	FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]);
+
+	printf (" ");
+
+	return error;
+}
--- a/board/evb4510/memsetup.S
+++ b/board/evb4510/memsetup.S
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM.  After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000.	After memsetup completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ *     to	8MB SRAM (U5) -- 8MB Map
+ * 0x00800000
+ *
+ * 0x01000000
+ *     to	2MB Flash @ 0x00000000 (U7) -- 2MB Map
+ * 0x01200000
+ *
+ * 0x02000000
+ *     to	512KB Flash @ 0x02000000 (U9) -- 2MB Map
+ * 0x02080000
+ *
+ * Load all 12 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written.	The
+ * last register written re-enables memory access.  For more info see
+ * the user's manual for the S3C4510B, available from Samsung's web
+ * site.  Search for part number "S3C4510B".
+ *
+ ***********************************************************************/
+
+.globl memsetup
+memsetup:
+
+	/* preserve the temp register (r12 AKA ip) and remap it. */
+	ldr r1, =SRAM_BASE+0xC
+	add r0, r12, #0x01000000
+	str r0, [r1]
+
+	/* remap the link register for when we return */
+	add lr, lr, #0x01000000
+
+	/* store a short program in the on chip SRAM, which is
+	 * unaffected when remapping memory.  Note the cache must be
+	 * disabled for the on chip SRAM to be available.
+	 */
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe8801ffe  /* stmia r0, {r1-r12} */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe59fc000  /* ldr r12, [pc, #0]  */
+	str r0, [r1]
+	add r1, r1, #4
+	ldr r0, =0xe1a0f00e  /* mov pc, lr	   */
+	str r0, [r1]
+
+	adr   r0, memory_map_data
+	ldmia r0, {r1-r12}
+	ldr   r0, =REG_EXTDBWTH
+
+	ldr pc, =SRAM_BASE
+
+.globl reset_cpu
+reset_cpu:
+	/*
+	 * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
+	 * address 0x0.	 We accomplish this by storing a few
+	 * instructions into the on chip SRAM (8KB) and run from
+	 * there.  Note the cache must be disabled for the on chip
+	 * SRAM to be available.
+	 *
+	 * load r2 with REG_ROMCON0
+	 * load r3 with 0x12040060	   configure FLASH bank 0 @ 0x00000000
+	 * load r4 with REG_DRAMCON0
+	 * load r5 with 0x08000380	   configure   RAM bank 0 @ 0x01000000
+	 * load r6 with REG_REFEXTCON
+	 * load r7 with 0x9c218360
+	 * load r8 with 0x0
+	 * store str r3,[r2] @ SRAM_BASE
+	 * store str r5,[r4] @ SRAM_BASE + 0x4
+	 * store str r7,[r6] @ SRAM_BASE + 0x8
+	 * store mov pc,r8   @ SRAM_BASE + 0xC
+	 * mov pc, SRAM_BASE
+	 *
+	 */
+
+	/* disable cache */
+	ldr r0, =REG_SYSCFG
+	ldr r1, =0x83ffffa0	/* cache-disabled  */
+	str r1, [r0]
+
+	ldr r2, =REG_ROMCON0
+	ldr r3, =0x02000060	/* Bank0 2MB FLASH   @ 0x00000000 */
+	ldr r4, =REG_DRAMCON0
+	ldr r5, =0x18040380	/* DRAM0 8MB SRAM    @ 0x01000000 */
+	ldr r6, =REG_REFEXTCON
+	ldr r7, =0xce278360
+	ldr r8, =0x00000000
+	ldr r1, =SRAM_BASE
+	ldr r0, =0xe5823000	/* str	r3, [r2] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+4
+	ldr r0, =0xe5845000	/* str	r5, [r4] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+8
+	ldr r0, =0xe5867000	/* str	r7, [r6] */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE+0xC
+	ldr r0, =0xe1a0f008	/* mov	pc, r8	 */
+	str r0, [r1]
+	ldr r1, =SRAM_BASE
+	mov pc, r1
+
+	/* never return */
+
+/************************************************************************
+ * Below are twelve 32-bit values for the twelve memory registers of
+ * the system manager, starting with register REG_EXTDBWTH.
+ ***********************************************************************/
+memory_map_data:
+	.long 0x00f03005     /* memory widths */
+	.long 0x12040060     /* Bank0 2MB FLASH	  @ 0x01000000 */
+	.long 0x22080060     /* Bank1 512KB FLASH @ 0x02000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x08000380     /* DRAM0 8MB SRAM	  @ 0x00000000 */
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x00000000
+	.long 0x9c218360     /* enable memory */
--- a/board/evb4510/u-boot.lds
+++ b/board/evb4510/u-boot.lds
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text	   :
+	{
+	  cpu/arm720t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+				  /* Stabs debugging sections.	  */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
--- a/board/fads/config.mk
+++ b/board/fads/config.mk
@@ -24,8 +24,8 @@
 #

 #
-# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and DUET
-# (MPC87x/88x) ADS boards
+# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
+# MPC885ADS boards
 #

 TEXT_BASE = 0xFE000000
--- a/board/fads/fads.c
+++ b/board/fads/fads.c
@@ -26,12 +26,13 @@
 #include <config.h>
 #include <common.h>
 #include <mpc8xx.h>
+#include <pcmcia.h>

 #define	_NOT_USED_	0xFFFFFFFF

 /* ========================================================================= */

-#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */

 #if defined(CONFIG_DRAM_50MHZ)
 /* 50MHz tables */
@@ -290,7 +291,7 @@ static void _dramdisable(void)

 	/* maybe we should turn off upma here or something */
 }
-#endif /* !CONFIG_DUET_ADS */
+#endif /* !CONFIG_MPC885ADS */

 /* ========================================================================= */

@@ -604,7 +605,7 @@ long int initdram (int board_type)
 	uint sdramsz = 0;	/* size of sdram in Mbytes */
 	uint base = 0;		/* base of dram in bytes */
 	uint m = 0;		/* size of dram in Mbytes */
-#ifndef CONFIG_DUET_ADS
+#ifndef CONFIG_MPC885ADS
 	uint k, s;
 #endif

@@ -614,7 +615,7 @@ long int initdram (int board_type)
 		printf ("(%u MB SDRAM) ", sdramsz);
 	}
 #endif
-#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */
+#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
 	k = (*((uint *) BCSR2) >> 23) & 0x0f;

 	switch (k & 0x3) {
@@ -665,7 +666,7 @@ long int initdram (int board_type)
 		_dramdisable ();
 		m = 0;
 	}
-#endif /* !CONFIG_DUET_ADS */
+#endif /* !CONFIG_MPC885ADS */
 	m += sdramsz;				/* add sdram size to total */

 	return (m << 20);
@@ -734,8 +735,8 @@ int checkboard (void)

 #if defined(CONFIG_MPC86xADS)
 	puts ("MPC86xADS");
-#elif defined(CONFIG_DUET_ADS)
-	puts ("DUET ADS");
+#elif defined(CONFIG_MPC885ADS)
+	puts ("MPC885ADS");
 	r = 0; /* I've got NR (No Revision) board */
 #elif defined(CONFIG_FADS)
 	puts ("FADS");
@@ -759,7 +760,7 @@ int checkboard (void)
 	case 0x03:
 		puts ("B \n");
 		break;
-#elif defined(CONFIG_DUET_ADS)
+#elif defined(CONFIG_MPC885ADS)
 	case 0x00:
 		puts ("NR\n");
 		break;
@@ -790,7 +791,7 @@ volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
 int pcmcia_init(void)
 {
 	volatile pcmconf8xx_t	*pcmp;
-	uint v, slota, slotb;
+	uint v, slota = 0, slotb = 0;

 	/*
 	** Enable the PCMCIA for a Flash card.
@@ -805,10 +806,10 @@ int pcmcia_init(void)
 	/* Set all slots to zero by default. */
 	pcmp->pcmc_pgcra = 0;
 	pcmp->pcmc_pgcrb = 0;
-#ifdef PCMCIA_SLOT_A
+#ifdef CONFIG_PCMCIA_SLOT_A
 	pcmp->pcmc_pgcra = 0x40;
 #endif
-#ifdef PCMCIA_SLOT_B
+#ifdef CONFIG_PCMCIA_SLOT_B
 	pcmp->pcmc_pgcrb = 0x40;
 #endif

@@ -817,17 +818,17 @@ int pcmcia_init(void)

 	/* Check if any PCMCIA card is plugged in. */

+#ifdef CONFIG_PCMCIA_SLOT_A
 	slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
 	slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
+#endif

 	if (!(slota || slotb)) {
 		printf("No card present\n");
-#ifdef PCMCIA_SLOT_A
 		pcmp->pcmc_pgcra = 0;
-#endif
-#ifdef PCMCIA_SLOT_B
 		pcmp->pcmc_pgcrb = 0;
-#endif
 		return -1;
 	}
 	else
@@ -908,9 +909,10 @@ int pcmcia_init(void)

 	udelay(20);

-#ifdef PCMCIA_SLOT_A
+#ifdef CONFIG_PCMCIA_SLOT_A
 	pcmp->pcmc_pgcra = 0;
-#elif PCMCIA_SLOT_B
+#endif
+#ifdef CONFIG_PCMCIA_SLOT_B
 	pcmp->pcmc_pgcrb = 0;
 #endif

--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -48,9 +48,6 @@
 * | ...                   |                                 v
 *
 *****************************************************************************/
-/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
-/* in general, we always know this for FADS+new ADS anyway */
-#define CONFIG_8xx_GCLK_FREQ     ((CFG_8XX_XIN) * (CFG_8XX_FACT))

 #if 0
 #define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
@@ -66,6 +63,7 @@
    "bootm"

 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */

 /*
 * New MPC86xADS and Duet provide two Ethernet connectivity options:
@@ -90,11 +88,13 @@
 #endif

 #ifndef CONFIG_COMMANDS
-#define CONFIG_COMMANDS	(CONFIG_CMD_DFL  \
-			 | CFG_CMD_DHCP  \
-			 | CFG_CMD_IMMAP \
-			 | CFG_CMD_MII   \
-			 | CFG_CMD_PING  \
+#define CONFIG_COMMANDS	(CONFIG_CMD_DFL   \
+			 | CFG_CMD_DHCP   \
+			 | CFG_CMD_IMMAP  \
+			 | CFG_CMD_JFFS2  \
+			 | CFG_CMD_MII    \
+			 | CFG_CMD_PCMCIA \
+			 | CFG_CMD_PING   \
 			)
 #endif /* !CONFIG_COMMANDS */

@@ -146,7 +146,7 @@
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
 #define	CFG_SDRAM_BASE		0x00000000
-#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */
+#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
 #define	CFG_SDRAM_SIZE		0x00800000      	/* 8 Mbyte */
 #elif defined(CONFIG_FADS)				/* Old/new FADS */
 #define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
@@ -167,14 +167,24 @@
 * the maximum mapped by the Linux kernel during initialization.
 */
 #define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
 /*-----------------------------------------------------------------------
 * Flash organization
 */
-#define CFG_FLASH_BASE		TEXT_BASE
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+#define CFG_FLASH_BASE		CFG_MONITOR_BASE
+#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/

-#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	16      /* max number of sectors on one chip	*/
+#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
@@ -184,9 +194,14 @@
 #define CFG_ENV_OFFSET		CFG_ENV_SECT_SIZE
 #define	CFG_ENV_SIZE		0x4000	/* Total Size of Environment		*/

-#define CFG_MONITOR_BASE	CFG_FLASH_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#define	CFG_DIRECT_FLASH_TFTP
+
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS2_FIRST_BANK	0
+#define CFG_JFFS2_NUM_BANKS	CFG_MAX_FLASH_BANKS
+#define CFG_JFFS2_FIRST_SECTOR  4
+#define CFG_JFFS2_SORT_FRAGMENTS
+#endif /* CFG_CMD_JFFS2 */

 /*-----------------------------------------------------------------------
 * Cache Configuration
@@ -248,7 +263,16 @@
 #define SCCR_MASK	SCCR_EBDF11
 #define CFG_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)

- /*-----------------------------------------------------------------------
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		14-22
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control
+ */
+#ifndef CFG_PLPRCR
+#define CFG_PLPRCR	PLPRCR_TEXPS
+#endif
+
+/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
@@ -339,6 +363,7 @@
 #define BCSR1_PCCVCCON		 BCSR1_PCCVCC0

 #define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
+#define BCSR2_FLASH_PD_SHIFT     28
 #define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
 #define BCSR2_DRAM_PD_SHIFT      23
 #define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
@@ -407,6 +432,20 @@
 #define BCSR4_DATA_VOICE         ((uint)0x00080000)
 #endif /* CONFIG_MPC850 */

+/* BSCR5 exists on MPC86xADS and Duet ADS only */
+
+#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+
+#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)
+
+#define BCSR5_MII2_EN		0x40
+#define BCSR5_MII2_RST		0x20
+#define BCSR5_T1_RST		0x10
+#define BCSR5_ATM155_RST	0x08
+#define BCSR5_ATM25_RST		0x04
+#define BCSR5_MII1_EN		0x02
+#define BCSR5_MII1_RST		0x01
+
 /* We don't use the 8259.
 */
 #define NR_8259_INTS	0
@@ -419,10 +458,6 @@
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 */
-#if !defined(CONFIG_MPC823) && !defined(CONFIG_MPC850)
-#define PCMCIA_SLOT_A 1
-#endif
-
 #define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
 #define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
 #define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
--- a/board/fads/flash.c
+++ b/board/fads/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>

-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */

 #if defined(CFG_ENV_IS_IN_FLASH)
 # ifndef  CFG_ENV_ADDR
@@ -38,124 +38,103 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 # endif
 #endif

+#define QUAD_ID(id)	((((ulong)(id) & 0xFF) << 24) | \
+			 (((ulong)(id) & 0xFF) << 16) | \
+			 (((ulong)(id) & 0xFF) << 8)  | \
+			 (((ulong)(id) & 0xFF) << 0)    \
+			)
+
 /*-----------------------------------------------------------------------
 * Functions
 */
 static ulong flash_get_size (vu_long * addr, flash_info_t * info);
 static int write_word (flash_info_t * info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t * info);

 /*-----------------------------------------------------------------------
 */
-
 unsigned long flash_init (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
-	unsigned long total_size;
-	unsigned long size_b0, size_b1;
+	vu_long *bcsr = (vu_long *)BCSR_ADDR;
+	unsigned long pd_size, total_size, bsize, or_am;
 	int i;

 	/* Init: no FLASHes known */
 	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].size = 0;
+		flash_info[i].sector_count = 0;
+		flash_info[i].start[0] = 0xFFFFFFFF; /* For TFTP */
+	}
+
+	switch ((bcsr[2] & BCSR2_FLASH_PD_MASK) >> BCSR2_FLASH_PD_SHIFT) {
+	case 2:
+	case 4:
+	case 6:
+		pd_size = 0x800000;
+		or_am = 0xFF800000;
+		break;
+
+	case 5:
+	case 7:
+		pd_size = 0x400000;
+		or_am = 0xFFC00000;
+		break;
+
+	case 8:
+		pd_size = 0x200000;
+		or_am = 0xFFE00000;
+		break;
+
+	default:
+		pd_size = 0;
+		or_am = 0xFFE00000;
+		printf("## Unsupported flash detected by BCSR: 0x%08X\n", bcsr[2]);
 	}

 	total_size = 0;
-	size_b0 = 0xffffffff;
-
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
-		size_b1 =
-			flash_get_size ((vu_long *) (CFG_FLASH_BASE +
-						     total_size),
-					&flash_info[i]);
+	for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
+		bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size),
+				       &flash_info[i]);

 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", i, size_b1, size_b1 >> 20);
+			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+				i, bsize, bsize >> 20);
 		}

-		/* Is this really needed ? - LP */
-		if (size_b1 > size_b0) {
-			printf ("## ERROR: Bank %d (0x%08lx = %ld MB) > Bank %d (0x%08lx = %ld MB)\n", i, size_b1, size_b1 >> 20, i - 1, size_b0, size_b0 >> 20);
-			goto out_error;
-		}
-		size_b0 = size_b1;
-		total_size += size_b1;
+		total_size += bsize;
 	}

-	/* Compute the Address Mask */
-	for (i = 0; (total_size >> i) != 0; ++i) {
-	}
-	i--;
-
-	if (total_size != (1 << i)) {
-		printf ("## WARNING: Total FLASH size (0x%08lx = %ld MB) is not a power of 2\n", total_size, total_size >> 20);
+	if (total_size != pd_size) {
+		printf("## Detected flash size %lu conflicts with PD data %lu\n",
+		       total_size, pd_size);
 	}

 	/* Remap FLASH according to real size */
-	memctl->memc_or0 =
-		((((unsigned long) ~1) << i) & OR_AM_MSK) |
-		CFG_OR_TIMING_FLASH;
-	memctl->memc_br0 = CFG_BR0_PRELIM;
-
-	total_size = 0;
+	memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH;

 	for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
-		/* Re-do sizing to get full correct info */
-		/* Why ? - LP */
-		size_b1 =
-			flash_get_size ((vu_long *) (CFG_FLASH_BASE +
-						     total_size),
-					&flash_info[i]);
-
-		/* This is done by flash_get_size - LP */
-		/* flash_get_offsets (CFG_FLASH_BASE + total_size, &flash_info[i]); */
-
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 		/* monitor protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[i]);
+		if (CFG_MONITOR_BASE >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_MONITOR_BASE,
+				       CFG_MONITOR_BASE + monitor_flash_len - 1,
+				       &flash_info[i]);
 #endif

 #ifdef	CFG_ENV_IS_IN_FLASH
 		/* ENV protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-			       CFG_ENV_ADDR,
-			       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
-			       &flash_info[i]);
+		if (CFG_ENV_ADDR >= flash_info[i].start[0])
+			flash_protect (FLAG_PROTECT_SET,
+				       CFG_ENV_ADDR,
+				       CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+				       &flash_info[i]);
 #endif
-
-		total_size += size_b1;
 	}

-	return (total_size);
-
-      out_error:
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-		flash_info[i].sector_count = -1;
-		flash_info[i].size = 0;
-	}
-
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	/* set up sector start address table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040
-	    || (info->flash_id & FLASH_TYPEMASK) == FLASH_AM080) {
-		/* set sector offsets for uniform sector type   */
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00040000);
-		}
-	}
+	return total_size;
 }

 /*-----------------------------------------------------------------------
@@ -235,48 +214,26 @@ void flash_print_info (flash_info_t * info)
 	}

 	printf ("\n");
-	return;
 }

 /*-----------------------------------------------------------------------
+ * The following code can not run from flash!
 */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
 static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 {
 	short i;

-#if 0
-	ulong base = (ulong) addr;
-#endif
-	uchar value;
-
 	/* Write auto select command: read Manufacturer ID */
-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00900090;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0x90909090;
-#endif

-	value = addr[0];
-
-	switch (value + (value << 16)) {
-	case AMD_MANUFACT:
+	switch (addr[0]) {
+	case QUAD_ID(AMD_MANUFACT):
 		info->flash_id = FLASH_MAN_AMD;
 		break;

-	case FUJ_MANUFACT:
+	case QUAD_ID(FUJ_MANUFACT):
 		info->flash_id = FLASH_MAN_FUJ;
 		break;

@@ -287,21 +244,20 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		break;
 	}

-	value = addr[1];	/* device ID            */
-
-	switch (value) {
-	case AMD_ID_F040B:
+	switch (addr[1]) {	/* device ID            */
+	case QUAD_ID(AMD_ID_F040B):
+	case QUAD_ID(AMD_ID_LV040B):
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x00200000;
 		break;		/* => 2 MB              */

-	case AMD_ID_F080B:
+	case QUAD_ID(AMD_ID_F080B):
 		info->flash_id += FLASH_AM080;
 		info->sector_count = 16;
 		info->size = 0x00400000;
 		break;		/* => 4 MB              */
-
+#if 0
 	case AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
@@ -337,7 +293,7 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->sector_count = 35;
 		info->size = 0x00400000;
 		break;		/* => 4 MB              */
-#if 0				/* enable when device IDs are available */
+
 	case AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 67;
@@ -349,11 +305,10 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->sector_count = 67;
 		info->size = 0x00800000;
 		break;		/* => 8 MB              */
-#endif
+#endif /* 0 */
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);	/* => no or unknown flash */
-
 	}

 #if 0
@@ -378,7 +333,9 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		}
 	}
 #else
-	flash_get_offsets ((ulong) addr, info);
+	/* set sector offsets for uniform sector type */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = (ulong)addr + (i * 0x00040000);
 #endif

 	/* check for protected sectors */
@@ -389,25 +346,16 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->protect[i] = addr[2] & 1;
 	}

-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
 		addr = (volatile unsigned long *) info->start[0];
-#if 0
-		*addr = 0x00F000F0;	/* reset bank */
-#else
 		*addr = 0xF0F0F0F0;	/* reset bank */
-#endif
 	}

 	return (info->size);
 }

-
 /*-----------------------------------------------------------------------
 */
-
 int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
 	vu_long *addr = (vu_long *) (info->start[0]);
@@ -420,13 +368,13 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		} else {
 			printf ("- no sectors to erase\n");
 		}
-		return 1;
+		return ERR_INVAL;
 	}

 	if ((info->flash_id == FLASH_UNKNOWN) ||
 	    (info->flash_id > FLASH_AMD_COMP)) {
 		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
+		return ERR_UNKNOWN_FLASH_TYPE;
 	}

 	prot = 0;
@@ -447,29 +395,17 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();

-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0x80808080;
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
-#endif

 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			addr = (vu_long *) (info->start[sect]);
-#if 0
-			addr[0] = 0x00300030;
-#else
 			addr[0] = 0x30303030;
-#endif
 			l_sect = sect;
 		}
 	}
@@ -490,15 +426,11 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 	start = get_timer (0);
 	last = start;
 	addr = (vu_long *) (info->start[l_sect]);
-#if 0
-	while ((addr[0] & 0x00800080) != 0x00800080)
-#else
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
-#endif
 	{
 		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
-			return 1;
+			return ERR_TIMOUT;
 		}
 		/* show that we're waiting */
 		if ((now - last) > 1000) {	/* every second */
@@ -510,13 +442,10 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
      DONE:
 	/* reset to read mode */
 	addr = (volatile unsigned long *) info->start[0];
-#if 0
-	addr[0] = 0x00F000F0;	/* reset bank */
-#else
 	addr[0] = 0xF0F0F0F0;	/* reset bank */
-#endif

 	printf (" done\n");
+
 	return 0;
 }

@@ -526,7 +455,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 * 1 - write timeout
 * 2 - Flash not erased
 */
-
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong cp, wp, data;
@@ -605,20 +533,14 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)

 	/* Check if Flash is (sufficiently) erased */
 	if ((*((vu_long *) dest) & data) != data) {
-		return (2);
+		return ERR_NOT_ERASED;
 	}
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();

-#if 0
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00A000A0;
-#else
 	addr[0x0555] = 0xAAAAAAAA;
 	addr[0x02AA] = 0x55555555;
 	addr[0x0555] = 0xA0A0A0A0;
-#endif

 	*((vu_long *) dest) = data;

@@ -628,18 +550,11 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)

 	/* data polling for D7 */
 	start = get_timer (0);
-#if 0
-	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080))
-#else
 	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
-#endif
 	{
 		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
-			return (1);
+			return ERR_TIMOUT;
 		}
 	}
 	return (0);
 }
-
-/*-----------------------------------------------------------------------
- */
--- a/board/fads/u-boot.lds
+++ b/board/fads/u-boot.lds
@@ -52,7 +52,7 @@ SECTIONS
  {
    cpu/mpc8xx/start.o		(.text)

-    . = DEFINED(env_offset) ? env_offset : .;
+    /*. = DEFINED(env_offset) ? env_offset : .;*/
    common/environment.o	(.ppcenv)

    *(.text)
--- a/board/integratorap/integratorap.c
+++ b/board/integratorap/integratorap.c
@@ -73,6 +73,8 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;

+	gd->flags = 0;
+
 	icache_enable ();

 	flash__init ();
--- a/board/integratorcp/integratorcp.c
+++ b/board/integratorcp/integratorcp.c
@@ -69,6 +69,8 @@ int board_init (void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;

+	gd->flags = 0;
+
 	icache_enable ();

 	flash__init ();
--- a/board/ispan/Makefile
+++ b/board/ispan/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/ispan/config.mk
+++ b/board/ispan/config.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2004 Arabella Software Ltd.
+# Yuli Barcohen <yuli@arabellasw.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Interphase iSPAN Communications Controllers
+#
+#TEXT_BASE = 0xFF800000
+#TEXT_BASE = 0xFFBA0000
+TEXT_BASE = 0xFE7A0000
--- a/board/ispan/ispan.c
+++ b/board/ispan/ispan.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Interphase iSPAN Communications Controllers
+ * (453x and others). Tested on 4532.
+ *
+ * Derived from iSPAN 4539 port (iphase4539) by
+ * Wolfgang Grandegger <wg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/io.h>
+
+/*
+ * I/O Ports configuration table
+ *
+ * If conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A */
+    {	/*	      conf      ppar psor pdir podr pdat */
+	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
+	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
+	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
+	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
+	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
+	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
+	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
+	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
+	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 SMTXD */
+	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 SMRXD */
+	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7 */
+	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
+	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5 */
+	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4 */
+	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3 */
+	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2 */
+	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
+	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0 */
+    },
+
+    /* Port B */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
+	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
+	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
+	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
+	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
+	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
+	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
+	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
+	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
+	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
+	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
+	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
+	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
+	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
+	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
+	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
+	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
+	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
+	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
+	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
+	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
+	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
+	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
+	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22 */
+	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21 */
+	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
+	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19 */
+	/* PC18 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
+	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
+	/* PC16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
+	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
+	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
+	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
+	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
+	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
+	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
+	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
+	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8  */
+	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7  */
+	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6  */
+	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5  */
+	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4  */
+	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3  */
+	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2  */
+	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1  */
+	/* PC0  */ { 0,          0,   0,   0,   0,   0 }  /* PC0  */
+    },
+
+    /* Port D */
+    {   /*	      conf      ppar psor pdir podr pdat */
+	/* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31 */
+	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30 */
+	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29 */
+	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28 */
+	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27 */
+	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26 */
+	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25 */
+	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24 */
+	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23 */
+	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22 */
+	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21 */
+	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20 */
+	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19 */
+	/* PD18 */ { 0,          1,   1,   0,   0,   0 }, /* SPICLK  */
+	/* PD17 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMOSI */
+	/* PD16 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMISO */
+	/* PD15 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SDA */
+	/* PD14 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SCL */
+	/* PD13 */ { 1,          0,   0,   0,   0,   0 }, /* MII MDIO */
+	/* PD12 */ { 1,          0,   0,   1,   0,   0 }, /* MII MDC  */
+	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11 */
+	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10 */
+	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 SMTXD */
+	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 SMRXD */
+	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7 */
+	/* PD6  */ { CFG_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
+	/* PD5  */ { CFG_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
+	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4 */
+	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
+	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
+    }
+};
+
+#define PSPAN_ADDR      0xF0020000
+#define EEPROM_REG      0x408
+#define EEPROM_READ_CMD 0xA000
+#define PSPAN_WRITE(a,v) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
+#define PSPAN_READ(a) \
+    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
+
+static int seeprom_read (int addr, uchar * data, int size)
+{
+	ulong val, cmd;
+	int i;
+
+	for (i = 0; i < size; i++) {
+
+		cmd = EEPROM_READ_CMD;
+		cmd |= ((addr + i) << 24) & 0xff000000;
+
+		/* Wait for ACT to authorize write */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Write command */
+		PSPAN_WRITE (EEPROM_REG, cmd);
+
+		/* Wait for data to be valid */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+		/* Do it twice, first read might be erratic */
+		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
+			eieio ();
+
+		/* Read error */
+		if (val & 0x00000040) {
+			return -1;
+		} else {
+			data[i] = (val >> 16) & 0xff;
+		}
+	}
+	return 0;
+}
+
+/***************************************************************
+ * We take some basic Hardware Configuration Parameter from the
+ * Serial EEPROM conected to the PSpan bridge. We keep it as
+ * simple as possible.
+ */
+#ifdef DEBUG
+static int hwc_flash_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte >> 2) & 0x3) {
+		case 0x1:
+			return 0x0400000;
+			break;
+		case 0x2:
+			return 0x0800000;
+			break;
+		case 0x3:
+			return 0x1000000;
+		default:
+			return 0x0100000;
+		}
+	}
+	return -1;
+}
+
+static int hwc_local_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
+		switch ((byte & 0x03)) {
+		case 0x1:
+			return 0x0800000;
+		case 0x2:
+			return 0x1000000;
+		default:
+			return 0;			/* not present */
+		}
+	}
+	return -1;
+}
+#endif	/* DEBUG */
+
+static int hwc_main_sdram_size (void)
+{
+	uchar byte;
+
+	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
+		return 0x1000000 << ((byte >> 5) & 0x7);
+	}
+	return -1;
+}
+
+static int hwc_serial_number (void)
+{
+	int sn = -1;
+
+	if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
+		sn = cpu_to_le32 (sn);
+	}
+	return sn;
+}
+
+static int hwc_mac_address (char *str)
+{
+	char mac[6];
+
+	if (!seeprom_read (0xb0, mac, sizeof (mac))) {
+		sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
+				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	} else {
+		strcpy (str, "ERROR");
+		return -1;
+	}
+	return 0;
+}
+
+static int hwc_manufact_date (char *str)
+{
+	uchar byte;
+	int value;
+
+	if (seeprom_read (0x92, &byte, sizeof (byte)))
+		goto out;
+	value = byte;
+	if (seeprom_read (0x93, &byte, sizeof (byte)))
+		goto out;
+	value += byte << 8;
+	sprintf (str, "%02d/%02d/%04d",
+			 value & 0x1F, (value >> 5) & 0xF,
+			 1980 + ((value >> 9) & 0x1FF));
+	return 0;
+
+out:
+	strcpy (str, "ERROR");
+	return -1;
+}
+
+static int hwc_board_type (char **str)
+{
+	ushort id = 0;
+
+	if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
+		switch (id) {
+		case 0x9080:
+			*str = "4532-002";
+			break;
+		case 0x9081:
+			*str = "4532-001";
+			break;
+		case 0x9082:
+			*str = "4532-000";
+			break;
+		default:
+			*str = "Unknown";
+		}
+	} else {
+		*str = "Unknown";
+	}
+
+	return id;
+}
+
+long int initdram (int board_type)
+{
+	long maxsize = hwc_main_sdram_size();
+
+#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *base;
+	int i;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x00000026;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_lcl_acr  = 0x00000000;
+	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
+	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
+	immap->im_siu_conf.sc_tescr1   = 0x00004000;
+	immap->im_siu_conf.sc_ltescr1  = 0x00004000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+
+	/* Initialise 60x bus SDRAM */
+	base = (uchar *)(CFG_SDRAM_BASE | 0x110);
+	memctl->memc_psrt  = CFG_PSRT;
+	memctl->memc_or1   = CFG_60x_OR;
+	memctl->memc_br1   = CFG_SDRAM_BASE | CFG_60x_BR;
+
+	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	*base = 0xFF;
+	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	*base = 0xFF;
+	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+
+	/* Initialise local bus SDRAM */
+	base = (uchar *)CFG_LSDRAM_BASE;
+	memctl->memc_lsrt  = CFG_LSRT;
+	memctl->memc_or2   = CFG_LOC_OR;
+	memctl->memc_br2   = CFG_LSDRAM_BASE | CFG_LOC_BR;
+
+	memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
+	*base = 0xFF;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*base = 0xFF;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+	*base = 0xFF;
+	memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
+
+	maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
+
+	memctl->memc_or1 |= ~(maxsize - 1);
+
+	if (maxsize != hwc_main_sdram_size())
+		puts("Oops: memory test has not found all memory!\n");
+#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
+
+	/* Return total RAM size (size of 60x SDRAM) */
+	return maxsize;
+}
+
+int checkboard(void)
+{
+	char string[32], *id;
+
+	hwc_manufact_date(string);
+	hwc_board_type(&id);
+	printf("Board: Interphase iSPAN %s (#%d %s)\n",
+	       id, hwc_serial_number(), string);
+#ifdef DEBUG
+	printf("Manufacturing date: %s\n", string);
+	printf("Serial number     : %d\n", hwc_serial_number());
+	printf("FLASH size        : %d MB\n", hwc_flash_size() >> 20);
+	printf("Main SDRAM size   : %d MB\n", hwc_main_sdram_size() >> 20);
+	printf("Local SDRAM size  : %d MB\n", hwc_local_sdram_size() >> 20);
+	hwc_mac_address(string);
+	printf("MAC address       : %s\n", string);
+#endif
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	char *s, str[32];
+	int num;
+
+	if ((s = getenv("serial#")) == NULL &&
+	    (num = hwc_serial_number()) != -1) {
+		sprintf(str, "%06d", num);
+		setenv("serial#", str);
+	}
+	if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
+		setenv("ethaddr", str);
+	}
+
+	return 0;
+}
--- a/board/ispan/u-boot.lds
+++ b/board/ispan/u-boot.lds
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
--- a/board/jse/flash.c
+++ b/board/jse/flash.c
@@ -35,7 +35,7 @@
 #if CFG_MAX_FLASH_BANKS != 1
 #error "CFG_MAX_FLASH_BANKS must be 1"
 #endif
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	*/

 /*-----------------------------------------------------------------------
 * Functions
@@ -44,8 +44,8 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info);
 static int write_word (flash_info_t * info, ulong dest, ulong data);
 static void flash_get_offsets (ulong base, flash_info_t * info);

-#define ADDR0           0x5555
-#define ADDR1           0x2aaa
+#define ADDR0		0x5555
+#define ADDR1		0x2aaa
 #define FLASH_WORD_SIZE unsigned char

 /*-----------------------------------------------------------------------
@@ -84,36 +84,17 @@ unsigned long flash_init (void)

 /*-----------------------------------------------------------------------
 */
+/*
+ * This implementation assumes that the flash chips are uniform sector
+ * devices. This is true for all likely JSE devices.
+ */
 static void flash_get_offsets (ulong base, flash_info_t * info)
 {
-	int i;
+	unsigned idx;
+	unsigned long sector_size = info->size / info->sector_count;

-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-					base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
+	for (idx = 0; idx < info->sector_count; idx += 1) {
+		info->start[idx] = base + (idx * sector_size);
 	}
 }

@@ -142,44 +123,21 @@ void flash_print_info (flash_info_t * info)
 	case FLASH_MAN_SST:
 		printf ("SST ");
 		break;
+	case FLASH_MAN_STM:
+		printf ("ST Micro ");
+		break;
 	default:
 		printf ("Unknown Vendor ");
 		break;
 	}

-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM040:
+	  /* (Reduced table of only parts expected in JSE boards.) */
+	switch (info->flash_id) {
+	case FLASH_MAN_AMD | FLASH_AM040:
 		printf ("AM29F040 (512 Kbit, uniform sector size)\n");
 		break;
-	case FLASH_AM400B:
-		printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM400T:
-		printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM800B:
-		printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM800T:
-		printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM160B:
-		printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM160T:
-		printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-		break;
-	case FLASH_AM320B:
-		printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-		break;
-	case FLASH_AM320T:
-		printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-		break;
-	case FLASH_SST800A:
-		printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
-		break;
-	case FLASH_SST160A:
-		printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
+	case FLASH_MAN_STM | FLASH_AM040:
+		printf ("MM29W040W (512 Kbit, uniform sector size)\n");
 		break;
 	default:
 		printf ("Unknown Chip Type\n");
@@ -253,14 +211,18 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 	case (FLASH_WORD_SIZE) SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
+	case (FLASH_WORD_SIZE)STM_MANUFACT:
+		info->flash_id = FLASH_MAN_STM;
+		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
+		printf("Unknown flash manufacturer code: 0x%x\n", value);
 		return (0);	/* no or unknown flash  */
 	}

-	value = addr2[1];	/* device ID            */
+	value = addr2[1];	/* device ID		*/

 	switch (value) {
 	case (FLASH_WORD_SIZE) AMD_ID_F040B:
@@ -273,99 +235,19 @@ static ulong flash_get_size (vu_long * addr, flash_info_t * info)
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
-	case (FLASH_WORD_SIZE) AMD_ID_LV400T:
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB            */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV400B:
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;
-		break;		/* => 0.5 MB            */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV800T:
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;		/* => 1 MB              */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV800B:
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;
-		break;		/* => 1 MB              */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV160T:
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;		/* => 2 MB              */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV160B:
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;
-		break;		/* => 2 MB              */
-#if 0				/* enable when device IDs are available */
-	case (FLASH_WORD_SIZE) AMD_ID_LV320T:
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00400000;
-		break;		/* => 4 MB              */
-
-	case (FLASH_WORD_SIZE) AMD_ID_LV320B:
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00400000;
-		break;		/* => 4 MB              */
-#endif
-	case (FLASH_WORD_SIZE) SST_ID_xF800A:
-		info->flash_id += FLASH_SST800A;
-		info->sector_count = 16;
-		info->size = 0x00100000;
-		break;		/* => 1 MB              */
-
-	case (FLASH_WORD_SIZE) SST_ID_xF160A:
-		info->flash_id += FLASH_SST160A;
-		info->sector_count = 32;
-		info->size = 0x00200000;
-		break;		/* => 2 MB              */
-
+	case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele JSE chip */
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x0080000; /* => 512 ko */
+		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);	/* => no or unknown flash */

 	}

-	/* set up sector start address table */
-	if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
-	    (info->flash_id == FLASH_AM040)) {
-		for (i = 0; i < info->sector_count; i++)
-			info->start[i] = base + (i * 0x00010000);
-	} else {
-		if (info->flash_id & FLASH_BTYPE) {
-			/* set sector offsets for bottom boot block type        */
-			info->start[0] = base + 0x00000000;
-			info->start[1] = base + 0x00004000;
-			info->start[2] = base + 0x00006000;
-			info->start[3] = base + 0x00008000;
-			for (i = 4; i < info->sector_count; i++) {
-				info->start[i] =
-					base + (i * 0x00010000) - 0x00030000;
-			}
-		} else {
-			/* set sector offsets for top boot block type           */
-			i = info->sector_count - 1;
-			info->start[i--] = base + info->size - 0x00004000;
-			info->start[i--] = base + info->size - 0x00006000;
-			info->start[i--] = base + info->size - 0x00008000;
-			for (; i >= 0; i--) {
-				info->start[i] = base + i * 0x00010000;
-			}
-		}
-	}
+	  /* Calculate the sector offsets (Use JSE Optimized code). */
+	flash_get_offsets(base, info);

 	/* check for protected sectors */
 	for (i = 0; i < info->sector_count; i++) {
@@ -505,7 +387,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
 		goto DONE;
 	wait_for_DQ7 (info, l_sect);

-      DONE:
+DONE:
 #endif
 	/* reset to read mode */
 	addr = (FLASH_WORD_SIZE *) info->start[0];
@@ -603,7 +485,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data)

 	/* Check if Flash is (sufficiently) erased */
 	if ((*((volatile FLASH_WORD_SIZE *) dest) &
-	     (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
+	    (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
 		return (2);
 	}

--- a/board/lpd7a40x/Makefile
+++ b/board/lpd7a40x/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= lpd7a40x.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/lpd7a40x/config.mk
+++ b/board/lpd7a40x/config.mk
@@ -0,0 +1,38 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine
+# w/Sharp LH7A400 SoC (ARM920T) cpu
+#
+
+#
+# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000
+#
+# Linux-Kernel is @ 0xC0008000, entry 0xc0008000
+# params @ 0xc0000100
+# optionally with a ramdisk at 0xc0300000
+#
+# we load ourself to 0xc1fc0000 (32M - 256K)
+#
+# download area is 0xc0f00000
+#
+
+TEXT_BASE = 0xc1fc0000
+#TEXT_BASE = 0x00000000
--- a/board/lpd7a40x/flash.c
+++ b/board/lpd7a40x/flash.c
@@ -0,0 +1,489 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* #define DEBUG */
+
+#include <common.h>
+#include <environment.h>
+
+#define FLASH_BANK_SIZE 0x1000000	/* 16MB (2 x 8 MB) */
+#define MAIN_SECT_SIZE  0x40000		/* 256KB (2 x 128kB) */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+
+#define CMD_READ_ARRAY		0x00FF00FF
+#define CMD_IDENTIFY		0x00900090
+#define CMD_ERASE_SETUP		0x00200020
+#define CMD_ERASE_CONFIRM	0x00D000D0
+#define CMD_PROGRAM		0x00400040
+#define CMD_RESUME		0x00D000D0
+#define CMD_SUSPEND		0x00B000B0
+#define CMD_STATUS_READ		0x00700070
+#define CMD_STATUS_RESET	0x00500050
+
+#define BIT_BUSY		0x00800080
+#define BIT_ERASE_SUSPEND	0x00400040
+#define BIT_ERASE_ERROR		0x00200020
+#define BIT_PROGRAM_ERROR	0x00100010
+#define BIT_VPP_RANGE_ERROR	0x00080008
+#define BIT_PROGRAM_SUSPEND	0x00040004
+#define BIT_PROTECT_ERROR	0x00020002
+#define BIT_UNDEFINED		0x00010001
+
+#define BIT_SEQUENCE_ERROR	0x00300030
+#define BIT_TIMEOUT		0x80000000
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(INTEL_MANUFACT     & FLASH_VENDMASK) |
+			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = CFG_FLASH_BASE;
+		else
+			panic ("configured too many flash banks!\n");
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase;
+
+			/* uniform sector size */
+			flashbase += MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/*
+	 * Protect monitor and environment sectors
+	 */
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_FLASH_BASE,
+			CFG_FLASH_BASE + monitor_flash_len - 1,
+			&flash_info[0]);
+
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+#ifdef CFG_ENV_ADDR_REDUND
+	flash_protect ( FLAG_PROTECT_SET,
+			CFG_ENV_ADDR_REDUND,
+			CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+			&flash_info[0]);
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (INTEL_MANUFACT & FLASH_VENDMASK):
+		printf ("Intel: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (INTEL_ID_28F640J3A & FLASH_TYPEMASK):
+		printf ("2x 28F640J3A (64Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		return;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_error (ulong code)
+{
+	/* Check bit patterns */
+	/* SR.7=0 is busy, SR.7=1 is ready */
+	/* all other flags indicate error on 1 */
+	/* SR.0 is undefined */
+	/* Timeout is our faked flag */
+
+	/* sequence is described in Intel 290644-005 document */
+
+	/* check Timeout */
+	if (code & BIT_TIMEOUT) {
+		puts ("Timeout\n");
+		return ERR_TIMOUT;
+	}
+
+	/* check Busy, SR.7 */
+	if (~code & BIT_BUSY) {
+		puts ("Busy\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Vpp low, SR.3 */
+	if (code & BIT_VPP_RANGE_ERROR) {
+		puts ("Vpp range error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Device Protect Error, SR.1 */
+	if (code & BIT_PROTECT_ERROR) {
+		puts ("Device protect error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Command Seq Error, SR.4 & SR.5 */
+	if (code & BIT_SEQUENCE_ERROR) {
+		puts ("Command seqence error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Error, SR.5 */
+	if (code & BIT_ERASE_ERROR) {
+		puts ("Block erase error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Error, SR.4 */
+	if (code & BIT_PROGRAM_ERROR) {
+		puts ("Program error\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Block Erase Suspended, SR.6 */
+	if (code & BIT_ERASE_SUSPEND) {
+		puts ("Block erase suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* check Program Suspended, SR.2 */
+	if (code & BIT_PROGRAM_SUSPEND) {
+		puts ("Program suspended\n");
+		return ERR_PROG_ERROR;
+	}
+
+	/* OK, no error */
+	return ERR_OK;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result, result1;
+	int iflag, prot, sect;
+	int rc = ERR_OK;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	debug ("flash_erase: s_first %d  s_last %d\n", s_first, s_last);
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+		(INTEL_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+
+		debug ("Erasing sector %2d @ %08lX... ",
+			sect, info->start[sect]);
+
+		/* arm simple, non interrupt dependent timer */
+		reset_timer_masked();
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			vu_long *addr = (vu_long *) (info->start[sect]);
+			ulong bsR7, bsR7_2, bsR5, bsR5_2;
+
+			/* *addr = CMD_STATUS_RESET; */
+			*addr = CMD_ERASE_SETUP;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			do {
+				/* check timeout */
+				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+					*addr = CMD_STATUS_RESET;
+					result = BIT_TIMEOUT;
+					break;
+				}
+
+				*addr = CMD_STATUS_READ;
+				result = *addr;
+				bsR7 = result & (1 << 7);
+				bsR7_2 = result & (1 << 23);
+			} while (!bsR7 | !bsR7_2);
+
+			*addr = CMD_STATUS_READ;
+			result1 = *addr;
+			bsR5 = result1 & (1 << 5);
+			bsR5_2 = result1 & (1 << 21);
+#ifdef SAMSUNG_FLASH_DEBUG
+			printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+			if (bsR5 != 0 && bsR5_2 != 0)
+				printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2);
+#endif
+
+			*addr = CMD_READ_ARRAY;
+			*addr = CMD_RESUME;
+
+			if ((rc = flash_error (result)) != ERR_OK)
+				goto outahere;
+#if 0
+			printf ("ok.\n");
+		} else {		/* it was protected */
+
+			printf ("protected!\n");
+#endif
+		}
+	}
+
+outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay_masked (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash
+ */
+
+volatile static int write_word (flash_info_t * info, ulong dest,
+								ulong data)
+{
+	vu_long *addr = (vu_long *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int iflag;
+
+#ifdef USE_920T_MMU
+	int cflag;
+#endif
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+#ifdef USE_920T_MMU
+	cflag = dcache_status ();
+	dcache_disable ();
+#endif
+	iflag = disable_interrupts ();
+
+	/* *addr = CMD_STATUS_RESET; */
+	*addr = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait until flash is ready */
+	do {
+		/* check timeout */
+		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+			*addr = CMD_SUSPEND;
+			result = BIT_TIMEOUT;
+			break;
+		}
+
+		*addr = CMD_STATUS_READ;
+		result = *addr;
+	} while (~result & BIT_BUSY);
+
+	/* *addr = CMD_READ_ARRAY; */
+	*addr = CMD_STATUS_READ;
+	result = *addr;
+
+	rc = flash_error (result);
+
+	if (iflag)
+		enable_interrupts ();
+
+#ifdef USE_920T_MMU
+	if (cflag)
+		dcache_enable ();
+#endif
+	*addr = CMD_READ_ARRAY;
+	*addr = CMD_RESUME;
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~3);			/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 24);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 4; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 24);
+		}
+
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = *((vu_long *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 4;
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0) {
+		return ERR_OK;
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 24);
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 24);
+	}
+
+	return write_word (info, wp, data);
+}
--- a/board/lpd7a40x/lpd7a40x.c
+++ b/board/lpd7a40x/lpd7a40x.c
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_LH7A400)
+#include <lh7a400.h>
+#elif defined(CONFIG_LH7A404)
+#include <lh7a404.h>
+#else
+#error "No CPU defined!"
+#endif
+#include <asm/mach-types.h>
+
+#include <lpd7a400_cpld.h>
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* set up the I/O ports */
+
+	/* enable flash programming */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN;
+
+	/* Auto wakeup, LCD disable, WLAN enable */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &=
+		~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE);
+
+	/* Status LED 2 on (leds are active low) */
+	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) =
+		(EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2);
+
+#if defined(CONFIG_LH7A400)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A400;
+#elif defined(CONFIG_LH7A404)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A404;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xc0000100;
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
--- a/board/lpd7a40x/memsetup.S
+++ b/board/lpd7a40x/memsetup.S
@@ -0,0 +1,212 @@
+/*
+ * Memory Setup - initialize memory controller(s) for devices required
+ *                to boot and relocate
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/* memory controller */
+#define BCRX_DEFAULT	(0x0000fbe0)
+#define BCRX_MW_8	(0x00000000)
+#define BCRX_MW_16	(0x10000000)
+#define BCRX_MW_32	(0x20000000)
+#define BCRX_PME	(0x08000000)
+#define BCRX_WP		(0x04000000)
+#define BCRX_WST2_SHIFT	(11)
+#define BCRX_WST1_SHIFT	(5)
+#define BCRX_IDCY_SHIFT	(0)
+
+/* Bank0 Async Flash */
+#define BCR0	   	(0x80002000)
+#define BCR0_FLASH	(BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT))
+
+/* Bank1 Open */
+#define BCR1	(0x80002004)
+
+/* Bank2 Not used (EEPROM?) */
+#define BCR2	(0x80002008)
+
+/* Bank3 Not used */
+#define BCR3	(0x8000200C)
+
+/* Bank4 PC Card1 */
+
+/* Bank5 PC Card2 */
+
+/* Bank6 CPLD IO Controller Peripherals (slow) */
+#define BCR6	 	(0x80002018)
+#define BCR6_CPLD_SLOW	(BCRX_DEFAULT | BCRX_MW_16)
+
+/* Bank7 CPLD IO Controller Peripherals (fast) */
+#define BCR7		(0x8000201C)
+#define BCR7_CPLD_FAST	(BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT))
+
+/* SDRAM */
+#define GBLCNFG		(0x80002404)
+#define GC_CKE		(0x80000000)
+#define GC_CKSD		(0x40000000)
+#define GC_LCR		(0x00000040)
+#define GC_SMEMBURST	(0x00000020)
+#define GC_MRS		(0x00000002)
+#define GC_INIT		(0x00000001)
+
+#define GC_CMD_NORMAL		(GC_CKE)
+#define GC_CMD_MODE		(GC_CKE | GC_MRS)
+#define GC_CMD_SYNCFLASH_LOAD	(GC_CKE | GC_MRS | GC_LCR)
+#define GC_CMD_PRECHARGEALL	(GC_CKE | GC_INIT)
+#define GC_CMD_NOP		(GC_CKE | GC_INIT | GC_MRS)
+
+#define RFSHTMR		(0x80002408)
+#define RFSHTMR_INIT	(10)	/* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */
+#define RFSHTMR_NORMAL	(1500)	/* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */
+
+#define SDCSCX_BASE		(0x80002410)
+#define SDCSCX_DEFAULT		(0x01220008)
+#define SDCSCX_AUTOPC		(0x01000000)
+#define SDCSCX_RAS2CAS_2	(0x00200000)
+#define SDCSCX_RAS2CAS_3	(0x00300000)
+#define SDCSCX_WBL		(0x00080000)
+#define SDCSCX_CASLAT_8		(0x00070000)
+#define SDCSCX_CASLAT_7		(0x00060000)
+#define SDCSCX_CASLAT_6		(0x00050000)
+#define SDCSCX_CASLAT_5		(0x00040000)
+#define SDCSCX_CASLAT_4		(0x00030000)
+#define SDCSCX_CASLAT_3		(0x00020000)
+#define SDCSCX_CASLAT_2		(0x00010000)
+#define SDCSCX_2KPAGE		(0x00000040)
+#define SDCSCX_SROMLL		(0x00000020)
+#define SDCSCX_SROM512		(0x00000010)
+#define SDCSCX_4BNK		(0x00000008)
+#define SDCSCX_2BNK		(0x00000000)
+#define SDCSCX_EBW_16		(0x00000004)
+#define SDCSCX_EBW_32		(0x00000000)
+
+#define SDRAM_BASE		(0xC0000000)
+#define SDCSC_BANK_OFFSET	(0x10000000)
+
+/*
+ * The SDRAM DEVICE MODE PROGRAMMING VALUE
+ */
+#define BURST_LENGTH_4		(2 << 10)
+#define BURST_LENGTH_8		(3 << 10)
+#define WBURST_LENGTH_BL	(0 << 19)
+#define WBURST_LENGTH_SINGLE	(1 << 19)
+#define CAS_2			(2 << 14)
+#define CAS_3			(3 << 14)
+#define BAT_SEQUENTIAL		(0 << 13)
+#define BAT_INTERLEAVED		(1 << 13)
+#define OPM_NORMAL		(0 << 17)
+#define SDRAM_DEVICE_MODE	(WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4)
+
+
+#define TIMER1_BASE	(0x80000C00)
+
+/*
+ * special lookup flags
+ */
+#define DO_MEM_DELAY	1
+#define DO_MEM_READ	2
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl memsetup
+memsetup:
+	mov	r9, lr	@ save return address
+
+	/* memory control configuration */
+	/* make r0 relative the current location so that it */
+	/* reads INITMEM_DATA out of FLASH rather than memory ! */
+	/*   r0 = current word pointer */
+	/*   r1 = end word location, one word past last actual word */
+	/*   r3 = address for writes, special lookup flags */
+	/*   r4 = value for writes, delay constants, or read addresses */
+	/*   r2 = location for mem reads */
+
+	ldr	r0, =INITMEM_DATA
+	ldr	r1, _TEXT_BASE
+	sub	r0, r0, r1
+	add	r1, r0, #112
+
+mem_loop:
+	cmp	r1, r0
+	moveq	pc, r9		@ Done
+
+	ldr	r3, [r0], #4	@ Fetch Destination Register Address, or 1 for delay
+	ldr	r4, [r0], #4	@ value
+
+	cmp	r3, #DO_MEM_DELAY
+	bleq	mem_delay
+	beq	mem_loop
+	cmp	r3, #DO_MEM_READ
+	ldreq	r2, [r4]
+	beq	mem_loop
+	str	r4, [r3]	@ normal register/ram store
+	b	mem_loop
+
+mem_delay:
+	ldr	r5, =TIMER1_BASE
+	mov	r6, r4, LSR #1	@ timer resolution is ~2us
+	str	r6, [r5]
+	mov	r6, #0x88	@ using 508.469KHz clock, enable
+	str	r6, [r5, #8]
+0:	ldr	r6, [r5, #4]	@ timer value
+	cmp	r6, #0
+	bne	0b
+	mov	r6, #0		@ disable timer
+	str	r6, [r5, #8]
+	mov	pc, lr
+
+	.ltorg
+/* the literal pools origin */
+
+INITMEM_DATA:
+	.word	BCR0
+	.word	BCR0_FLASH
+	.word	BCR6
+	.word	BCR6_CPLD_SLOW
+	.word	BCR7
+	.word	BCR7_CPLD_FAST
+	.word	SDCSCX_BASE
+	.word	(SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
+	.word	GBLCNFG
+	.word	GC_CMD_NOP
+	.word	DO_MEM_DELAY
+	.word	200
+	.word	GBLCNFG
+	.word	GC_CMD_PRECHARGEALL
+	.word	RFSHTMR
+	.word	RFSHTMR_INIT
+	.word	DO_MEM_DELAY
+	.word	8
+	.word	RFSHTMR
+	.word	RFSHTMR_NORMAL
+	.word	GBLCNFG
+	.word	GC_CMD_MODE
+	.word	DO_MEM_READ
+	.word	(SDRAM_BASE | SDRAM_DEVICE_MODE)
+	.word	GBLCNFG
+	.word	GC_CMD_NORMAL
+	.word	SDCSCX_BASE
+	.word	(SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32)
--- a/board/lpd7a40x/u-boot.lds
+++ b/board/lpd7a40x/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/lh7a40x/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/lwmon/flash.c
+++ b/board/lwmon/flash.c
@@ -403,6 +403,26 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 			/* Disable interrupts which might cause a timeout here */
 			flag = disable_interrupts();

+			*addr = 0x00600060;	/* clear lock bit setup */
+			*addr = 0x00D000D0;	/* clear lock bit confirm */
+
+			udelay (1000);
+			/* This takes awfully long - up to 50 ms and more */
+			while (((status = *addr) & 0x00800080) != 0x00800080) {
+				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0x00FF00FF; /* reset to read mode */
+					return 1;
+				}
+
+				/* show that we're waiting */
+				if ((now - last) > 1000) {	/* every second */
+					putc ('.');
+					last = now;
+				}
+				udelay (1000);	/* to trigger the watchdog */
+			}
+
 			*addr = 0x00500050;	/* clear status register */
 			*addr = 0x00200020;	/* erase setup */
 			*addr = 0x00D000D0;	/* erase confirm */
@@ -427,6 +447,7 @@ int	flash_erase (flash_info_t *info, int s_first, int s_last)
 					putc ('.');
 					last = now;
 				}
+				udelay (1000);	/* to trigger the watchdog */
 			}

 			*addr = 0x00FF00FF;	/* reset to read mode */
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -40,6 +40,7 @@ V* Verification:  dzu@denx.de
 #include <command.h>
 #include <malloc.h>
 #include <post.h>
+#include <serial.h>

 #include <linux/types.h>
 #include <linux/string.h>	/* for strdup */
@@ -468,6 +469,13 @@ int board_postclk_init (void)
 	return (0);
 }

+struct serial_device * default_serial_console (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
+}
+
 static void kbd_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
--- a/board/mpc8540ads/config.mk
+++ b/board/mpc8540ads/config.mk
@@ -1,3 +1,4 @@
+# Copyright 2004 Freescale Semiconductor.
 # Modified by Xianghua Xiao, X.Xiao@motorola.com
 # (C) Copyright 2002,Motorola Inc.
 #
--- a/board/mpc8540ads/flash.c
+++ b/board/mpc8540ads/flash.c
@@ -86,14 +86,12 @@ unsigned long flash_init (void)

 	flash_info[0].size = size;

-#if !defined(CONFIG_RAM_AS_FLASH)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
 		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
-#endif

 #ifdef	CFG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
--- a/board/mpc8540ads/init.S
+++ b/board/mpc8540ads/init.S
@@ -1,25 +1,26 @@
 /*
-* Copyright (C) 2002,2003, Motorola Inc.
-* Xianghua Xiao <X.Xiao@motorola.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -28,6 +29,24 @@
 #include <config.h>
 #include <mpc85xx.h>

+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
 #define	entry_start \
 	mflr	r1 	;	\
 	bl	0f 	;
@@ -37,142 +56,225 @@
 	mtlr	r1	;	\
 	blr		;

-/* TLB1 entries configuration: */

 	.section	.bootpg, "ax"
 	.globl	tlb1_entry
 tlb1_entry:
 	entry_start

-	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13

-	.long TLB1_MAS0(1,1,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif

-  #if defined(CFG_FLASH_PORT_WIDTH_16)
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
-  #else
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-  #endif
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)

-  #if !defined(CONFIG_SPD_EEPROM)
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-  #else
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-  #endif
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,6,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-  #if defined(CONFIG_RAM_AS_FLASH)
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-  #else
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-  #endif
-	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,7,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-  #ifdef CONFIG_L2_INIT_RAM
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
-  #else
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-  #endif
-	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,8,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,9,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,1,0,1,0,1)
+#endif

-  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-  #else
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-  #endif
 	entry_end

-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(128M) -or- larger
- * f000_0000-f3ff_ffff: PCI(256M)
- * f400_0000-f7ff_ffff: RapidIO(128M)
- * f800_0000-ffff_ffff: localbus(128M)
- *   f800_0000-fbff_ffff: LBC SDRAM(64M)
- *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
- *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
- *   fe00_0000-ffff_ffff: Flash(32M)
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- *       Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
 */

 #if !defined(CONFIG_SPD_EEPROM)
 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0 	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
 #else
 #define LAWBAR0 0
 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 #endif

-#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))

-#if !defined(CONFIG_RAM_AS_FLASH)
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR2 0
-#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+

 	.section .bootpg, "ax"
 	.globl	law_entry
 law_entry:
 	entry_start
-	.long 0x03
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
 	entry_end
--- a/board/mpc8540ads/mpc8540ads.c
+++ b/board/mpc8540ads/mpc8540ads.c
@@ -1,4 +1,5 @@
-/*
+ /*
+ * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003, Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
@@ -24,29 +25,23 @@
 */


-extern long int spd_sdram (void);
-
 #include <common.h>
+#include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <spd.h>

-long int fixed_sdram (void);
-
-/* MPC8540ADS Board Status & Control Registers */
-#if 0
-typedef struct bscr_ {
-	unsigned long bcsr0;
-	unsigned long bcsr1;
-	unsigned long bcsr2;
-	unsigned long bcsr3;
-	unsigned long bcsr4;
-	unsigned long bcsr5;
-	unsigned long bcsr6;
-	unsigned long bcsr7;
-} bcsr_t;
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
 #endif

+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+
+
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
@@ -55,49 +50,51 @@ int board_early_init_f (void)

    pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
-	return 0;
+
+    return 0;
 }

 int checkboard (void)
 {
-	sys_info_t sysinfo;
+	puts("Board: ADS\n");

-	get_sys_info (&sysinfo);
+#ifdef CONFIG_PCI
+	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("    PCI1: disabled\n");
+#endif

-	printf ("Board: Motorola MPC8540ADS Board\n");
-	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
-	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
-	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
-	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
-		|| (CFG_LBC_LCRR & 0x0f) == 8) {
-		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
-	} else {
-		printf("\tLBC: unknown\n");
-	}
-	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
-	return (0);
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();
+
+	return 0;
 }

-long int initdram (int board_type)
+
+long int
+initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-#if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
-	sys_info_t sysinfo;
-	uint temp_lbcdll = 0;
-#endif
-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur= &immap->im_gur;
-#endif
-#if defined(CONFIG_DDR_DLL)
-	uint temp_ddrdll = 0;

-	/* Work around to stabilize DDR DLL */
-	temp_ddrdll = gur->ddrdllcr;
-	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
-	asm("sync;isync;msync");
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    uint temp_ddrdll = 0;
+
+	    /*
+	     * Work around to stabilize DDR DLL
+	     */
+	    temp_ddrdll = gur->ddrdllcr;
+	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	    asm("sync;isync;msync");
+	}
 #endif

 #if defined(CONFIG_SPD_EEPROM)
@@ -106,91 +103,142 @@ long int initdram (int board_type)
 	dram_size = fixed_sdram ();
 #endif

-#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
-	get_sys_info(&sysinfo);
-	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
-	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
-		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
-	} else {
-#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
-		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
 #endif
-		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+
+	/*
+	 * Initialize SDRAM.
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
 		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("    SDRAM: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
 	lbc->br2 = CFG_BR2_PRELIM;
 	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->lsdmr = CFG_LBC_LSDMR_1;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_3;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_5;
-	asm("sync");
+	asm("msync");
+
 	lbc->lsrt = CFG_LBC_LSRT;
-	asm("sync");
 	lbc->mrtpr = CFG_LBC_MRTPR;
 	asm("sync");
-#endif

-#if defined(CONFIG_DDR_ECC)
-	{
-		/* Initialize all of memory for ECC, then
-		 * enable errors */
-		uint *p = 0;
-		uint i = 0;
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
-		dma_init();
-		for (*p = 0; p < (uint *)(8 * 1024); p++) {
-			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
-			*p = (unsigned int)0xdeadbeef;
-			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
-		}
+	/*
+	 * Configure the SDRAM controller.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-		/* 8K */
-		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
-		/* 16K */
-		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
-		/* 32K */
-		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
-		/* 64K */
-		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
-		/* 128k */
-		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
-		/* 256k */
-		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
-		/* 512k */
-		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
-		/* 1M */
-		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
-		/* 2M */
-		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
-		/* 4M */
-		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-		for (i = 1; i < dram_size / 0x800000; i++) {
-			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
-		}
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-		/* Enable errors for ECC */
-		ddr->err_disable = 0x00000000;
-		asm("sync;isync;msync");
-	}
-#endif
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-	return dram_size;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
 }


@@ -260,6 +308,44 @@ long int fixed_sdram (void)
 	asm("sync; isync; msync");
 	udelay(500);
  #endif
-	return (CFG_SDRAM_SIZE * 1024 * 1024);
+	return CFG_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
--- a/board/mpc8560ads/config.mk
+++ b/board/mpc8560ads/config.mk
@@ -1,3 +1,4 @@
+# Copyright 2004 Freescale Semiconductor.
 # Modified by Xianghua Xiao, X.Xiao@motorola.com
 # (C) Copyright 2002,2003 Motorola Inc.
 #
--- a/board/mpc8560ads/flash.c
+++ b/board/mpc8560ads/flash.c
@@ -86,14 +86,12 @@ unsigned long flash_init (void)

 	flash_info[0].size = size;

-#if !defined(CONFIG_RAM_AS_FLASH)
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CFG_MONITOR_BASE,
 		      CFG_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
-#endif

 #ifdef	CFG_ENV_IS_IN_FLASH
 	/* ENV protection ON by default */
--- a/board/mpc8560ads/init.S
+++ b/board/mpc8560ads/init.S
@@ -1,25 +1,26 @@
 /*
-* Copyright (C) 2002,2003, Motorola Inc.
-* Xianghua Xiao <X.Xiao@motorola.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * Copyright 2004 Freescale Semiconductor.
+ * Copyright (C) 2002,2003, Motorola Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */

 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
@@ -28,6 +29,24 @@
 #include <config.h>
 #include <mpc85xx.h>

+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
 #define	entry_start \
 	mflr	r1 	;	\
 	bl	0f 	;
@@ -37,142 +56,225 @@
 	mtlr	r1	;	\
 	blr		;

-/* TLB1 entries configuration: */

 	.section	.bootpg, "ax"
 	.globl	tlb1_entry
 tlb1_entry:
 	entry_start

-	.long 0x0a	/* the following data table uses a few of 16 TLB entries */
+	/*
+	 * Number of TLB0 and TLB1 entries in the following table
+	 */
+	.long 13

-	.long TLB1_MAS0(1,1,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+	/*
+	 * TLB0		4K	Non-cacheable, guarded
+	 * 0xff700000	4K	Initial CCSRBAR mapping
+	 *
+	 * This ends up at a TLB0 Index==0 entry, and must not collide
+	 * with other TLB0 Entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+#else
+#error("Update the number of table entries in tlb1_entry")
+#endif

-  #if defined(CFG_FLASH_PORT_WIDTH_16)
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB0		16K	Cacheable, non-guarded
+	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 *
+	 * Use four 4K TLB0 entries.  These entries must be cacheable
+	 * as they provide the bootstrap memory before the memory
+	 * controler and real memory have been configured.
+	 *
+	 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+	 * and must not collide with other TLB0 entries.
+	 */
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
-	.long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
-  #else
-	.long TLB1_MAS0(1,2,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
-	.long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,3,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-  #endif
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+			0,0,0,0,0,1,0,1,0,1)

-  #if !defined(CONFIG_SPD_EEPROM)
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS0(0, 0, 0)
+	.long TLB1_MAS1(1, 0, 0, 0, 0)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-  #else
-	.long TLB1_MAS0(1,4,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,5,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-  #endif
+	/*
+	 * TLB 0:	16M	Non-cacheable, guarded
+	 * 0xff000000	16M	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	.long TLB1_MAS0(1, 0, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,6,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
-  #if defined(CONFIG_RAM_AS_FLASH)
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-  #else
-	.long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-  #endif
-	.long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 1:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	.long TLB1_MAS0(1, 1, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,7,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-  #ifdef CONFIG_L2_INIT_RAM
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
-  #else
-	.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
-  #endif
-	.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 2:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	.long TLB1_MAS0(1, 2, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,8,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 3:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	Rapid IO MEM First half
+	 */
+	.long TLB1_MAS0(1, 3, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)

-	.long TLB1_MAS0(1,9,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
-	.long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 */
+	.long TLB1_MAS0(1, 4, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 5:	64M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 * 0xe200_0000	16M	PCI1 IO
+	 */
+	.long TLB1_MAS0(1, 5, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 6:	64M	Cacheable, non-guarded
+	 * 0xf000_0000	64M	LBC SDRAM
+	 */
+	.long TLB1_MAS0(1, 6, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	/*
+	 * TLB 7:	16K	Non-cacheable, guarded
+	 * 0xf8000000	16K	BCSR registers
+	 */
+	.long TLB1_MAS0(1, 7, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), 0,0,0,0,0,1,0,1,0,1)
+
+#if !defined(CONFIG_SPD_EEPROM)
+	/*
+	 * TLB 8, 9:	128M	DDR
+	 * 0x00000000	64M	DDR System memory
+	 * 0x04000000	64M	DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+#error("Update the number of table entries in tlb1_entry")
+	.long TLB1_MAS0(1, 8, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+
+	.long TLB1_MAS0(1, 9, 0)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE + 0x4000000),
+			0,0,0,0,0,1,0,1,0,1)
+#endif

-  #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
-  #else
-	.long TLB1_MAS0(1,15,0)
-	.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
-  #endif
 	entry_end

-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(128M) -or- larger
- * f000_0000-f3ff_ffff: PCI(256M)
- * f400_0000-f7ff_ffff: RapidIO(128M)
- * f800_0000-ffff_ffff: localbus(128M)
- *   f800_0000-fbff_ffff: LBC SDRAM(64M)
- *   fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
- *   fdf0_0000-fdff_ffff: CCSRBAR(1M)
- *   fe00_0000-ffff_ffff: Flash(32M)
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- *       Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x7fff_ffff     DDR                     2G
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xe200_0000     0xe2ff_ffff     PCI1 IO                 16M
+ * 0xf000_0000     0xf7ff_ffff     SDRAM                   128M
+ * 0xf800_0000     0xf80f_ffff     BCSR                    1M
+ * 0xff00_0000     0xffff_ffff     FLASH (boot bank)       16M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
 */

 #if !defined(CONFIG_SPD_EEPROM)
 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR0  (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#define LAWAR0	(LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
 #else
 #define LAWBAR0 0
 #define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
 #endif

-#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1  (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))

-#if !defined(CONFIG_RAM_AS_FLASH)
+/*
+ * This is not so much the SDRAM map as it is the whole localbus map.
+ */
 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR2  (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
-#else
-#define LAWBAR2 0
-#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-#endif
+#define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
+#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+
+/*
+ * Rapid IO at 0xc000_0000 for 512 M
+ */
+#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
+#define LAWAR4	(LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+

 	.section .bootpg, "ax"
-	.globl  law_entry
+	.globl	law_entry
 law_entry:
 	entry_start
-	.long 0x03
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+	.long 0x05
+	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
+	.long LAWBAR4,LAWAR4
 	entry_end
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2003,Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
@@ -24,16 +25,24 @@
 */


-extern long int spd_sdram (void);
-
 #include <common.h>
+#include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
 #include <spd.h>
 #include <miiphy.h>

-long int fixed_sdram (void);
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void local_bus_init(void);
+void sdram_init(void);
+long int fixed_sdram(void);
+

 /*
 * I/O Port configuration table
@@ -189,8 +198,11 @@ const iop_conf_t iop_conf_tab[4][32] = {
    }
 };

-/* MPC8560ADS Board Status & Control Registers */
-typedef struct bscr_ {
+
+/*
+ * MPC8560ADS Board Status & Control Registers
+ */
+typedef struct bcsr_ {
 	volatile unsigned char bcsr0;
 	volatile unsigned char bcsr1;
 	volatile unsigned char bcsr2;
@@ -199,15 +211,17 @@ typedef struct bscr_ {
 	volatile unsigned char bcsr5;
 } bcsr_t;

+
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
    volatile immap_t *immr = (immap_t *)CFG_IMMR;
    volatile ccsr_pcix_t *pci = &immr->im_pcix;

-    pci->peer &= 0xfffffffdf; /* disable master abort */
+    pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
-	return 0;
+
+    return 0;
 }

 void reset_phy (void)
@@ -236,49 +250,48 @@ void reset_phy (void)
 #endif /* CONFIG_MII */
 }

+
 int checkboard (void)
 {
-	sys_info_t sysinfo;
+	puts("Board: ADS\n");

-	get_sys_info (&sysinfo);
+#ifdef CONFIG_PCI
+	printf("    PCI1: 32 bit, %d MHz (compiled)\n",
+	       CONFIG_SYS_CLK_FREQ / 1000000);
+#else
+	printf("    PCI1: disabled\n");
+#endif

-	printf ("Board: Motorola MPC8560ADS Board\n");
-	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
-	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
-	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
-	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
-		|| (CFG_LBC_LCRR & 0x0f) == 8) {
-		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
-	} else {
-		printf("\tLBC: unknown\n");
-	}
-	printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
-	printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init();

-	return (0);
+	return 0;
 }


-long int initdram (int board_type)
+long int
+initdram(int board_type)
 {
 	long dram_size = 0;
 	extern long spd_sdram (void);
 	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-#if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
-	sys_info_t sysinfo;
-	uint temp_lbcdll = 0;
-#endif
-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur= &immap->im_gur;
-#endif
-#if defined(CONFIG_DDR_DLL)
-	uint temp_ddrdll = 0;

-	/* Work around to stabilize DDR DLL */
-	temp_ddrdll = gur->ddrdllcr;
-	gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
-	asm("sync;isync;msync");
+	puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+	{
+	    volatile ccsr_gur_t *gur= &immap->im_gur;
+	    uint temp_ddrdll = 0;
+
+	    /*
+	     * Work around to stabilize DDR DLL
+	     */
+	    temp_ddrdll = gur->ddrdllcr;
+	    gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+	    asm("sync;isync;msync");
+	}
 #endif

 #if defined(CONFIG_SPD_EEPROM)
@@ -287,91 +300,142 @@ long int initdram (int board_type)
 	dram_size = fixed_sdram ();
 #endif

-#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
-	get_sys_info(&sysinfo);
-	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
-	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
-		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
-	} else {
-#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
-		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#if defined(CONFIG_DDR_ECC)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
 #endif
-		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+
+	/*
+	 * Initialize SDRAM.
+	 */
+	sdram_init();
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+/*
+ * Initialize Local Bus
+ */
+
+void
+local_bus_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+
+	uint clkdiv;
+	uint lbc_hz;
+	sys_info_t sysinfo;
+
+	/*
+	 * Errata LBC11.
+	 * Fix Local Bus clock glitch when DLL is enabled.
+	 *
+	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
+	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
+	 * Between 66 and 133, the DLL is enabled with an override workaround.
+	 */
+
+	get_sys_info(&sysinfo);
+	clkdiv = lbc->lcrr & 0x0f;
+	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+	if (lbc_hz < 66) {
+		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+
+	} else if (lbc_hz >= 133) {
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+
+	} else {
+		/*
+		 * On REV1 boards, need to change CLKDIV before enable DLL.
+		 * Default CLKDIV is 8, change it to 4 temporarily.
+		 */
+		uint pvr = get_pvr();
+		uint temp_lbcdll = 0;
+
+		if (pvr == PVR_85xx_REV1) {
+			/* FIXME: Justify the high bit here. */
+			lbc->lcrr = 0x10000004;
+		}
+
+		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
 		udelay(200);
+
+		/*
+		 * Sample LBC DLL ctrl reg, upshift it to set the
+		 * override bits.
+		 */
 		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+}
+
+
+/*
+ * Initialize SDRAM memory on the Local Bus.
+ */
+
+void
+sdram_init(void)
+{
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+
+	puts("    SDRAM: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+
+	/*
+	 * Setup SDRAM Base and Option Registers
+	 */
+	lbc->or2 = CFG_OR2_PRELIM;
 	lbc->br2 = CFG_BR2_PRELIM;
 	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->lsdmr = CFG_LBC_LSDMR_1;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_3;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
-	asm("sync");
-	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_5;
-	asm("sync");
+	asm("msync");
+
 	lbc->lsrt = CFG_LBC_LSRT;
-	asm("sync");
 	lbc->mrtpr = CFG_LBC_MRTPR;
 	asm("sync");
-#endif

-#if defined(CONFIG_DDR_ECC)
-	{
-		/* Initialize all of memory for ECC, then
-		 * enable errors */
-		uint *p = 0;
-		uint i = 0;
-		volatile immap_t *immap = (immap_t *)CFG_IMMR;
-		volatile ccsr_ddr_t *ddr= &immap->im_ddr;
-		dma_init();
-		for (*p = 0; p < (uint *)(8 * 1024); p++) {
-			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
-			*p = (unsigned int)0xdeadbeef;
-			if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
-		}
+	/*
+	 * Configure the SDRAM controller.
+	 */
+	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-		/* 8K */
-		dma_xfer((uint *)0x2000,0x2000,(uint *)0);
-		/* 16K */
-		dma_xfer((uint *)0x4000,0x4000,(uint *)0);
-		/* 32K */
-		dma_xfer((uint *)0x8000,0x8000,(uint *)0);
-		/* 64K */
-		dma_xfer((uint *)0x10000,0x10000,(uint *)0);
-		/* 128k */
-		dma_xfer((uint *)0x20000,0x20000,(uint *)0);
-		/* 256k */
-		dma_xfer((uint *)0x40000,0x40000,(uint *)0);
-		/* 512k */
-		dma_xfer((uint *)0x80000,0x80000,(uint *)0);
-		/* 1M */
-		dma_xfer((uint *)0x100000,0x100000,(uint *)0);
-		/* 2M */
-		dma_xfer((uint *)0x200000,0x200000,(uint *)0);
-		/* 4M */
-		dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-		for (i = 1; i < dram_size / 0x800000; i++) {
-			dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
-		}
+	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-		/* Enable errors for ECC */
-		ddr->err_disable = 0x00000000;
-		asm("sync;isync;msync");
-	}
-#endif
+	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);

-	return dram_size;
+	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	asm("sync");
+	*sdram_addr = 0xff;
+	ppcDcbf((unsigned long) sdram_addr);
+	udelay(100);
 }


@@ -409,6 +473,7 @@ int testdram (void)
 }
 #endif

+
 #if !defined(CONFIG_SPD_EEPROM)
 /*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
@@ -440,6 +505,44 @@ long int fixed_sdram (void)
 	asm("sync; isync; msync");
 	udelay(500);
  #endif
-	return ( CFG_SDRAM_SIZE * 1024 * 1024);
+	return CFG_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
+
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+      PCI_IDSEL_NUMBER, PCI_ANY_ID,
+      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+				   PCI_ENET0_MEMADDR,
+				   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+      } },
+    { }
+};
+#endif
+
+
+static struct pci_controller hose = {
+#ifndef CONFIG_PCI_PNP
+	config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+#endif	/* CONFIG_PCI */
+
+
+void
+pci_init_board(void)
+{
+#ifdef CONFIG_PCI
+	extern void pci_mpc85xx_init(struct pci_controller *hose);
+
+	pci_mpc85xx_init(&hose);
+#endif /* CONFIG_PCI */
+}
--- a/board/mx1ads/Makefile
+++ b/board/mx1ads/Makefile
@@ -0,0 +1,48 @@
+#
+# board/mx1ads/Makefile
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mx1ads.o syncflash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/mx1ads/config.mk
+++ b/board/mx1ads/config.mk
@@ -0,0 +1,25 @@
+#
+# board/mx1ads/config.mk
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <minglen_wu@techware.com.tw>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+TEXT_BASE = 0x08400000
--- a/board/mx1ads/memsetup.S
+++ b/board/mx1ads/memsetup.S
@@ -0,0 +1,81 @@
+/*
+ * board/mx1ads/memsetup.S
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+#define SDCTL0			0x221000
+#define SDCTL1			0x221004
+
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+.globl memsetup
+memsetup:
+/* memory controller init	 	*/
+
+	ldr  r1, =SDCTL0
+
+/*  Set Precharge Command		*/
+
+	ldr  r3, =0x92120200
+/*	ldr  r3, =0x92120251
+*/
+	str  r3, [r1]
+
+/* Issue Precharge All Commad		*/
+	ldr  r3, =0x8200000
+	ldr  r2, [r3]
+
+/* Set AutoRefresh Command 		*/
+	ldr  r3, =0xA2120200
+	str  r3, [r1]
+
+/* Issue AutoRefresh Command		*/
+	ldr  r3, =0x8000000
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+	ldr  r2, [r3]
+
+/* Set Mode Register 			*/
+	ldr  r3, =0xB2120200
+	str  r3, [r1]
+
+/* Issue Mode Register Command		*/
+	ldr  r3, =0x08111800 	/* Mode Register Value 		*/
+	ldr  r2, [r3]
+
+/* Set Normal Mode			*/
+	ldr  r3, =0x82124200
+	str  r3, [r1]
+
+/* everything is fine now 		*/
+	mov	pc, lr
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -0,0 +1,168 @@
+/*
+ * board/mx1ads/mx1ads.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <mc9328.h>*/
+#include <asm/arch-arm920t/imx-regs.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define FCLK_SPEED 1
+
+#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
+#define M_MDIV	0xC3
+#define M_PDIV	0x4
+#define M_SDIV	0x1
+#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
+#define M_MDIV	0xA1
+#define M_PDIV	0x3
+#define M_SDIV	0x1
+#endif
+
+#define USB_CLOCK 1
+
+#if USB_CLOCK==0
+#define U_M_MDIV	0xA1
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x1
+#elif USB_CLOCK==1
+#define U_M_MDIV	0x48
+#define U_M_PDIV	0x3
+#define U_M_SDIV	0x2
+#endif
+
+#if 0
+
+static inline void delay (unsigned long loops) {
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b":"=r" (loops):"0" (loops));
+}
+
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+void SetAsynchMode(void) {
+	__asm__ (
+		"mrc p15,0,r0,c1,c0,0 \n"
+		"mov r2, #0xC0000000 \n"
+		"orr r0,r2,r0 \n"
+		"mcr p15,0,r0,c1,c0,0 \n"
+	);
+}
+
+static u32 mc9328sid;
+
+int board_init (void) {
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile unsigned int  tmp;
+
+	mc9328sid	= SIDR;
+
+	GPCR 		= 0x000003AB;		/* I/O pad driving strength 	*/
+
+/*	MX1_CS1U 	= 0x00000A00;	*/	/* SRAM initialization 		*/
+/*	MX1_CS1L 	= 0x11110601; 	*/
+
+	MPCTL0 		= 0x04632410;	/* setting for 150 MHz MCU PLL CLK	*/
+
+/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
+ * BCLK divider to 2 (i.e. BCLK to 48 MHz)
+ */
+	CSCR 	= 0xAF000403;
+
+	CSCR 	|= 0x00200000;   	/* Trigger the restart bit(bit 21)	*/
+	CSCR 	&= 0xFFFF7FFF;		/* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+
+/* setup cs4 for cs8900 ethernet */
+
+	CS4U	= 0x00000F00;	/* Initialize CS4 for CS8900 ethernet 	*/
+	CS4L	= 0x00001501;
+
+	GIUS(0)	&= 0xFF3FFFFF;
+	GPR(0)	&= 0xFF3FFFFF;
+
+	tmp = *(unsigned int *)(0x1500000C);
+	tmp = *(unsigned int *)(0x1500000C);
+
+	SetAsynchMode();
+
+	gd->bd->bi_arch_number = 160;	/* Arch number of MX1ADS Board 		*/
+
+	gd->bd->bi_boot_params = 0x08000100;	/* adress of boot parameters	*/
+
+	icache_enable();
+	dcache_enable();
+
+/* set PERCLKs				*/
+	PCDR = 0x00000055;     	/* set PERCLKS				*/
+
+/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
+ * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
+ * all sources selected as normal interrupt
+ */
+
+/*	MX1_INTTYPEH = 0;
+	MX1_INTTYPEL = 0;
+*/
+	return 0;
+}
+
+int board_late_init(void) {
+
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+
+	switch	(mc9328sid) {
+		case 0x0005901d :
+			printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
+			break;
+		case 0x04d4c01d :
+			printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+			break;
+		case 0x00d4c01d :
+			printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
+			break;
+
+		default :
+			printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
+			break;
+	}
+	return 0;
+}
+
+int dram_init (void) {
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -0,0 +1,322 @@
+/*
+ * board/mx1ads/syncflash.c
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
+
+typedef unsigned long * p_u32;
+
+/* 4Mx16x2 IAM=0 CSD1 */
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*  Following Setting is for CSD1	*/
+#define SFCTL			0x00221004
+#define reg_SFCTL		__REG(SFCTL)
+
+#define SYNCFLASH_A10		(0x00100000)
+
+#define CMD_NORMAL		(0x81020300)			/* Normal Mode			*/
+#define CMD_PREC		(CMD_NORMAL + 0x10000000) 	/* Precharge Command		*/
+#define CMD_AUTO		(CMD_NORMAL + 0x20000000) 	/* Auto Refresh Command		*/
+#define CMD_LMR			(CMD_NORMAL + 0x30000000) 	/* Load Mode Register Command 	*/
+#define CMD_LCR			(CMD_NORMAL + 0x60000000) 	/* LCR Command			*/
+#define CMD_PROGRAM		(CMD_NORMAL + 0x70000000)
+
+#define MODE_REG_VAL		(CFG_FLASH_BASE+0x0008CC00) 	/* Cas Latency 3		*/
+
+/* LCR Command */
+#define LCR_READSTATUS		(0x0001C000)			/* 0x70				*/
+#define LCR_ERASE_CONFIRM	(0x00008000)			/* 0x20				*/
+#define LCR_ERASE_NVMODE	(0x0000C000)			/* 0x30				*/
+#define LCR_PROG_NVMODE		(0x00028000)			/* 0xA0				*/
+#define LCR_SR_CLEAR		(0x00014000)			/* 0x50				*/
+
+/* Get Status register 			*/
+u32 SF_SR(void) {
+	u32 tmp,tmp1;
+
+	reg_SFCTL	= CMD_PROGRAM;
+	tmp 		= __REG(CFG_FLASH_BASE);
+
+	reg_SFCTL	= CMD_NORMAL;
+
+	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode 		*/
+	tmp1 		= __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
+
+	return tmp;
+}
+
+/* check if SyncFlash is ready 		*/
+u8 SF_Ready(void) {
+	u32 tmp;
+
+	tmp	= SF_SR();
+
+	if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
+		printf ("SyncFlash Error code %08x\n",tmp);
+	};
+
+	if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
+		printf ("SyncFlash Error code %08x\n",tmp);
+	};
+
+	if (tmp == 0x00800080) 		/* Test Bit 7 of SR	*/
+		return 1;
+	else
+		return 0;
+}
+
+/* Issue the precharge all command 		*/
+void SF_PrechargeAll(void) {
+
+	u32 tmp;
+
+	reg_SFCTL	= CMD_PREC;			/* Set Precharge Command 	*/
+	tmp 		= __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+}
+
+/* set SyncFlash to normal mode			*/
+void SF_Normal(void) {
+
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_NORMAL;
+}
+
+/* Erase SyncFlash 				*/
+void SF_Erase(u32 RowAddress) {
+	u32 tmp;
+
+	reg_SFCTL	= CMD_NORMAL;
+	tmp 		= __REG(RowAddress);
+
+	reg_SFCTL	= CMD_PREC;
+	tmp 		= __REG(RowAddress);
+
+	reg_SFCTL 	= CMD_LCR;			/* Set LCR mode 		*/
+	__REG(RowAddress + LCR_ERASE_CONFIRM)	= 0;	/* Issue Erase Setup Command 	*/
+
+	reg_SFCTL	= CMD_NORMAL;			/* return to Normal mode 	*/
+	__REG(RowAddress)	= 0xD0D0D0D0; 		/* Confirm			*/
+
+	while(!SF_Ready());
+}
+
+void SF_NvmodeErase(void) {
+	SF_PrechargeAll();
+
+	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
+	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
+
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode 	*/
+	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm 		*/
+
+	while(!SF_Ready());
+}
+
+void SF_NvmodeWrite(void) {
+	SF_PrechargeAll();
+
+	reg_SFCTL 	= CMD_LCR;			/* Set to LCR mode 		*/
+	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
+
+	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode 	*/
+	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; 	/* Confirm not needed 	*/
+}
+
+/****************************************************************************************/
+
+ulong flash_init(void) {
+	int i, j;
+	u32 tmp;
+
+/* Turn on CSD1 for negating RESETSF of SyncFLash */
+
+	reg_SFCTL 	|= 0x80000000;		/* enable CSD1 for SyncFlash 		*/
+	udelay(200);
+
+	reg_SFCTL 	= CMD_LMR;		/* Set Load Mode Register Command 	*/
+	tmp 		= __REG(MODE_REG_VAL);	/* Issue Load Mode Register Command 	*/
+
+	SF_Normal();
+
+	i = 0;
+
+	flash_info[i].flash_id 	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
+
+	flash_info[i].size 	= FLASH_BANK_SIZE;
+	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+
+	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+
+	for (j = 0; j < flash_info[i].sector_count; j++) {
+		flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
+	}
+
+	flash_protect(FLAG_PROTECT_SET,
+		CFG_FLASH_BASE,
+		CFG_FLASH_BASE + monitor_flash_len - 1,
+		&flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		CFG_ENV_ADDR,
+		CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+		&flash_info[0]);
+
+	return FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t *info) {
+
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case (FLASH_MAN_MT & FLASH_VENDMASK):
+			printf("Micron: ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
+			printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			return;
+			break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses: ");
+
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------*/
+
+int flash_erase (flash_info_t *info, int s_first, int s_last) {
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+
+/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last))
+		return ERR_INVAL;
+
+	if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
+		return ERR_UNKNOWN_FLASH_VENDOR;
+
+	prot = 0;
+
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf("protected!\n");
+		return ERR_PROTECTED;
+	}
+/*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+	cflag = icache_status();
+	icache_disable();
+	iflag = disable_interrupts();
+
+/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
+
+		printf("Erasing sector %2d ... ", sect);
+
+/* arm simple, non interrupt dependent timer */
+
+		reset_timer_masked();
+
+		SF_NvmodeErase();
+		SF_NvmodeWrite();
+
+		SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
+		SF_Normal();
+
+		printf("ok.\n");
+	}
+
+	if (ctrlc())
+		printf("User Interrupt!\n");
+
+	if (iflag)
+		enable_interrupts();
+
+	if (cflag)
+		icache_enable();
+
+	return rc;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
+	int i;
+
+	for(i = 0; i < cnt; i += 4) {
+
+		SF_PrechargeAll();
+
+		reg_SFCTL	= CMD_PROGRAM;		/* Enter SyncFlash Program mode */
+		__REG(addr + i) = __REG((u32)src  + i);
+
+		while(!SF_Ready());
+	}
+
+	SF_Normal();
+
+	return ERR_OK;
+}
--- a/board/mx1ads/u-boot.lds
+++ b/board/mx1ads/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * board/mx1ads/u-boot.lds
+ *
+ * (c) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * Ming-Len Wu <minglen_wu@techware.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/mx1fs2/Makefile
+++ b/board/mx1fs2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mx1fs2.o flash.o
+SOBJS	:= memsetup.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- a/board/mx1fs2/config.mk
+++ b/board/mx1fs2/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of IMX sources
+#
+# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+TEXT_BASE = 0x08f00000
--- a/board/mx1fs2/flash.c
+++ b/board/mx1fs2/flash.c
@@ -0,0 +1,914 @@
+/*
+ * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) 2003 August Hoeraendl, Logotronic GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef CONFIG_FLASH_16BIT
+
+#include <common.h>
+
+#if defined CFG_JFFS_CUSTOM_PART
+#include <jffs2/jffs2.h>
+#endif
+
+#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
+#define MAIN_SECT_SIZE  MX1FS2_FLASH_SECT_SIZE
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips   */
+
+/*
+ * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define	FLASH_ID_MASK	0xFFFFFFFF
+#endif
+
+#define FPW	FLASH_PORT_WIDTH
+#define FPWV	FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+#if 0
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+#endif
+static void flash_reset(flash_info_t * info);
+static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+#define write_word(in, de, da)   write_word_amd(in, de, da)
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t * info);
+#endif
+
+#if defined CFG_JFFS_CUSTOM_PART
+
+/**
+ * jffs2_part_info - get information about a JFFS2 partition
+ *
+ * @part_num: number of the partition you want to get info about
+ * @return:   struct part_info* in case of success, 0 if failure
+ */
+
+static struct part_info part;
+static int current_part = -1;
+
+struct part_info *
+jffs2_part_info(int part_num)
+{
+	void *jffs2_priv_saved = part.jffs2_priv;
+
+	printf("jffs2_part_info: part_num=%i\n", part_num);
+
+	if (current_part == part_num)
+		return &part;
+
+	/* rootfs                                                 */
+	if (part_num == 0) {
+		memset(&part, 0, sizeof (part));
+
+		part.offset = (char *) MX1FS2_JFFS2_PART0_START;
+		part.size = MX1FS2_JFFS2_PART0_SIZE;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
+		printf("part.size   = 0x%08x\n", (unsigned int) part.size);
+	}
+
+	/* userfs                                    */
+	if (part_num == 1) {
+		memset(&part, 0, sizeof (part));
+
+		part.offset = (char *) MX1FS2_JFFS2_PART1_START;
+		part.size = MX1FS2_JFFS2_PART1_SIZE;
+
+		/* Mark the struct as ready */
+		current_part = part_num;
+
+		printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
+		printf("part.size   = 0x%08x\n", (unsigned int) part.size);
+	}
+
+	if (current_part == part_num) {
+		part.usr_priv = &current_part;
+		part.jffs2_priv = jffs2_priv_saved;
+		return &part;
+	}
+
+	printf("jffs2_part_info: end of partition table\n");
+	return 0;
+}
+#endif				/* CFG_JFFS_CUSTOM_PART */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+ulong
+flash_init(void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+		flash_info[i].flash_id =
+		    (FLASH_MAN_AMD & FLASH_VENDMASK) |
+		    (FLASH_AM640U & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		switch (i) {
+		case 0:
+			flashbase = MX1FS2_FLASH_BASE;
+			break;
+		default:
+			panic("configured too many flash banks!\n");
+			break;
+		}
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors */
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_FLASH_BASE,
+		      CFG_FLASH_BASE + _bss_start - _armboot_start,
+		      &flash_info[0]);
+
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_reset(flash_info_t * info)
+{
+	FPWV *base = (FPWV *) (info->start[0]);
+
+	/* Put FLASH back in read mode */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+		*base = (FPW) 0x00FF00FF;	/* Intel Read Mode */
+	else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+		*base = (FPW) 0x00F000F0;	/* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+	    && (info->flash_id & FLASH_BTYPE)) {
+		int bootsect_size;	/* number of bytes/boot sector  */
+		int sect_size;	/* number of bytes/regular sector */
+
+		bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set sector offsets for bottom boot block type        */
+		for (i = 0; i < 8; ++i) {
+			info->start[i] = base + (i * bootsect_size);
+		}
+		for (i = 8; i < info->sector_count; i++) {
+			info->start[i] = base + ((i - 7) * sect_size);
+		}
+	} else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+		   && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+		int sect_size;	/* number of bytes/sector */
+
+		sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+		/* set up sector start address table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = base + (i * sect_size);
+	}
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+
+void
+flash_print_info(flash_info_t * info)
+{
+	int i;
+	uchar *boottype;
+	uchar *bootletter;
+	uchar *fmt;
+	uchar botbootletter[] = "B";
+	uchar topbootletter[] = "T";
+	uchar botboottype[] = "bottom boot sector";
+	uchar topboottype[] = "top boot sector";
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_BM:
+		printf("BRIGHT MICRO ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_SST:
+		printf("SST ");
+		break;
+	case FLASH_MAN_STM:
+		printf("STM ");
+		break;
+	case FLASH_MAN_INTEL:
+		printf("INTEL ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	/* check for top or bottom boot, if it applies */
+	if (info->flash_id & FLASH_BTYPE) {
+		boottype = botboottype;
+		bootletter = botbootletter;
+	} else {
+		boottype = topboottype;
+		bootletter = topbootletter;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM640U:
+		fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+		break;
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+		fmt = "28F800C3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL800B:
+	case FLASH_INTEL800T:
+		fmt = "28F800B3%s (8 Mbit, %s)\n";
+		break;
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+		fmt = "28F160C3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL160B:
+	case FLASH_INTEL160T:
+		fmt = "28F160B3%s (16 Mbit, %s)\n";
+		break;
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+		fmt = "28F320C3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL320B:
+	case FLASH_INTEL320T:
+		fmt = "28F320B3%s (32 Mbit, %s)\n";
+		break;
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		fmt = "28F640C3%s (64 Mbit, %s)\n";
+		break;
+	case FLASH_INTEL640B:
+	case FLASH_INTEL640T:
+		fmt = "28F640B3%s (64 Mbit, %s)\n";
+		break;
+	default:
+		fmt = "Unknown Chip Type\n";
+		break;
+	}
+
+	printf(fmt, bootletter, boottype);
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0) {
+			printf("\n   ");
+		}
+
+		printf(" %08lX%s", info->start[i],
+		       info->protect[i] ? " (RO)" : "     ");
+	}
+
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#if 0
+ulong
+flash_get_size(FPWV * addr, flash_info_t * info)
+{
+	/* Write auto select command: read Manufacturer ID */
+
+	/* Write auto select command sequence and test FLASH answer */
+	addr[0x0555] = (FPW) 0x00AA00AA;	/* for AMD, Intel ignores this */
+	addr[0x02AA] = (FPW) 0x00550055;	/* for AMD, Intel ignores this */
+	addr[0x0555] = (FPW) 0x00900090;	/* selects Intel or AMD */
+
+	/* The manufacturer codes are only 1 byte, so just use 1 byte.
+	 * This works for any bus width and any FLASH device width.
+	 */
+	switch (addr[0] & 0xff) {
+
+	case (uchar) AMD_MANUFACT:
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+
+	case (uchar) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		break;
+	}
+
+	/* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+	if (info->flash_id != FLASH_UNKNOWN)
+		switch (addr[1]) {
+
+		case (FPW) AMD_ID_LV640U:	/* 29LV640 and 29LV641 have same ID */
+			info->flash_id += FLASH_AM640U;
+			info->sector_count = 128;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F800C3B:
+			info->flash_id += FLASH_28F800C3B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F800B3B:
+			info->flash_id += FLASH_INTEL800B;
+			info->sector_count = 23;
+			info->size = 0x00100000 * (sizeof (FPW) / 2);
+			break;	/* => 1 or 2 MB         */
+
+		case (FPW) INTEL_ID_28F160C3B:
+			info->flash_id += FLASH_28F160C3B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F160B3B:
+			info->flash_id += FLASH_INTEL160B;
+			info->sector_count = 39;
+			info->size = 0x00200000 * (sizeof (FPW) / 2);
+			break;	/* => 2 or 4 MB         */
+
+		case (FPW) INTEL_ID_28F320C3B:
+			info->flash_id += FLASH_28F320C3B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F320B3B:
+			info->flash_id += FLASH_INTEL320B;
+			info->sector_count = 71;
+			info->size = 0x00400000 * (sizeof (FPW) / 2);
+			break;	/* => 4 or 8 MB         */
+
+		case (FPW) INTEL_ID_28F640C3B:
+			info->flash_id += FLASH_28F640C3B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		case (FPW) INTEL_ID_28F640B3B:
+			info->flash_id += FLASH_INTEL640B;
+			info->sector_count = 135;
+			info->size = 0x00800000 * (sizeof (FPW) / 2);
+			break;	/* => 8 or 16 MB        */
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* => no or unknown flash */
+		}
+
+	flash_get_offsets((ulong) addr, info);
+
+	/* Put FLASH back in read mode */
+	flash_reset(info);
+
+	return (info->size);
+}
+#endif /* 0 */
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void
+flash_sync_real_protect(flash_info_t * info)
+{
+	FPWV *addr = (FPWV *) (info->start[0]);
+	FPWV *sect;
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		/* check for protected sectors */
+		*addr = (FPW) 0x00900090;
+		for (i = 0; i < info->sector_count; i++) {
+			/* read sector protection at sector address, (A7 .. A0) = 0x02.
+			 * D0 = 1 for each device if protected.
+			 * If at least one device is protected the sector is marked
+			 * protected, but mixed protected and  unprotected devices
+			 * within a sector should never happen.
+			 */
+			sect = (FPWV *) (info->start[i]);
+			info->protect[i] =
+			    (sect[2] & (FPW) (0x00010001)) ? 1 : 0;
+		}
+
+		/* Put FLASH back in read mode */
+		flash_reset(info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		break;
+	}
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	FPWV *addr;
+	int flag, prot, sect;
+	int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+	ulong start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_INTEL800B:
+	case FLASH_INTEL160B:
+	case FLASH_INTEL320B:
+	case FLASH_INTEL640B:
+	case FLASH_28F800C3B:
+	case FLASH_28F160C3B:
+	case FLASH_28F320C3B:
+	case FLASH_28F640C3B:
+	case FLASH_AM640U:
+		break;
+	case FLASH_UNKNOWN:
+	default:
+		printf("Can't erase unknown flash type %08lx - aborted\n",
+		       info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		printf("\n");
+	}
+
+	start = get_timer(0);
+	last = start;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+		if (info->protect[sect] != 0)	/* protected, skip it */
+			continue;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr = (FPWV *) (info->start[sect]);
+		if (intel) {
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+		} else {
+			/* must be AMD style if not Intel */
+			FPWV *base;	/* first address in bank */
+
+			base = (FPWV *) (info->start[0]);
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			base[0x0555] = (FPW) 0x00800080;	/* erase mode */
+			base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+			base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+			*addr = (FPW) 0x00300030;	/* erase sector */
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 50us for AMD, 80us for Intel.
+		 * Let's wait 1 ms.
+		 */
+		udelay(1000);
+
+		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) {
+				printf("Timeout\n");
+
+				if (intel) {
+					/* suspend erase        */
+					*addr = (FPW) 0x00B000B0;
+				}
+
+				flash_reset(info);	/* reset to read mode */
+				rcode = 1;	/* failed */
+				break;
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc('.');
+				last = now;
+			}
+		}
+
+		flash_reset(info);	/* reset to read mode   */
+	}
+
+	printf(" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int
+bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	FPW data = 0;		/* 16 or 32 bit word, matches flash bus width on MPC8XX */
+	int bytes;		/* number of bytes to program in current word         */
+	int left;		/* number of bytes left to program                    */
+	int i, res;
+
+	for (left = cnt, res = 0;
+	     left > 0 && res == 0;
+	     addr += sizeof (data), left -= sizeof (data) - bytes) {
+
+		bytes = addr & (sizeof (data) - 1);
+		addr &= ~(sizeof (data) - 1);
+
+		/* combine source and destination data so can program
+		 * an entire word of 16 or 32 bits
+		 */
+		for (i = 0; i < sizeof (data); i++) {
+			data <<= 8;
+			if (i < bytes || i - bytes >= left)
+				data += *((uchar *) addr + i);
+			else
+				data += *src++;
+		}
+
+		/* write one word to the flash */
+		switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			res = write_word_amd(info, (FPWV *) addr, data);
+			break;
+		case FLASH_MAN_INTEL:
+			res = write_word_intel(info, (FPWV *) addr, data);
+			break;
+		default:
+			/* unknown flash type, error! */
+			printf("missing or unknown FLASH type\n");
+			res = 1;	/* not really a timeout, but gives error */
+			break;
+		}
+	}
+
+	return (res);
+}
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src:	source of copy transaction
+ * @param addr:	where to copy to
+ * @param cnt: 	number of bytes to copy
+ *
+ * @return	error code
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+	int l;
+	int i, rc;
+
+	wp = (addr & ~1);	/* get lower word aligned address */
+
+	/* handle unaligned start bytes */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+		for (; i < 2 && cnt > 0; ++i) {
+			data = (data >> 8) | (*src++ << 8);
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < 2; ++i, ++cp) {
+			data = (data >> 8) | (*(uchar *) cp << 8);
+		}
+
+		if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+			return (rc);
+		}
+		wp += 2;
+	}
+
+	/* handle word aligned part */
+	while (cnt >= 2) {
+		/* data = *((vushort*)src); */
+		data = *((FPW *) src);
+		if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+			return (rc);
+		}
+		src += sizeof (FPW);
+		wp += sizeof (FPW);
+		cnt -= sizeof (FPW);
+	}
+
+	if (cnt == 0)
+		return ERR_OK;
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+		data = (data >> 8) | (*src++ << 8);
+		--cnt;
+	}
+	for (; i < 2; ++i, ++cp) {
+		data = (data >> 8) | (*(uchar *) cp << 8);
+	}
+
+	return write_word(info, (FPWV *)wp, data);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_amd(flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+	FPWV *base;		/* first address in flash bank  */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	base = (FPWV *) (info->start[0]);
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	base[0x0555] = (FPW) 0x00AA00AA;	/* unlock */
+	base[0x02AA] = (FPW) 0x00550055;	/* unlock */
+	base[0x0555] = (FPW) 0x00A000A0;	/* selects program mode */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	/* data polling for D7 */
+	while (res == 0
+	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+		if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00F000F0;	/* reset bank */
+			printf("SHA timeout\n");
+			res = 1;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_intel(flash_info_t * info, FPWV * dest, FPW data)
+{
+	ulong start;
+	int flag;
+	int res = 0;		/* result, assume success       */
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*dest & data) != data) {
+		return (2);
+	}
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+	*dest = (FPW) 0x00400040;	/* program setup                */
+
+	*dest = data;		/* start programming the data   */
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	start = get_timer(0);
+
+	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
+			res = 1;
+		}
+	}
+
+	if (res == 0 && (*dest & (FPW) 0x00100010))
+		res = 1;	/* write failed, time out error is close enough */
+
+	*dest = (FPW) 0x00500050;	/* clear status register        */
+	*dest = (FPW) 0x00FF00FF;	/* make sure in read mode       */
+
+	return (res);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int
+flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+	int rcode = 0;		/* assume success */
+	FPWV *addr;		/* address of sector */
+	FPW value;
+
+	addr = (FPWV *) (info->start[sector]);
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F800C3B:
+	case FLASH_28F800C3T:
+	case FLASH_28F160C3B:
+	case FLASH_28F160C3T:
+	case FLASH_28F320C3B:
+	case FLASH_28F320C3T:
+	case FLASH_28F640C3B:
+	case FLASH_28F640C3T:
+		flash_reset(info);	/* make sure in read mode */
+		*addr = (FPW) 0x00600060L;	/* lock command setup */
+		if (prot)
+			*addr = (FPW) 0x00010001L;	/* lock sector */
+		else
+			*addr = (FPW) 0x00D000D0L;	/* unlock sector */
+		flash_reset(info);	/* reset to read mode */
+
+		/* now see if it really is locked/unlocked as requested */
+		*addr = (FPW) 0x00900090;
+		/* read sector protection at sector address, (A7 .. A0) = 0x02.
+		 * D0 = 1 for each device if protected.
+		 * If at least one device is protected the sector is marked
+		 * protected, but return failure. Mixed protected and
+		 * unprotected devices within a sector should never happen.
+		 */
+		value = addr[2] & (FPW) 0x00010001;
+		if (value == 0)
+			info->protect[sector] = 0;
+		else if (value == (FPW) 0x00010001)
+			info->protect[sector] = 1;
+		else {
+			/* error, mixed protected and unprotected */
+			rcode = 1;
+			info->protect[sector] = 1;
+		}
+		if (info->protect[sector] != prot)
+			rcode = 1;	/* failed to protect/unprotect as requested */
+
+		/* reload all protection bits from hardware for now */
+		flash_sync_real_protect(info);
+		break;
+
+	case FLASH_AM640U:
+	default:
+		/* no hardware protect that we support */
+		info->protect[sector] = prot;
+		break;
+	}
+
+	return rcode;
+}
+#endif
--- a/board/mx1fs2/intel.h
+++ b/board/mx1fs2/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ *     28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ *     28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef	FLASH_INTEL_H
+#define	FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define	CFI_INTEL_CMD_READ_ARRAY		0xFF	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_IDENTIFIER		0x90	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_QUERY		0x98	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_READ_STATUS_REGISTER	0x70	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CLEAR_STATUS_REGISTER	0x50	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM1			0x40	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_PROGRAM2			0x10	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_WRITE_TO_BUFFER		0xE8	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_CONFIRM			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_BLOCK_ERASE		0x20	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_SUSPEND			0xB0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_RESUME			0xD0	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_SETUP		0x60	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_BLOCK		0x01	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_UNLOCK_BLOCK		0xD0	/* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_CMD_LOCK_DOWN_BLOCK		0x2F	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define	CFI_INTEL_SR_READY			1 << 7	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_SUSPEND		1 << 6	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_ERASE_ERROR		1 << 5	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_ERROR		1 << 4	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_VPEN_ERROR			1 << 3	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_PROGRAM_SUSPEND		1 << 2	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BLOCK_LOCKED		1 << 1	/* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define	CFI_INTEL_SR_BEFP			1 << 0	/* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define	CFI_CHIP_INTEL_28F320J3A		0x0016
+#define	CFI_CHIPN_INTEL_28F320J3A		"28F320J3A"
+#define	CFI_CHIP_INTEL_28F640J3A		0x0017
+#define	CFI_CHIPN_INTEL_28F640J3A		"28F640J3A"
+#define	CFI_CHIP_INTEL_28F128J3A		0x0018
+#define	CFI_CHIPN_INTEL_28F128J3A		"28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define	CFI_CHIP_INTEL_28F640K3			0x8801
+#define	CFI_CHIPN_INTEL_28F640K3		"28F640K3"
+#define	CFI_CHIP_INTEL_28F128K3			0x8802
+#define	CFI_CHIPN_INTEL_28F128K3		"28F128K3"
+#define	CFI_CHIP_INTEL_28F256K3			0x8803
+#define	CFI_CHIPN_INTEL_28F256K3		"28F256K3"
+#define	CFI_CHIP_INTEL_28F640K18		0x8805
+#define	CFI_CHIPN_INTEL_28F640K18		"28F640K18"
+#define	CFI_CHIP_INTEL_28F128K18		0x8806
+#define	CFI_CHIPN_INTEL_28F128K18		"28F128K18"
+#define	CFI_CHIP_INTEL_28F256K18		0x8807
+#define	CFI_CHIPN_INTEL_28F256K18		"28F256K18"
+
+#endif				/* FLASH_INTEL_H */
--- a/board/mx1fs2/memsetup.S
+++ b/board/mx1fs2/memsetup.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl memsetup
+memsetup:
+
+	mov	r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+	ldr		r0,	=PCDR
+	ldr		r1,	=CFG_PCDR_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 0 */
+
+	ldr		r0,	=MPCTL0
+	ldr		r1,	=CFG_MPCTL0_VAL
+	str		r1,   [r0]
+
+/* set MCU PLL Control Register 1 */
+
+	ldr		r0,	=MPCTL1
+	ldr		r1,	=CFG_MPCTL1_VAL
+	str		r1,   [r0]
+
+/* set mpll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<21)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+/* set System PLL Control Register 0 */
+
+	ldr		r0,	=SPCTL0
+	ldr		r1,	=CFG_SPCTL0_VAL
+	str		r1,   [r0]
+
+/* set System PLL Control Register 1 */
+
+	ldr		r0,	=SPCTL1
+	ldr		r1,	=CFG_SPCTL1_VAL
+	str		r1,   [r0]
+
+/* set spll restart bit */
+	ldr		r0, =CSCR
+	ldr		r1, [r0]
+	orr		r1,r1,#(1<<22)
+	str		r1, [r0]
+
+	mov		r2,#0x10
+1:
+	mov		r3,#0x2000
+2:
+	subs	r3,r3,#1
+	bne		2b
+
+	subs	r2,r2,#1
+	bne		1b
+
+	ldr		r0,   =CSCR
+	ldr		r1,   =CFG_CSCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,   =GPCR
+	ldr		r1,   =CFG_GPCR_VAL
+	str		r1,   [r0]
+
+/*
+ * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ * this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+ *
+ * Slapping this into my bootloader does the trick...
+ *
+ * MRC p15,0,r0,c1,c0,0    ; read core configuration register
+ * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
+ * register
+ *
+ */
+	MRC p15,0,r0,c1,c0,0
+/*	ORR r0,r0,#0xC0000000 async mode */
+/*	ORR r0,r0,#0x40000000 sync mode */
+	ORR r0,r0,#0xC0000000
+	MCR p15,0,r0,c1,c0,0
+
+	ldr		r0,	=GIUS(0)
+	ldr		r1,	=CFG_GIUS_A_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=FMCR
+	ldr		r1,	=CFG_FMCR_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0U
+	ldr		r1,	=CFG_CS0U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS0L
+	ldr		r1,	=CFG_CS0L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1U
+	ldr		r1,	=CFG_CS1U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS1L
+	ldr		r1,	=CFG_CS1L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4U
+	ldr		r1,	=CFG_CS4U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS4L
+	ldr		r1,	=CFG_CS4L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5U
+	ldr		r1,	=CFG_CS5U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=CS5L
+	ldr		r1,	=CFG_CS5L_VAL
+	str		r1,   [r0]
+
+/* SDRAM Setup */
+
+	ldr  r1,=0x00221000   /* adr of SDCTRL0			*/
+	ldr  r0,=0x92120200
+	str  r0,[r1,#0]       /* put in precharge command mode    */
+	ldr  r2,=0x08200000   /* adr for precharge cmd 	   */
+	ldr  r0,[r2,#0]       /* precharge			   */
+	ldr  r0,=0xA2120200
+	ldr  r2,=0x08000000   /* start of SDRAM		   */
+	str  r0,[r1,#0]       /* put in auto-refresh mode	   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,[r2,#0]       /* auto-refresh  		   */
+	ldr  r0,=0xB2120200
+	ldr  r2,=0x08111800
+	str  r0,[r1,#0]       /* setup for mode register of SDRAM */
+	ldr  r0,[r2,#0]       /* program mode register 	   */
+	ldr  r0,=0x82124267
+	str  r0,[r1,#0]       /* back to normal operation	   */
+
+	mov	pc,r10
--- a/board/mx1fs2/mx1fs2.c
+++ b/board/mx1fs2/mx1fs2.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+
+#define SHOW_BOOT_PROGRESS(arg)        show_boot_progress(arg)
+
+extern void imx_gpio_mode(int gpio_mode);
+
+static void logo_init(void)
+{
+	imx_gpio_mode(PD15_PF_LD0);
+	imx_gpio_mode(PD16_PF_LD1);
+	imx_gpio_mode(PD17_PF_LD2);
+	imx_gpio_mode(PD18_PF_LD3);
+	imx_gpio_mode(PD19_PF_LD4);
+	imx_gpio_mode(PD20_PF_LD5);
+	imx_gpio_mode(PD21_PF_LD6);
+	imx_gpio_mode(PD22_PF_LD7);
+	imx_gpio_mode(PD23_PF_LD8);
+	imx_gpio_mode(PD24_PF_LD9);
+	imx_gpio_mode(PD25_PF_LD10);
+	imx_gpio_mode(PD26_PF_LD11);
+	imx_gpio_mode(PD27_PF_LD12);
+	imx_gpio_mode(PD28_PF_LD13);
+	imx_gpio_mode(PD29_PF_LD14);
+	imx_gpio_mode(PD30_PF_LD15);
+	imx_gpio_mode(PD14_PF_FLM_VSYNC);
+	imx_gpio_mode(PD13_PF_LP_HSYNC);
+	imx_gpio_mode(PD6_PF_LSCLK);
+	imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
+	imx_gpio_mode(PD11_PF_CONTRAST);
+	imx_gpio_mode(PD10_PF_SPL_SPR);
+
+	LCDC_RMCR = 0x00000000;
+	LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5);
+	LCDC_HCR = HCR_H_WIDTH(2);
+	LCDC_VCR = VCR_V_WIDTH(2);
+
+	LCDC_PWMR = 0x00000380;   /* contrast to 0x80 middle (is best !!!) */
+	LCDC_SSA  = 0x10040000;   /* image in flash */
+
+	LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240);   /* screen size */
+
+	LCDC_VPW  = 0x000000A0;   /* Virtual Page Width Register */
+	LCDC_POS  = 0x00000000;   /* panning offset 0 (0 pixel offset) */
+
+	/* disable Cursor */
+	LCDC_CPOS  = 0x00000000;
+
+	/* fixed burst length */
+	LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2);
+
+	/* enable LCD */
+	DR(3)   |= 0x00001000;
+	LCDC_RMCR = RMCR_LCDC_EN;
+
+}
+
+int
+board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_arch_number = 470;
+	gd->bd->bi_boot_params = 0x08000100;
+serial_init();
+	logo_init();
+	return 0;
+}
+
+int
+dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+	gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
+	gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;
+#endif
+	return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ */
+
+void
+show_boot_progress(int status)
+{
+	/* We use this as a hook to disable serial ports just before booting
+	 * This way we suppress the "uncompressing linux..." message
+	 */
+#ifdef CONFIG_SILENT_CONSOLE
+	if( status == 8) {
+		if( getenv("silent") != NULL ) {
+			*(volatile unsigned long *)0x206080 &= ~1;
+			*(volatile unsigned long *)0x207080 &= ~1;
+		}
+	}
+#endif
+	return;
+}
--- a/board/mx1fs2/u-boot.lds
+++ b/board/mx1fs2/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/arm920t/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
--- a/board/nc650/Makefile
+++ b/board/nc650/Makefile
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/adderII/config.mk
+++ b/board/adderII/config.mk
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000
+# (C) Copyright 2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -22,7 +22,7 @@
 #

 #
-# AdderII board ( Analogue-Micro )
+# NC650 board
 #

-TEXT_BASE = 0xFE000000
+TEXT_BASE = 0x40700000
--- a/board/nc650/flash.c
+++ b/board/nc650/flash.c
@@ -0,0 +1,542 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef DEBUG
+
+#include <common.h>
+#include <mpc8xx.h>
+
+#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				      OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef  CFG_ENV_ADDR
+#  define CFG_ENV_ADDR	(CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# ifndef  CFG_ENV_SECT_SIZE
+#  define CFG_ENV_SECT_SIZE  CFG_ENV_SIZE
+# endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/* Board support for 1 or 2 flash devices */
+#undef FLASH_PORT_WIDTH32
+#undef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH8
+
+#ifdef FLASH_PORT_WIDTH16
+#define FLASH_PORT_WIDTH	ushort
+#define FLASH_PORT_WIDTHV	vu_short
+#elif FLASH_PORT_WIDTH32
+#define FLASH_PORT_WIDTH	ulong
+#define FLASH_PORT_WIDTHV	vu_long
+#else /* FLASH_PORT_WIDTH8 */
+#define FLASH_PORT_WIDTH	uchar
+#define FLASH_PORT_WIDTHV	vu_char
+#endif
+
+#define FPW			FLASH_PORT_WIDTH
+#define FPWV			FLASH_PORT_WIDTHV
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (FPWV * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, FPW data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size_b0;
+	int i;
+#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
+	int scy, trlx, flash_or_timing, clk_diff;
+
+	DECLARE_GLOBAL_DATA_PTR;
+
+	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+		trlx = OR_TRLX;
+		scy *= 2;
+	} else
+		trlx = 0;
+
+		/* We assume that each 10MHz of bus clock require 1-clk SCY
+		 * adjustment.
+		 */
+	clk_diff = (gd->bus_clk / 1000000) - 50;
+
+		/* We need proper rounding here. This is what the "+5" and "-5"
+		 * are here for.
+		 */
+	if (clk_diff >= 0)
+		scy += (clk_diff + 5) / 10;
+	else
+		scy += (clk_diff - 5) / 10;
+
+		/* For bus frequencies above 50MHz, we want to use relaxed
+		 * timing (OR_TRLX).
+		 */
+	if (gd->bus_clk >= 50000000)
+		trlx = OR_TRLX;
+	else
+		trlx = 0;
+
+	if (trlx)
+		scy /= 2;
+
+	if (scy > 0xf)
+		scy = 0xf;
+	if (scy < 1)
+		scy = 1;
+
+	flash_or_timing = (scy << 4) | trlx |
+			  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+#endif
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+	size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+			size_b0, size_b0 << 20);
+	}
+
+	/* Remap FLASH according to real size */
+#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+#else
+	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
+#endif
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
+
+	/* Re-do sizing to get full correct info */
+	size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	/* monitor protection ON by default */
+	(void) flash_protect (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				&flash_info[0]);
+#endif
+
+#ifdef	CFG_ENV_IS_IN_FLASH
+	/* ENV protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+			CFG_ENV_ADDR,
+			CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
+			&flash_info[0]);
+#endif
+
+	flash_info[0].size = size_b0;
+
+	return (size_b0);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00020000);
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:
+		printf ("28F320J3A\n");
+		break;
+	case FLASH_28F640J3A:
+		printf ("28F640J3A\n");
+		break;
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+			info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (FPWV * addr, flash_info_t * info)
+{
+	FPW value;
+
+	addr[0] = (FPW) 0x00900090;
+
+	value = addr[0];
+
+	debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
+
+	switch (value) {
+	case (FPW) INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+		return (0);			/* no or unknown flash  */
+	}
+
+#ifdef FLASH_PORT_WIDTH8
+	value = addr[2];			/* device ID        */
+#else
+	value = addr[1];			/* device ID        */
+#endif
+
+	debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
+
+	switch (value) {
+	case (FPW) INTEL_ID_28F320J3A:
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;				/* => 4 MB     */
+
+	case (FPW) INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;				/* => 8 MB     */
+
+	case (FPW) INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;				/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+				info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type, start, now, last;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+			prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last = start;
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			FPWV *addr = (FPWV *) (info->start[sect]);
+			FPW status;
+
+			/* Disable interrupts which might cause a timeout here */
+			flag = disable_interrupts ();
+
+			*addr = (FPW) 0x00500050;	/* clear status register */
+			*addr = (FPW) 0x00200020;	/* erase setup */
+			*addr = (FPW) 0x00D000D0;	/* erase confirm */
+
+			/* re-enable interrupts if necessary */
+			if (flag)
+				enable_interrupts ();
+
+			/* wait at least 80us - let's wait 1 ms */
+			udelay (1000);
+
+			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
+				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+				rcode = 1;
+				break;
+			    }
+
+			    /* show that we're waiting */
+			    if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			    }
+			}
+
+			*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
+		}
+	}
+	printf (" done\n");
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	FPW data;
+
+	int i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return 4;
+	}
+/* get lower word aligned address */
+#ifdef FLASH_PORT_WIDTH16
+	wp = (addr & ~1);
+	port_width = 2;
+#elif defined(FLASH_PORT_WIDTH32)
+	wp = (addr & ~3);
+	port_width = 4;
+#else
+	wp = addr;
+	port_width = 1;
+#endif
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, FPW data)
+{
+	FPWV *addr = (FPWV *) dest;
+	ulong status;
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = (FPW) 0x00400040;	/* write setup */
+	*addr = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+
+	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
+
+	return (0);
+}
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <config.h>
+#include <mpc8xx.h>
+
+/*
+ *  Memory Controller Using
+ *
+ *  CS0 - Flash memory            (0x40000000)
+ *  CS3 - SDRAM                   (0x00000000}
+ */
+
+/* ------------------------------------------------------------------------- */
+
+#define _not_used_	0xffffffff
+
+const uint sdram_table[] = {
+	/* single read. (offset 0 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+	0x1ff77c47,
+
+	/* MRS initialization (offset 5) */
+
+	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
+
+	/* burst read. (offset 8 in upm RAM) */
+	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* single write. (offset 18 in upm RAM) */
+	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* burst write. (offset 20 in upm RAM) */
+	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* refresh. (offset 30 in upm RAM) */
+	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
+	_not_used_, _not_used_, _not_used_, _not_used_,
+
+	/* exception. (offset 3c in upm RAM) */
+	0x7ffffc07, _not_used_, _not_used_, _not_used_
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard (void)
+{
+	puts ("Board: NC650\n");
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	long int size8, size9;
+	long int size_b0 = 0;
+	unsigned long reg;
+
+	upmconfig (UPMA, (uint *) sdram_table,
+			   sizeof (sdram_table) / sizeof (uint));
+
+	/*
+	 * Preliminary prescaler for refresh (depends on number of
+	 * banks): This value is selected for four cycles every 62.4 us
+	 * with two SDRAM banks or four cycles every 31.2 us with one
+	 * bank. It will be adjusted after memory sizing.
+	 */
+	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+
+	memctl->memc_mar = 0x00000088;
+
+	/*
+	 * Map controller bank 1 to the SDRAM bank at
+	 * preliminary address - these have to be modified after the
+	 * SDRAM size has been determined.
+	 */
+	memctl->memc_or3 = CFG_OR3_PRELIM;
+	memctl->memc_br3 = CFG_BR3_PRELIM;
+
+	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+
+	udelay (200);
+
+	/* perform SDRAM initializsation sequence */
+
+	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 0 */
+	udelay (200);
+	memctl->memc_mcr = 0x80006230;	/* SDRAM bank 0 - execute twice */
+	udelay (200);
+
+	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
+
+	udelay (1000);
+
+	/*
+	 * Check Bank 0 Memory Size for re-configuration
+	 *
+	 * try 8 column mode
+	 */
+	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
+					   SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	/*
+	 * try 9 column mode
+	 */
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
+					  SDRAM_MAX_SIZE);
+
+	udelay (1000);
+
+	if (size8 < size9) {
+		size_b0 = size9;
+	} else {
+		size_b0 = size8;
+		memctl->memc_mamr = CFG_MAMR_8COL;
+		udelay (500);
+	}
+
+	/*
+	 * Adjust refresh rate depending on SDRAM type, both banks.
+	 * For types > 128 MBit leave it at the current (fast) rate
+	 */
+	if ((size_b0 < 0x02000000)) {
+		/* reduce to 15.6 us (62.4 us / quad) */
+		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		udelay (1000);
+	}
+
+	/*
+	 * Final mapping
+	 */
+
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+	/* adjust refresh rate depending on SDRAM type, one bank */
+	reg = memctl->memc_mptpr;
+	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	memctl->memc_mptpr = reg;
+
+	udelay (10000);
+
+	return (size_b0);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base,
+						   long int maxsize)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+
+	memctl->memc_mamr = mamr_value;
+
+	return (get_ram_size(base, maxsize));
+}
--- a/board/nc650/u-boot.lds
+++ b/board/nc650/u-boot.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/nc650/u-boot.lds.debug
+++ b/board/nc650/u-boot.lds.debug
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8xx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
--- a/board/netphone/flash.c
+++ b/board/netphone/flash.c
@@ -87,21 +87,22 @@ unsigned long flash_init(void)

 #if CONFIG_NETPHONE_VERSION == 2
 	size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
+	if (size1 > 0) {
+		if (flash_info[1].flash_id == FLASH_UNKNOWN)
+			printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);

-	if (flash_info[1].flash_id == FLASH_UNKNOWN && size1 > 0) {
-		printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
-	}
+		/* Remap FLASH according to real size */
+		memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
+		memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));

-	/* Remap FLASH according to real size */
-	memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
-	memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
+		/* Re-do sizing to get full correct info */
+		size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);

-	/* Re-do sizing to get full correct info */
-	size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
+		flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);

-	flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
-
-	size += size1;
+		size += size1;
+	} else
+		memctl->memc_br4 &= ~BR_V;
 #endif

 	return (size);
--- a/board/netphone/phone_console.c
+++ b/board/netphone/phone_console.c
@@ -12,7 +12,7 @@
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
@@ -52,7 +52,7 @@
 /*************************************************************************************************/

 #define DISPLAY_BACKLIT_PORT	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat
-#define DISPLAY_BACKLIT_MASK 	0x0010
+#define DISPLAY_BACKLIT_MASK	0x0010

 /*************************************************************************************************/

@@ -63,23 +63,23 @@
 #define KP_IDLE_DELAY_HZ	(CFG_HZ/2)	/* key was released and idle */

 #if CONFIG_NETPHONE_VERSION == 1
-#define KP_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_RXD_MASK	0x0008
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_RXD_MASK 0x0008

-#define KP_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_TXD_MASK	0x0004
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_TXD_MASK 0x0004

-#define KP_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_CLK_MASK	0x0001
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_CLK_MASK 0x0001
 #elif CONFIG_NETPHONE_VERSION == 2
-#define KP_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_RXD_MASK	0x00000008
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_RXD_MASK 0x00000008

-#define KP_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_TXD_MASK	0x00000004
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_TXD_MASK 0x00000004

-#define KP_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_CLK_MASK	0x00000002
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_CLK_MASK 0x00000002
 #endif

 #define KP_CS_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat)
@@ -115,8 +115,8 @@
 			KP_CS_PORT &= ~KP_CS_MASK; \
 	} while(0)

-#define KP_ROWS	7
-#define KP_COLS	4
+#define KP_ROWS 7
+#define KP_COLS 4

 #define KP_ROWS_MASK	((1 << KP_ROWS) - 1)
 #define KP_COLS_MASK	((1 << KP_COLS) - 1)
@@ -124,29 +124,29 @@
 #define SCAN		0
 #define SCAN_FILTER	1
 #define SCAN_COL	2
-#define SCAN_COL_FILTER	3
+#define SCAN_COL_FILTER 3
 #define PRESSED		4

-#define KP_F1	0	/* leftmost dot (tab) */
-#define KP_F2	1	/* middle left dot    */
-#define KP_F3	2	/* up                 */
-#define KP_F4	3	/* middle right dot   */
-#define KP_F5	4	/* rightmost dot      */
-#define KP_F6	5	/* C                  */
-#define KP_F7	6	/* left               */
-#define KP_F8	7	/* down               */
-#define KP_F9	8	/* right              */
-#define KP_F10	9	/* enter              */
-#define KP_F11	10	/* R                  */
-#define KP_F12	11	/* save               */
-#define KP_F13	12	/* redial             */
-#define KP_F14	13	/* speaker            */
-#define KP_F15  14	/* unused             */
-#define KP_F16  15	/* unused             */
+#define KP_F1	0	/* leftmost dot (tab)	*/
+#define KP_F2	1	/* middle left dot	*/
+#define KP_F3	2	/* up			*/
+#define KP_F4	3	/* middle right dot	*/
+#define KP_F5	4	/* rightmost dot	*/
+#define KP_F6	5	/* C			*/
+#define KP_F7	6	/* left			*/
+#define KP_F8	7	/* down			*/
+#define KP_F9	8	/* right		*/
+#define KP_F10	9	/* enter		*/
+#define KP_F11	10	/* R			*/
+#define KP_F12	11	/* save			*/
+#define KP_F13	12	/* redial		*/
+#define KP_F14	13	/* speaker		*/
+#define KP_F15	14	/* unused		*/
+#define KP_F16	15	/* unused		*/

-#define KP_RELEASE		-1	/* key depressed                          */
-#define KP_FORCE		-2	/* key was pressed for more than force hz */
-#define KP_IDLE			-3	/* key was released and idle              */
+#define KP_RELEASE		-1	/* key depressed				*/
+#define KP_FORCE		-2	/* key was pressed for more than force hz	*/
+#define KP_IDLE			-3	/* key was released and idle			*/

 #define KP_1	'1'
 #define KP_2	'2'
@@ -158,8 +158,8 @@
 #define KP_8	'8'
 #define KP_9	'9'
 #define KP_0	'0'
-#define KP_STAR	'*'
-#define KP_HASH	'#'
+#define KP_STAR '*'
+#define KP_HASH '#'

 /*************************************************************************************************/

@@ -198,7 +198,7 @@ static const char *whspace = " 0\n";
 /* per mode character select (for 2-9) */
 static const char *digits_sel[2][8] = {
 	{	/* small */
-		"abc2", 				/* 2 */
+		"abc2",					/* 2 */
 		"def3",					/* 3 */
 		"ghi4",					/* 4 */
 		"jkl5",					/* 5 */
@@ -206,8 +206,8 @@ static const char *digits_sel[2][8] = {
 		"pqrs7",				/* 7 */
 		"tuv8",					/* 8 */
 		"wxyz9",				/* 9 */
-	}, { 	/* capital */
-		"ABC2", 				/* 2 */
+	}, {	/* capital */
+		"ABC2",					/* 2 */
 		"DEF3",					/* 3 */
 		"GHI4",					/* 4 */
 		"JKL5",					/* 5 */
@@ -326,13 +326,6 @@ int phone_getc(void)
 int drv_phone_init(void)
 {
 	device_t console_dev;
-	char *penv;
-
-	/*
-	 * Force console i/o to serial ?
-	 */
-	if ((penv = getenv("console")) != NULL && strcmp(penv, "serial") == 0)
-		return 0;

 	console_init();

@@ -810,10 +803,10 @@ static void ensure_visible(int col, int row, int dx, int dy)


 	/* move to easier to use vars */
-	x1 = disp_col;   y1 = disp_row;
+	x1 = disp_col;	 y1 = disp_row;
 	x2 = x1 + width; y2 = y1 + height;
-	a1 = col;        b1 = row;
-	a2 = a1 + dx;    b2 = b1 + dy;
+	a1 = col;	 b1 = row;
+	a2 = a1 + dx;	 b2 = b1 + dy;

 	/* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */

@@ -891,7 +884,7 @@ void phone_putc(const char c)
 	blink_time = BLINK_HZ;

 	switch (c) {
-		case '\a':		/* ignore bell            */
+		case '\a':		/* ignore bell		  */
 		case '\r':		/* ignore carriage return */
 			break;

@@ -900,7 +893,7 @@ void phone_putc(const char c)
 			ensure_visible(curs_col, curs_row, 1, 1);
 			break;

-		case 9:	/* tab 8 */
+		case 9: /* tab 8 */
 			/* move to tab */
 			i = curs_col;
 			i |=  0x0008;
@@ -1006,13 +999,13 @@ unsigned int kp_get_col_mask(unsigned int row_mask)
 /**************************************************************************************/

 static const int kp_scancodes[KP_ROWS * KP_COLS] = {
-	KP_F1,   KP_F3,   KP_F4,  KP_F2,
-	KP_F6,   KP_F8,   KP_F9,  KP_F7,
-	KP_1,    KP_3,    KP_F11, KP_2,
-	KP_4,    KP_6,    KP_F12, KP_5,
-	KP_7,    KP_9,    KP_F13, KP_8,
+	KP_F1,	 KP_F3,	  KP_F4,  KP_F2,
+	KP_F6,	 KP_F8,	  KP_F9,  KP_F7,
+	KP_1,	 KP_3,	  KP_F11, KP_2,
+	KP_4,	 KP_6,	  KP_F12, KP_5,
+	KP_7,	 KP_9,	  KP_F13, KP_8,
 	KP_STAR, KP_HASH, KP_F14, KP_0,
-	KP_F5,   KP_F15,  KP_F16, KP_F10,
+	KP_F5,	 KP_F15,  KP_F16, KP_F10,
 };

 static const int kp_repeats[KP_ROWS * KP_COLS] = {
--- a/board/netta/Makefile
+++ b/board/netta/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk

 LIB	= lib$(BOARD).a

-OBJS	= $(BOARD).o flash.o dsp.o
+OBJS	= $(BOARD).o flash.o dsp.o codec.o

 $(LIB):	.depend $(OBJS)
 	$(AR) crv $@ $(OBJS)
--- a/board/netta/codec.c
+++ b/board/netta/codec.c
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
wdenk	7ca202f566	Add support for IDS "NC650" board	2004-08-28 22:45:57 +00:00
wdenk	31a649234e	* Add automatic update support for LWMON board * Enable MSDOS/VFAT filesystem support for LWMON board * Clear Block Lock-Bits when erasing flash on LWMON board. * Fix return code of "fatload" command * Disable debugging for TQM5200 board	2004-08-28 21:09:14 +00:00
wdenk	89394047ba	* Patch by Martin Krause, 03 Aug 2004: change timing for SM501 graphics controller on TQM5200 module * Patch by Mark Jonas, 13 July 2004: - Total5200 LCD now run in little endian mode. Endianess conversion is done in hardware. - Removed last reference to "console" environment variable.	2004-08-04 21:56:49 +00:00
wdenk	429168ea88	Patches by Lars Munch, 12 Jul 2004: - move at45.c to board/at91rm9200dk/ since this is at91rm9200dk board specific - split out the LXT971A PHY from ns_9750_eth.h - split the dm9161 phy part out of at91rm9200_ether.c	2004-08-02 23:39:03 +00:00
wdenk	6705d81e90	* Patch by Andreas Engel, 12 Jul 2004: Replaced hardcoded PL011 clock frequency with config variable. Fixed wrong CONFIG_CMD_DFL doc. * Patch by Thomas Viehweger, 09 Jun 2004: make it possible to remove chpart when there is only one partition	2004-08-02 23:22:59 +00:00
wdenk	68ceb29e71	Add support for console over UDP (compatible to Ingo Molnar's netconsole patch under Linux)	2004-08-02 21:11:11 +00:00
wdenk	9aea95307f	Patch by Jon Loeliger, 16 Jul 2004: - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads	2004-08-01 23:02:45 +00:00
wdenk	281e00a3be	* Code cleanup * Patch by Sascha Hauer, 28 Jun: - add generic support for Motorola i.MX architecture - add support for mx1ads, mx1fs2 and scb9328 boards * Patches by Marc Leeman, 23 Jul 2004: - Add define for the PCI/Memory Buffer Configuration Register - corrected comments in cpu/mpc824x/cpu_init.c * Add support for multiple serial interfaces (for example to allow modem dial-in / dial-out)	2004-08-01 22:48:16 +00:00
wdenk	cfca5e604d	* Fix NSCU config; add ethernet wakeup code. * Add link for preloader for Motorola Coldfire to RAEDME.m68k	2004-08-01 13:09:47 +00:00
stroese	45eeb8983c	Patch by Stefan Roese, 15 Jul 2004	2004-07-15 14:41:43 +00:00
stroese	de8d5a3600	cpu/ppc4xx/sdram.c rewritten now using get_ram_size()	2004-07-15 14:41:13 +00:00
wdenk	75b1fa7864	Patch by Michael Bendzick, 12 Jul 2004: fix output formatting in drivers/cfi_flash.c	2004-07-12 22:34:51 +00:00
wdenk	07cba3514b	Patch by Mark Jonas, 02 Jul 2004: Fix lowboot (again) on MPC5xxx	2004-07-12 14:37:59 +00:00
wdenk	b8c8318160	Add cerf250 to MAINTAINERS and README	2004-07-11 22:37:59 +00:00
wdenk	cdc7fea173	Patch by Curt Brune, 07 Jul 2004: relocate exception vectors on arm720t if needed	2004-07-11 22:27:55 +00:00
wdenk	a1f4a3dd05	* Patch by George G. Davis, 06 Jul 2004: - update mach-types.h to latest arm.linux.org.uk master list - Set correct OMAP1610 bi_arch_number for build target * Patch by Curt Brune, 06 Jul 2004: evb4510: add support for timer interrupt; cleanup	2004-07-11 22:19:26 +00:00
wdenk	b9283e2dbe	* Patch by Dan Poirot, 06 Jul 2004: Fix sbc8260 environment variables * Cleanup redundand "console" environment variable	2004-07-11 21:49:42 +00:00
wdenk	810509266f	* Cleanup * Patch by Mark Jonas, 05 Jul 2004: add support for the Total5100's and Total5200's LCD screen * Patches by Dan Eisenhut, 01 Jul 2004: - README fixes. - Move doc2000.h include to prevent compiler warning on some boards	2004-07-11 20:04:51 +00:00
wdenk	6c7a14084a	Patch by Mark Jonas, 01 Jul 2004: Added support for Total5100 and Total5200 (Rev.1 and Rev.2) MGT5100 and MPC5200 based Freescale platforms.	2004-07-11 19:17:20 +00:00
wdenk	bc54f309a1	* Patch by Philippe Robin, 01 Jul 2004: Add initialization for Integrator and versatile board files. * Patch by Hinko Kocevar, 01 Jun 2004: Fix VFD FB allocation, add LCD FB allocation on ARM	2004-07-11 18:10:30 +00:00
wdenk	56523f1283	* Patch by Martin Krause, 30 Jun 2004: Add support for TQM5200 board * Patch by Martin Krause, 29 Jun 2004: Add loopw command: infinite write loop on address range	2004-07-11 17:40:54 +00:00
wdenk	857cad37a4	Patches by Yasushi Shoji, 29 Jun 2004: - add empty include/asm-microblaze/processor.h - add to CREDITS and MAINTAINERS - add gd initialization - add MicroBlaze and SUZAKU board to MAKEALL script - add reset support for SUZAKU - add flush_cache() for MicroBlaze - add CFG_FLASH_SIZE to include/configs/suzaku.h since we have fixed size flash memory on SUZAKU	2004-07-10 23:48:41 +00:00
wdenk	fabd46acff	* Patch by Prakash Kumar, 27 Jun 2004: Add support for the PXA250 based Intrinsyc Cerf board. * Patch by Yasushi Shoji, 27 Jun 2004: fix comment in include/common.h	2004-07-10 23:11:10 +00:00
wdenk	10a36a98c4	Fix swapped config files.	2004-07-10 23:02:23 +00:00
wdenk	466b74108f	* Rename SBC8560 into sbc8560 for consistency * Patch by Daniel Poirot, 24 Jun 2004: Add support for Wind River's sbc8240 board * Patches by Yasushi Shoji, 26 Jun 2004: - drivers/serial_xuartlite.c: fix "return 0" in void function - add microblaze support to mkimage tool	2004-07-10 22:35:59 +00:00
wdenk	8b07a1103d	* Patch by Fred Klatt, 25 Jun 2004: Add support for WindRiver's SBC8560 board * Patch by Nicolas Lacressonniere, 24 Jun 2004 Small Bugs fixes for "at91rm9200dk" board: - Timing modifications for SPI DataFlash access - Fix NAND flash detection bug * Patch by Nicolas Lacressonniere, 24 Jun 2004: Add Support for Flash AT49BV6416 for AT91RM9200DK board	2004-07-10 21:45:47 +00:00
wdenk	0ac6f8b749	Patch by Jon Loeliger, 17 June 2004: Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads	2004-07-09 23:27:13 +00:00
wdenk	262381329b	* Patch by Yuli Barcohen, 16 Jun 2004: Remove obsolete AdderII port which was superseded by unified AdderII/Adder87x port * Patch by Ladislav Michl, 16 Jun 2004: Fix gcc-3.3.3 warnings for smc91111.c	2004-07-09 22:51:01 +00:00
stroese	ede130229c	Patch by Stefan Roese, 02 Jul 2004	2004-07-02 14:38:26 +00:00
stroese	2c96baa2a4	Fix problem in 405 i2c driver; don't try to print without console!	2004-07-02 14:37:04 +00:00
stroese	18f71f27ae	Fix bug in 405 ethernet driver; allocated data not cleared!	2004-07-02 14:36:35 +00:00
wdenk	78953f2f93	Patch by Paul Ruhland, 11 Jun 2004: Remove debug code from 'board/lpd7a40x/flash.c'	2004-07-01 22:02:29 +00:00
wdenk	e55ca7e262	Patch by Andrea Marson, 11 Jun 2004: Update for PPChameleon board: - support for SysClk @ 25MHz - support for Silicon Motion SM712 VGA controller - some clean ups	2004-07-01 21:40:08 +00:00
wdenk	93f6a6771b	* Patches by Richard Woodruff, 10 Jun 2004: - fix problems with examples/stubs.c for GCC >= 3.4 - fix problems with gd initialization * Enable FAT filesystem support for HMI10 board	2004-07-01 20:28:03 +00:00
wdenk	39539887ea	* Code cleanup (ARM mostly) * Patch by Curt Brune, 17 May 2004: - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) - Add support for ESPD-Inc. EVB4510 Board	2004-07-01 16:30:44 +00:00
wdenk	e94d2cd9d1	* Fix "cls" command when used with splash screen * Increase NFS download timeout (now 1 min - 10 sec is to short for a slow download of a big image)	2004-06-30 22:59:18 +00:00
wdenk	c3f4d17e05	Add "cls" function to MPC823 LCD driver so we can reinitialize the display even after showing a bitmap	2004-06-25 23:35:58 +00:00
wdenk	021bfcd3c6	Add MicroSys maintainer.	2004-06-24 15:54:37 +00:00
wdenk	49822e23a0	Patch by Josef Wagner, 04 Jun 2004: - DDR Ram support for PM520 (MPC5200) - support for different flash types (PM520) - USB / IDE / CF-Card / DiskOnChip support for PM520 - 8 bit boot rom support for PM520/CE520 - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) - I2C and RTC support for CPC45 - support of new flash type (28F160C3T) for CPC45	2004-06-19 21:19:10 +00:00
wdenk	46a414dc12	* Fix flash parameters passed to Linux for PPChameleon board * Remove eth_init() from lib_arm/board.c; it's done in net.net.c.	2004-06-17 18:50:45 +00:00
wdenk	f832d8a143	* Patch by Paul Ruhland, 10 Jun 2004: fix support for Logic SDK-LH7A404 board and clean up the LH7A404 register macros. * Patch by Matthew McClintock, 10 Jun 2004: Modify code to select correct serial clock on Sandpoint8245	2004-06-10 21:55:33 +00:00
wdenk	b54d32b40d	* Patch by Robert Schwebel, 10 Jun 2004: Add support for Intel K3 strata flash. * Some cleanup * Patch by Thomas Brand, 10 Jun 2004: Fix "loads" command on DK1S10 board	2004-06-10 21:34:36 +00:00
wdenk	681334540d	Remove duplicate entry	2004-06-09 22:52:57 +00:00
wdenk	99edcfb29e	Patch by Yuli Barcohen, 09 Jun 2004: Add support for 8MB flash SIMM and JFFS2 file system on Motorola FADS board and its derivatives (MPC86xADS, MPC885ADS).	2004-06-09 21:54:22 +00:00
wdenk	2d24a3a787	* Patch by Yuli Barcohen, 09 Jun 2004: Add support for Analogue&Micro Adder87x and the older AdderII board. * Patch by Ming-Len Wu, 09 Jun 2004: Add suppport for MC9328 (Dargonball) CPU and Motorola MX1ADS board	2004-06-09 21:50:45 +00:00
wdenk	e63c8ee3dc	Patch by Sam Song, 09 Jun 2004: - Add support for RPXlite_DW board - Update FLASH driver for 4*AM29DL323DB90VI - Add option configuration of CFG_ENV_IS_IN_NVRAM on RPXlite_DW board	2004-06-09 21:04:48 +00:00
wdenk	36c728774e	* Patch by Mark Jonas, 08 June 2004: - Make MPC5200 boards evaluate the SVR to print processor name and version in checkcpu() (cpu/mpc5xxx/cpu.c). * Patch by Kai-Uwe Bloem, 06 May 2004: Fix endianess problem in cramfs code	2004-06-09 17:45:32 +00:00
wdenk	4c0d4c3b78	* Patch by Tom Armistead, 04 Jun 2004: Add support for MAX6900 RTC * Patches by Ladislav Michl, 03 Jun 2004: - fix cfi_flash.c on LE systems - let 'make mrproper' delete u-boot.img as well - turn printf into debug in cfi_flash.c	2004-06-09 17:34:58 +00:00
wdenk	ca0e774894	Patch by Kurt Stremerch, 28 May 2004: Add support for Exys XSEngine board Some code cleanup.	2004-06-09 15:37:23 +00:00
wdenk	697037fe9b	* Patch by Martin Krause, 27 May 2004: Fix a MPC5xxx I2C timing issue in i2c_probe(). * Patch by Leif Lindholm, 27 May 2004: Fix board_init_f() for dbau1x00 board.	2004-06-09 15:29:49 +00:00
wdenk	3ff02c27d5	* Patch by Imre Deak, 26 May 2004: On OMAP1610 platforms check if booting from RAM(CS0) or flash(CS3). Set flash base accordingly, and decide whether to do or skip board specific setup steps. * Patch by Josef Baumgartner, 26 May 2004: Add missing define in include/asm-m68k/global_data.h	2004-06-09 15:25:53 +00:00
wdenk	70f05ac34e	* Patch by Josef Baumgartner, 25 May 2004: Add missing functions get_ticks() and get_tbclk() in lib_m68k/time.c * Patch by Paul Ruhland, 24 May 2004: fix SDRAM initialization for LPD7A400 board.	2004-06-09 15:24:18 +00:00
wdenk	13a5695b7c	Patch by Jian Zhang, 20 May 2004: add support for environment in NAND flash	2004-06-09 14:58:14 +00:00
wdenk	c3c7f861ae	Patch by Yuli Barcohen, 20 May 2004: Add support for Interphase iSPAN boards.	2004-06-09 14:47:54 +00:00
wdenk	f39748ae8e	* Patch by Paul Ruhland, 17 May 2004: - Add support for the Logic Zoom LH7A40x based SDK board(s), specifically the LPD7A400. * Patches by Robert Schwebel, 15 May 2004: - call MAC address reading code also for SMSC91C111; - make SMSC91C111 timeout configurable, remove duplicate code - fix get_timer() for PXA - update doc/README.JFFS2 - use "bootfile" env variable also for jffs2	2004-06-09 13:37:52 +00:00
wdenk	aa24509041	Patch by Tolunay Orkun, 14 May 2004: Add support for Cogent CSB472 board (8MB Flash Rev)	2004-06-09 12:47:02 +00:00
wdenk	aa5590b66f	Patch by Thomas Viehweger, 14 May 2004: - flash.h: more flash types added - immap_8260.h: some bits added (useful for RMII) - cmd_coninfo.c: typo corrected, printf -> puts - reduced size by replacing spaces with tab	2004-06-09 12:42:26 +00:00
wdenk	48abe7bfab	Patch by Robert Schwebel, 13 May 2004: Add 'imgextract' command: extract one part of a multi file image.	2004-06-09 10:15:00 +00:00
wdenk	547b4cb25e	Patches by Jon Loeliger, 11 May 2004: (partially, as they contained a lot of crap)	2004-06-09 00:51:50 +00:00
wdenk	97d80fc391	Patches Part 1 by Jon Loeliger, 11 May 2004: Dynamically handle REV1 and REV2 MPC85xx parts. (Jon Loeliger, 10-May-2004). New consistent memory map and Local Access Window across MPC85xx line. New CCSRBAR at 0xE000_0000 now. Add RAPID I/O memory map. New memory map in README.MPC85xxads (Kumar Gala, 10-May-2004) Better board and CPU identification on MPC85xx boards at boot. (Jon Loeliger, 10-May-2004) SDRAM clock control fixes on MPC8540ADS & MPC8560 boards. Some configuration options for MPC8540ADS & MPC8560ADS cleaned up. (Jim Robertson, 10-May-2004) Rewrite of the MPC85xx Three Speed Ethernet Controller (TSEC) driver. Supports multiple PHYs. (Andy Fleming, 10-May-2004) Some README.MPC85xxads updates. (Kumar Gala, 10-May-2004) Copyright updates for "Freescale" (Andy Fleming, 10-May-2004)	2004-06-09 00:34:46 +00:00
wdenk	6bdd1377af	Patch by Stephen Williams, 11 May 2004: Add flash support for ST M29W040B Reduce JSE specific flash.c to remove dead code.	2004-06-09 00:15:33 +00:00
wdenk	356a0d9f31	Patch by Markus Pietrek, 04 May 2004: Fix clear_bss code for ARM systems (all except s3c44b0 which doesn't clear BSS at all?)	2004-06-09 00:10:59 +00:00
wdenk	1eaeb58e3c	* Patch by Rishi Bhattacharya, 08 May 2004: Add support for TI OMAP5912 OSK Board * Patch by Sam Song May, 07 May 2004: Fix typo of UPM table for rmu board	2004-06-08 00:22:43 +00:00
wdenk	79fa88f3ed	Patch by Pantelis Antoniou, 5 May 2004: - Intracom board update. - Add Codec POST.	2004-06-07 23:46:25 +00:00
wdenk	cea655a224	Add support for the second Ethernet interface for the 'PPChameleon' board.	2004-06-06 23:53:59 +00:00
wdenk	a56bd92289	* Patch by Dave Peverley, 30 Apr 2004: Add support for OMAP730 Perseus2 Development board * Patch by Alan J. Luse, 29 Apr 2004: Fix flash chip-select (OR0) option register setting on FADS boards. * Patch by Alan J. Luse, 29 Apr 2004: Report MII network speed and duplex setting properly when auto-negotiate is not enabled. * Patch by Jarrett Redd, 29 Apr 2004: Fix hang on reset on Ocotea board due to flash in wrong mode.	2004-06-06 23:13:55 +00:00
wdenk	5ca2679933	Patch by Dave Peverley, 29 Apr 2004: add MAC address detection to smc91111 driver	2004-06-06 22:11:41 +00:00
wdenk	17ea117743	Patch by Tolunay Orkun, 20 Apr 2004: - README update: add CONFIG_CSB272 and csb272_config - add descriptions for some MII/PHY options, CONFIG_I2CFAST, and i2cfast environment variable	2004-06-06 21:51:03 +00:00
wdenk	1114257c9d	Patch by Yuli Barcohen, 19 Apr 2004: - Rename DUET_ADS to MPC885ADS - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY - Clean up FADS family port to use the new defines	2004-06-06 21:35:06 +00:00
wdenk	d7a04603ae	Fix text alignment	2004-06-01 21:15:28 +00:00
wdenk	979bdbc70e	Fix PCI support on CPC45 board	2004-06-01 21:08:17 +00:00