Merge tag 'efi-2026-07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2026-07-rc5 CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/30365 Documentation: * Update urllib3 version for building * usb: typos 'requird', 'current' UEFI * Improve PE-COFF relocation data validation Devicetree-to-C generator: * dtoc: test: add missing escape in help text
Merge patch series "ti: j7: Update to v0.12.0 of DDR config tool"
2026-06-09 21:26:42 +03:00 · 2026-06-09 10:27:02 -06:00 · 2026-06-09 10:26:36 -06:00 · 2026-06-09 10:26:21 -06:00 · 2026-06-09 10:26:21 -06:00 · 2026-06-09 10:26:21 -06:00
14 changed files with 14486 additions and 5498 deletions
--- a/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-am68-ddr-sk-lp4-4266.dtsi
--- a/arch/arm/dts/k3-am68-sk-r5-base-board.dts
+++ b/arch/arm/dts/k3-am68-sk-r5-base-board.dts
@@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-am68-sk-base-board.dts"
-#include "k3-j721s2-ddr-evm-lp4-4266.dtsi"
+#include "k3-am68-ddr-sk-lp4-4266.dtsi"
 #include "k3-j721s2-ddr.dtsi"
 #include "k3-am68-sk-base-board-u-boot.dtsi"
 #include "k3-j721s2-r5.dtsi"
--- a/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-am69-ddr-sk-lp4-4266.dtsi
--- a/arch/arm/dts/k3-am69-r5-sk.dts
+++ b/arch/arm/dts/k3-am69-r5-sk.dts
@@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-am69-sk.dts"
-#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-am69-ddr-sk-lp4-4266.dtsi"
 #include "k3-j784s4-ddr.dtsi"
 #include "k3-am69-sk-u-boot.dtsi"
 #include "k3-j784s4-r5.dtsi"
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-3200.dtsi
@@ -1,14 +1,22 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
- * This file was generated on 06/01/2021
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the following tool revisions:
+ *     - SysConfig: Revision 1.25.0+4268
+ *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
+ * This file was generated on Thu Oct 30 2025 13:11:41 GMT+0530 (India Standard Time)
 */

-#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_0 27500000
-#define DDRSS_PLL_FREQUENCY_1 666500000
-#define DDRSS_PLL_FREQUENCY_2 666500000
+#define DDRSS_PLL_FREQUENCY_1 800000000
+#define DDRSS_PLL_FREQUENCY_2 800000000
+
+#define DDR_REG0_SIZE_MSB 0x00000000
+#define DDR_REG0_SIZE_LSB 0x80000000
+#define DDR_REG1_SIZE_MSB 0x00000000
+#define DDR_REG1_SIZE_LSB 0x80000000
+

 #define DDRSS_CTL_00_DATA 0x00000B00
 #define DDRSS_CTL_01_DATA 0x00000000
@@ -21,16 +29,16 @@
 #define DDRSS_CTL_08_DATA 0x0001ADAF
 #define DDRSS_CTL_09_DATA 0x00000005
 #define DDRSS_CTL_10_DATA 0x0000006E
-#define DDRSS_CTL_11_DATA 0x000411AB
-#define DDRSS_CTL_12_DATA 0x0028B0AB
+#define DDRSS_CTL_11_DATA 0x0004E200
+#define DDRSS_CTL_12_DATA 0x0030D400
 #define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000A6B
-#define DDRSS_CTL_15_DATA 0x000411AB
-#define DDRSS_CTL_16_DATA 0x0028B0AB
+#define DDRSS_CTL_14_DATA 0x00000C80
+#define DDRSS_CTL_15_DATA 0x0004E200
+#define DDRSS_CTL_16_DATA 0x0030D400
 #define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000A6B
+#define DDRSS_CTL_18_DATA 0x00000C80
 #define DDRSS_CTL_19_DATA 0x01010000
-#define DDRSS_CTL_20_DATA 0x02011001
+#define DDRSS_CTL_20_DATA 0x01011001
 #define DDRSS_CTL_21_DATA 0x02010000
 #define DDRSS_CTL_22_DATA 0x00020100
 #define DDRSS_CTL_23_DATA 0x0000000B
@@ -38,66 +46,66 @@
 #define DDRSS_CTL_25_DATA 0x00000000
 #define DDRSS_CTL_26_DATA 0x00000000
 #define DDRSS_CTL_27_DATA 0x03020200
-#define DDRSS_CTL_28_DATA 0x00003636
+#define DDRSS_CTL_28_DATA 0x00004040
 #define DDRSS_CTL_29_DATA 0x00100000
 #define DDRSS_CTL_30_DATA 0x00000000
 #define DDRSS_CTL_31_DATA 0x00000000
 #define DDRSS_CTL_32_DATA 0x00000000
 #define DDRSS_CTL_33_DATA 0x00000000
 #define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x0C300C30
+#define DDRSS_CTL_35_DATA 0x0E400E40
 #define DDRSS_CTL_36_DATA 0x00050804
 #define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x0D000204
-#define DDRSS_CTL_39_DATA 0x113C0057
-#define DDRSS_CTL_40_DATA 0x0D00291B
-#define DDRSS_CTL_41_DATA 0x113C0057
-#define DDRSS_CTL_42_DATA 0x2000291B
+#define DDRSS_CTL_38_DATA 0x14000304
+#define DDRSS_CTL_39_DATA 0x15480068
+#define DDRSS_CTL_40_DATA 0x14004220
+#define DDRSS_CTL_41_DATA 0x15480068
+#define DDRSS_CTL_42_DATA 0x20004220
 #define DDRSS_CTL_43_DATA 0x000A0A09
-#define DDRSS_CTL_44_DATA 0x0400078A
-#define DDRSS_CTL_45_DATA 0x130E0B04
-#define DDRSS_CTL_46_DATA 0x0A00B6D0
-#define DDRSS_CTL_47_DATA 0x130E0B0A
-#define DDRSS_CTL_48_DATA 0x0A00B6D0
-#define DDRSS_CTL_49_DATA 0x0203040A
-#define DDRSS_CTL_50_DATA 0x1C040500
-#define DDRSS_CTL_51_DATA 0x081D1C1D
+#define DDRSS_CTL_44_DATA 0x040003C5
+#define DDRSS_CTL_45_DATA 0x17100D04
+#define DDRSS_CTL_46_DATA 0x0C006DB0
+#define DDRSS_CTL_47_DATA 0x17100D0C
+#define DDRSS_CTL_48_DATA 0x0C006DB0
+#define DDRSS_CTL_49_DATA 0x0203040C
+#define DDRSS_CTL_50_DATA 0x21060500
+#define DDRSS_CTL_51_DATA 0x08222122
 #define DDRSS_CTL_52_DATA 0x14000E0A
-#define DDRSS_CTL_53_DATA 0x02010A0A
-#define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x04383808
-#define DDRSS_CTL_56_DATA 0x041F1F04
-#define DDRSS_CTL_57_DATA 0x00001F1F
+#define DDRSS_CTL_53_DATA 0x03010A0A
+#define DDRSS_CTL_54_DATA 0x01010003
+#define DDRSS_CTL_55_DATA 0x0442420A
+#define DDRSS_CTL_56_DATA 0x04252504
+#define DDRSS_CTL_57_DATA 0x00002525
 #define DDRSS_CTL_58_DATA 0x00010100
 #define DDRSS_CTL_59_DATA 0x03010000
 #define DDRSS_CTL_60_DATA 0x00001008
-#define DDRSS_CTL_61_DATA 0x000000CE
-#define DDRSS_CTL_62_DATA 0x00000176
-#define DDRSS_CTL_63_DATA 0x00001448
-#define DDRSS_CTL_64_DATA 0x00000176
-#define DDRSS_CTL_65_DATA 0x00001448
+#define DDRSS_CTL_61_DATA 0x00000068
+#define DDRSS_CTL_62_DATA 0x000001C0
+#define DDRSS_CTL_63_DATA 0x00000C28
+#define DDRSS_CTL_64_DATA 0x000001C0
+#define DDRSS_CTL_65_DATA 0x00000C28
 #define DDRSS_CTL_66_DATA 0x00000005
 #define DDRSS_CTL_67_DATA 0x00040000
-#define DDRSS_CTL_68_DATA 0x005D0012
-#define DDRSS_CTL_69_DATA 0x005D0282
-#define DDRSS_CTL_70_DATA 0x00400282
+#define DDRSS_CTL_68_DATA 0x00700005
+#define DDRSS_CTL_69_DATA 0x0070017E
+#define DDRSS_CTL_70_DATA 0x0040017E
 #define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x000A0005
-#define DDRSS_CTL_73_DATA 0x1F08000A
-#define DDRSS_CTL_74_DATA 0x0505011F
+#define DDRSS_CTL_72_DATA 0x000C0005
+#define DDRSS_CTL_73_DATA 0x2408000C
+#define DDRSS_CTL_74_DATA 0x05050124
 #define DDRSS_CTL_75_DATA 0x0301030A
-#define DDRSS_CTL_76_DATA 0x03130A07
-#define DDRSS_CTL_77_DATA 0x0A070301
-#define DDRSS_CTL_78_DATA 0x00010313
+#define DDRSS_CTL_76_DATA 0x03170C08
+#define DDRSS_CTL_77_DATA 0x0C080301
+#define DDRSS_CTL_78_DATA 0x00010317
 #define DDRSS_CTL_79_DATA 0x00100010
-#define DDRSS_CTL_80_DATA 0x01800180
-#define DDRSS_CTL_81_DATA 0x01800180
+#define DDRSS_CTL_80_DATA 0x01CC01CC
+#define DDRSS_CTL_81_DATA 0x01CC01CC
 #define DDRSS_CTL_82_DATA 0x03050505
 #define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x14070A07
-#define DDRSS_CTL_85_DATA 0x03030A03
-#define DDRSS_CTL_86_DATA 0x14070A07
-#define DDRSS_CTL_87_DATA 0x03030A03
+#define DDRSS_CTL_84_DATA 0x18080C08
+#define DDRSS_CTL_85_DATA 0x03030C03
+#define DDRSS_CTL_86_DATA 0x18080C08
+#define DDRSS_CTL_87_DATA 0x03030C03
 #define DDRSS_CTL_88_DATA 0x03010000
 #define DDRSS_CTL_89_DATA 0x00010000
 #define DDRSS_CTL_90_DATA 0x00000000
@@ -112,27 +120,27 @@
 #define DDRSS_CTL_99_DATA 0x00000000
 #define DDRSS_CTL_100_DATA 0x00040005
 #define DDRSS_CTL_101_DATA 0x00000000
-#define DDRSS_CTL_102_DATA 0x00003380
-#define DDRSS_CTL_103_DATA 0x00003380
-#define DDRSS_CTL_104_DATA 0x00003380
-#define DDRSS_CTL_105_DATA 0x00003380
-#define DDRSS_CTL_106_DATA 0x00003380
+#define DDRSS_CTL_102_DATA 0x000018C0
+#define DDRSS_CTL_103_DATA 0x000018C0
+#define DDRSS_CTL_104_DATA 0x000018C0
+#define DDRSS_CTL_105_DATA 0x000018C0
+#define DDRSS_CTL_106_DATA 0x000018C0
 #define DDRSS_CTL_107_DATA 0x00000000
-#define DDRSS_CTL_108_DATA 0x000005A2
-#define DDRSS_CTL_109_DATA 0x00051200
-#define DDRSS_CTL_110_DATA 0x00051200
-#define DDRSS_CTL_111_DATA 0x00051200
-#define DDRSS_CTL_112_DATA 0x00051200
-#define DDRSS_CTL_113_DATA 0x00051200
+#define DDRSS_CTL_108_DATA 0x000002B5
+#define DDRSS_CTL_109_DATA 0x00030A00
+#define DDRSS_CTL_110_DATA 0x00030A00
+#define DDRSS_CTL_111_DATA 0x00030A00
+#define DDRSS_CTL_112_DATA 0x00030A00
+#define DDRSS_CTL_113_DATA 0x00030A00
 #define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00008DF8
-#define DDRSS_CTL_116_DATA 0x00051200
-#define DDRSS_CTL_117_DATA 0x00051200
-#define DDRSS_CTL_118_DATA 0x00051200
-#define DDRSS_CTL_119_DATA 0x00051200
-#define DDRSS_CTL_120_DATA 0x00051200
+#define DDRSS_CTL_115_DATA 0x00005518
+#define DDRSS_CTL_116_DATA 0x00030A00
+#define DDRSS_CTL_117_DATA 0x00030A00
+#define DDRSS_CTL_118_DATA 0x00030A00
+#define DDRSS_CTL_119_DATA 0x00030A00
+#define DDRSS_CTL_120_DATA 0x00030A00
 #define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00008DF8
+#define DDRSS_CTL_122_DATA 0x00005518
 #define DDRSS_CTL_123_DATA 0x00000000
 #define DDRSS_CTL_124_DATA 0x00000000
 #define DDRSS_CTL_125_DATA 0x00000000
@@ -141,8 +149,8 @@
 #define DDRSS_CTL_128_DATA 0x00000000
 #define DDRSS_CTL_129_DATA 0x00000000
 #define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x07030500
-#define DDRSS_CTL_132_DATA 0x00030703
+#define DDRSS_CTL_131_DATA 0x08030500
+#define DDRSS_CTL_132_DATA 0x00030803
 #define DDRSS_CTL_133_DATA 0x0A090000
 #define DDRSS_CTL_134_DATA 0x0A090701
 #define DDRSS_CTL_135_DATA 0x0900000E
@@ -177,31 +185,31 @@
 #define DDRSS_CTL_164_DATA 0x000B0000
 #define DDRSS_CTL_165_DATA 0x000E0006
 #define DDRSS_CTL_166_DATA 0x000E0404
-#define DDRSS_CTL_167_DATA 0x0086010B
-#define DDRSS_CTL_168_DATA 0x0A0A014E
-#define DDRSS_CTL_169_DATA 0x010B014E
-#define DDRSS_CTL_170_DATA 0x014E0086
-#define DDRSS_CTL_171_DATA 0x014E0A0A
+#define DDRSS_CTL_167_DATA 0x00A00140
+#define DDRSS_CTL_168_DATA 0x0C0C0190
+#define DDRSS_CTL_169_DATA 0x01400190
+#define DDRSS_CTL_170_DATA 0x019000A0
+#define DDRSS_CTL_171_DATA 0x01900C0C
 #define DDRSS_CTL_172_DATA 0x00000000
 #define DDRSS_CTL_173_DATA 0x00000000
 #define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x24C40084
-#define DDRSS_CTL_176_DATA 0x2B0024C4
-#define DDRSS_CTL_177_DATA 0x00002B2B
+#define DDRSS_CTL_175_DATA 0x2DD40084
+#define DDRSS_CTL_176_DATA 0xEB002DD4
+#define DDRSS_CTL_177_DATA 0x0000EBEB
 #define DDRSS_CTL_178_DATA 0x36000000
 #define DDRSS_CTL_179_DATA 0x27270036
 #define DDRSS_CTL_180_DATA 0x0F0F0000
 #define DDRSS_CTL_181_DATA 0x15000000
 #define DDRSS_CTL_182_DATA 0x00841515
-#define DDRSS_CTL_183_DATA 0x24C424C4
-#define DDRSS_CTL_184_DATA 0x2B2B2B00
+#define DDRSS_CTL_183_DATA 0x2DD42DD4
+#define DDRSS_CTL_184_DATA 0xEBEBEB00
 #define DDRSS_CTL_185_DATA 0x00000000
 #define DDRSS_CTL_186_DATA 0x00363600
 #define DDRSS_CTL_187_DATA 0x00002727
 #define DDRSS_CTL_188_DATA 0x00000F0F
 #define DDRSS_CTL_189_DATA 0x15151500
 #define DDRSS_CTL_190_DATA 0x00000020
-#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x01000000
 #define DDRSS_CTL_192_DATA 0x00000001
 #define DDRSS_CTL_193_DATA 0x00000000
 #define DDRSS_CTL_194_DATA 0x01000000
@@ -239,17 +247,17 @@
 #define DDRSS_CTL_226_DATA 0x00000000
 #define DDRSS_CTL_227_DATA 0x15110000
 #define DDRSS_CTL_228_DATA 0x00040C18
-#define DDRSS_CTL_229_DATA 0x00000000
-#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
 #define DDRSS_CTL_231_DATA 0x00000000
 #define DDRSS_CTL_232_DATA 0x00000000
-#define DDRSS_CTL_233_DATA 0x00000000
-#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
 #define DDRSS_CTL_235_DATA 0x00000000
 #define DDRSS_CTL_236_DATA 0x00000000
 #define DDRSS_CTL_237_DATA 0x00000000
-#define DDRSS_CTL_238_DATA 0x00000000
-#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
 #define DDRSS_CTL_240_DATA 0x00000000
 #define DDRSS_CTL_241_DATA 0x00000000
 #define DDRSS_CTL_242_DATA 0x00030000
@@ -271,13 +279,13 @@
 #define DDRSS_CTL_258_DATA 0x00370040
 #define DDRSS_CTL_259_DATA 0x00020008
 #define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00280536
+#define DDRSS_CTL_261_DATA 0x00300640
 #define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x05360040
-#define DDRSS_CTL_264_DATA 0x00000028
-#define DDRSS_CTL_265_DATA 0x00430003
-#define DDRSS_CTL_266_DATA 0x01000043
-#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x06400040
+#define DDRSS_CTL_264_DATA 0x00000030
+#define DDRSS_CTL_265_DATA 0x00500003
+#define DDRSS_CTL_266_DATA 0x01000050
+#define DDRSS_CTL_267_DATA 0x03030303
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
 #define DDRSS_CTL_270_DATA 0x00000FFF
@@ -301,14 +309,14 @@
 #define DDRSS_CTL_288_DATA 0x00000000
 #define DDRSS_CTL_289_DATA 0x00000000
 #define DDRSS_CTL_290_DATA 0x03030300
-#define DDRSS_CTL_291_DATA 0x00000001
+#define DDRSS_CTL_291_DATA 0x00010101
 #define DDRSS_CTL_292_DATA 0x00000000
 #define DDRSS_CTL_293_DATA 0x00000000
 #define DDRSS_CTL_294_DATA 0x00000000
 #define DDRSS_CTL_295_DATA 0x00000000
 #define DDRSS_CTL_296_DATA 0x00000000
-#define DDRSS_CTL_297_DATA 0x00000000
-#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS_CTL_298_DATA 0x00000FFF
 #define DDRSS_CTL_299_DATA 0x00000000
 #define DDRSS_CTL_300_DATA 0x00000000
 #define DDRSS_CTL_301_DATA 0x00000000
@@ -328,15 +336,15 @@
 #define DDRSS_CTL_315_DATA 0x01000101
 #define DDRSS_CTL_316_DATA 0x01010001
 #define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05070703
-#define DDRSS_CTL_319_DATA 0x0A081414
-#define DDRSS_CTL_320_DATA 0x0009030A
-#define DDRSS_CTL_321_DATA 0x080C030F
-#define DDRSS_CTL_322_DATA 0x080C0306
-#define DDRSS_CTL_323_DATA 0x0C090006
-#define DDRSS_CTL_324_DATA 0x0100000C
-#define DDRSS_CTL_325_DATA 0x05020501
-#define DDRSS_CTL_326_DATA 0x00000002
+#define DDRSS_CTL_318_DATA 0x05080803
+#define DDRSS_CTL_319_DATA 0x0C081C1C
+#define DDRSS_CTL_320_DATA 0x0009030C
+#define DDRSS_CTL_321_DATA 0x090B030F
+#define DDRSS_CTL_322_DATA 0x090B0306
+#define DDRSS_CTL_323_DATA 0x0B090006
+#define DDRSS_CTL_324_DATA 0x0100000B
+#define DDRSS_CTL_325_DATA 0x06030601
+#define DDRSS_CTL_326_DATA 0x00000003
 #define DDRSS_CTL_327_DATA 0x00000000
 #define DDRSS_CTL_328_DATA 0x00010000
 #define DDRSS_CTL_329_DATA 0x00280D00
@@ -397,32 +405,32 @@
 #define DDRSS_CTL_384_DATA 0x00000000
 #define DDRSS_CTL_385_DATA 0x00000000
 #define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x2E2E1B00
+#define DDRSS_CTL_387_DATA 0x33331B00
 #define DDRSS_CTL_388_DATA 0x000A0000
-#define DDRSS_CTL_389_DATA 0x0000019C
+#define DDRSS_CTL_389_DATA 0x000000C6
 #define DDRSS_CTL_390_DATA 0x00000200
 #define DDRSS_CTL_391_DATA 0x00000200
 #define DDRSS_CTL_392_DATA 0x00000200
 #define DDRSS_CTL_393_DATA 0x00000200
-#define DDRSS_CTL_394_DATA 0x000004D4
-#define DDRSS_CTL_395_DATA 0x00001018
+#define DDRSS_CTL_394_DATA 0x00000270
+#define DDRSS_CTL_395_DATA 0x000007BC
 #define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00002890
+#define DDRSS_CTL_397_DATA 0x00001850
 #define DDRSS_CTL_398_DATA 0x00000200
 #define DDRSS_CTL_399_DATA 0x00000200
 #define DDRSS_CTL_400_DATA 0x00000200
 #define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000079B0
-#define DDRSS_CTL_403_DATA 0x000195A0
-#define DDRSS_CTL_404_DATA 0x0000080E
-#define DDRSS_CTL_405_DATA 0x00002890
+#define DDRSS_CTL_402_DATA 0x000048F0
+#define DDRSS_CTL_403_DATA 0x0000F320
+#define DDRSS_CTL_404_DATA 0x00000A14
+#define DDRSS_CTL_405_DATA 0x00001850
 #define DDRSS_CTL_406_DATA 0x00000200
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
 #define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000079B0
-#define DDRSS_CTL_411_DATA 0x000195A0
-#define DDRSS_CTL_412_DATA 0x0202080E
+#define DDRSS_CTL_410_DATA 0x000048F0
+#define DDRSS_CTL_411_DATA 0x0000F320
+#define DDRSS_CTL_412_DATA 0x02020A14
 #define DDRSS_CTL_413_DATA 0x03030202
 #define DDRSS_CTL_414_DATA 0x00000022
 #define DDRSS_CTL_415_DATA 0x00000000
@@ -433,13 +441,13 @@
 #define DDRSS_CTL_420_DATA 0x00000000
 #define DDRSS_CTL_421_DATA 0x00030000
 #define DDRSS_CTL_422_DATA 0x0007001F
-#define DDRSS_CTL_423_DATA 0x0013002B
-#define DDRSS_CTL_424_DATA 0x0013002B
+#define DDRSS_CTL_423_DATA 0x0016002E
+#define DDRSS_CTL_424_DATA 0x0016002E
 #define DDRSS_CTL_425_DATA 0x00000000
 #define DDRSS_CTL_426_DATA 0x00000000
 #define DDRSS_CTL_427_DATA 0x02000000
 #define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x05120512
+#define DDRSS_CTL_429_DATA 0x071A071A
 #define DDRSS_CTL_430_DATA 0x00000105
 #define DDRSS_CTL_431_DATA 0x00010101
 #define DDRSS_CTL_432_DATA 0x00010101
@@ -448,8 +456,8 @@
 #define DDRSS_CTL_435_DATA 0x02000201
 #define DDRSS_CTL_436_DATA 0x02010000
 #define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x18060000
-#define DDRSS_CTL_439_DATA 0x00000118
+#define DDRSS_CTL_438_DATA 0x1E060000
+#define DDRSS_CTL_439_DATA 0x0000011E
 #define DDRSS_CTL_440_DATA 0xFFFFFFFF
 #define DDRSS_CTL_441_DATA 0xFFFFFFFF
 #define DDRSS_CTL_442_DATA 0x00000000
@@ -482,8 +490,8 @@
 #define DDRSS_PI_09_DATA 0x00000000
 #define DDRSS_PI_10_DATA 0x00000000
 #define DDRSS_PI_11_DATA 0x00000000
-#define DDRSS_PI_12_DATA 0x00000007
-#define DDRSS_PI_13_DATA 0x00010002
+#define DDRSS_PI_12_DATA 0x00000003
+#define DDRSS_PI_13_DATA 0x00010001
 #define DDRSS_PI_14_DATA 0x0800000F
 #define DDRSS_PI_15_DATA 0x00000103
 #define DDRSS_PI_16_DATA 0x00000005
@@ -516,7 +524,7 @@
 #define DDRSS_PI_43_DATA 0x00000000
 #define DDRSS_PI_44_DATA 0x00000000
 #define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000017
+#define DDRSS_PI_46_DATA 0x00000019
 #define DDRSS_PI_47_DATA 0x000007D0
 #define DDRSS_PI_48_DATA 0x00000300
 #define DDRSS_PI_49_DATA 0x00000000
@@ -531,18 +539,18 @@
 #define DDRSS_PI_58_DATA 0x00000000
 #define DDRSS_PI_59_DATA 0x00000000
 #define DDRSS_PI_60_DATA 0x0A0A140A
-#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_61_DATA 0x10020201
 #define DDRSS_PI_62_DATA 0x00020805
 #define DDRSS_PI_63_DATA 0x01000404
 #define DDRSS_PI_64_DATA 0x00000000
 #define DDRSS_PI_65_DATA 0x00000000
-#define DDRSS_PI_66_DATA 0x00000100
-#define DDRSS_PI_67_DATA 0x0001010F
+#define DDRSS_PI_66_DATA 0x01000100
+#define DDRSS_PI_67_DATA 0x0102020F
 #define DDRSS_PI_68_DATA 0x00340000
 #define DDRSS_PI_69_DATA 0x00000000
 #define DDRSS_PI_70_DATA 0x00000000
 #define DDRSS_PI_71_DATA 0x0000FFFF
-#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x01000000
 #define DDRSS_PI_73_DATA 0x00080100
 #define DDRSS_PI_74_DATA 0x02000200
 #define DDRSS_PI_75_DATA 0x01000100
@@ -631,104 +639,104 @@
 #define DDRSS_PI_158_DATA 0x00000000
 #define DDRSS_PI_159_DATA 0x00000401
 #define DDRSS_PI_160_DATA 0x00000000
-#define DDRSS_PI_161_DATA 0x00010000
-#define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x1B1B0200
+#define DDRSS_PI_161_DATA 0x05010000
+#define DDRSS_PI_162_DATA 0x00000001
+#define DDRSS_PI_163_DATA 0x20200201
 #define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x00000051
-#define DDRSS_PI_166_DATA 0x00020051
+#define DDRSS_PI_165_DATA 0x0000005C
+#define DDRSS_PI_166_DATA 0x0002005C
 #define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x300C0C04
-#define DDRSS_PI_169_DATA 0x0010300C
-#define DDRSS_PI_170_DATA 0x000000CE
-#define DDRSS_PI_171_DATA 0x00000176
-#define DDRSS_PI_172_DATA 0x00001448
-#define DDRSS_PI_173_DATA 0x00000176
-#define DDRSS_PI_174_DATA 0x04001448
+#define DDRSS_PI_168_DATA 0x400E0C04
+#define DDRSS_PI_169_DATA 0x0010400E
+#define DDRSS_PI_170_DATA 0x00000068
+#define DDRSS_PI_171_DATA 0x000001C0
+#define DDRSS_PI_172_DATA 0x00000C28
+#define DDRSS_PI_173_DATA 0x000001C0
+#define DDRSS_PI_174_DATA 0x04000C28
 #define DDRSS_PI_175_DATA 0x01010404
-#define DDRSS_PI_176_DATA 0x00001501
+#define DDRSS_PI_176_DATA 0x00001500
 #define DDRSS_PI_177_DATA 0x00150015
 #define DDRSS_PI_178_DATA 0x01000100
 #define DDRSS_PI_179_DATA 0x00000100
 #define DDRSS_PI_180_DATA 0x00000000
 #define DDRSS_PI_181_DATA 0x01010101
-#define DDRSS_PI_182_DATA 0x00000101
-#define DDRSS_PI_183_DATA 0x00000100
-#define DDRSS_PI_184_DATA 0x00000100
-#define DDRSS_PI_185_DATA 0x0E040100
-#define DDRSS_PI_186_DATA 0x0808020E
+#define DDRSS_PI_182_DATA 0x00010000
+#define DDRSS_PI_183_DATA 0x00010100
+#define DDRSS_PI_184_DATA 0x00010100
+#define DDRSS_PI_185_DATA 0x14040100
+#define DDRSS_PI_186_DATA 0x0A0A0214
 #define DDRSS_PI_187_DATA 0x00040402
 #define DDRSS_PI_188_DATA 0x000D0035
-#define DDRSS_PI_189_DATA 0x00198041
-#define DDRSS_PI_190_DATA 0x00198041
-#define DDRSS_PI_191_DATA 0x01010101
-#define DDRSS_PI_192_DATA 0x0002000E
-#define DDRSS_PI_193_DATA 0x0002014E
-#define DDRSS_PI_194_DATA 0x0100014E
+#define DDRSS_PI_189_DATA 0x001C0044
+#define DDRSS_PI_190_DATA 0x001C0044
+#define DDRSS_PI_191_DATA 0x01000101
+#define DDRSS_PI_192_DATA 0x0003000E
+#define DDRSS_PI_193_DATA 0x00030190
+#define DDRSS_PI_194_DATA 0x01000190
 #define DDRSS_PI_195_DATA 0x000F000F
-#define DDRSS_PI_196_DATA 0x014F0100
-#define DDRSS_PI_197_DATA 0x0100014F
-#define DDRSS_PI_198_DATA 0x014F014F
-#define DDRSS_PI_199_DATA 0x32103200
-#define DDRSS_PI_200_DATA 0x01013210
+#define DDRSS_PI_196_DATA 0x01910100
+#define DDRSS_PI_197_DATA 0x01000191
+#define DDRSS_PI_198_DATA 0x01910191
+#define DDRSS_PI_199_DATA 0x2F1B3200
+#define DDRSS_PI_200_DATA 0x01012F1B
 #define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x140D080D
-#define DDRSS_PI_203_DATA 0x140D0810
-#define DDRSS_PI_204_DATA 0x0000C010
+#define DDRSS_PI_202_DATA 0x180F090D
+#define DDRSS_PI_203_DATA 0x180F0911
+#define DDRSS_PI_204_DATA 0x0000C011
 #define DDRSS_PI_205_DATA 0x00C01000
 #define DDRSS_PI_206_DATA 0x00C01000
 #define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x001C000E
-#define DDRSS_PI_209_DATA 0x001C014E
-#define DDRSS_PI_210_DATA 0x0011014E
+#define DDRSS_PI_208_DATA 0x001E000E
+#define DDRSS_PI_209_DATA 0x001E0190
+#define DDRSS_PI_210_DATA 0x00110190
 #define DDRSS_PI_211_DATA 0x32000056
-#define DDRSS_PI_212_DATA 0x00000301
-#define DDRSS_PI_213_DATA 0x005A002A
+#define DDRSS_PI_212_DATA 0x00000101
+#define DDRSS_PI_213_DATA 0x005E0030
 #define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00002A00
-#define DDRSS_PI_216_DATA 0x3212005A
-#define DDRSS_PI_217_DATA 0x09000301
-#define DDRSS_PI_218_DATA 0x04010504
-#define DDRSS_PI_219_DATA 0x040006C9
+#define DDRSS_PI_215_DATA 0x00003000
+#define DDRSS_PI_216_DATA 0x3212005E
+#define DDRSS_PI_217_DATA 0x09000001
+#define DDRSS_PI_218_DATA 0x06010504
+#define DDRSS_PI_219_DATA 0x04000364
 #define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x1C1F0B0A
-#define DDRSS_PI_222_DATA 0x00001D12
-#define DDRSS_PI_223_DATA 0x3C00A488
-#define DDRSS_PI_224_DATA 0x13142005
-#define DDRSS_PI_225_DATA 0x1C1F0B0E
-#define DDRSS_PI_226_DATA 0x00001D12
-#define DDRSS_PI_227_DATA 0x3C00A488
-#define DDRSS_PI_228_DATA 0x13142005
-#define DDRSS_PI_229_DATA 0x00019C0E
-#define DDRSS_PI_230_DATA 0x00001018
-#define DDRSS_PI_231_DATA 0x00002890
-#define DDRSS_PI_232_DATA 0x000195A0
-#define DDRSS_PI_233_DATA 0x00002890
-#define DDRSS_PI_234_DATA 0x000195A0
-#define DDRSS_PI_235_DATA 0x01800010
-#define DDRSS_PI_236_DATA 0x03030180
+#define DDRSS_PI_221_DATA 0x21250D0A
+#define DDRSS_PI_222_DATA 0x00002216
+#define DDRSS_PI_223_DATA 0x480062B8
+#define DDRSS_PI_224_DATA 0x17182006
+#define DDRSS_PI_225_DATA 0x21250D10
+#define DDRSS_PI_226_DATA 0x00002216
+#define DDRSS_PI_227_DATA 0x480062B8
+#define DDRSS_PI_228_DATA 0x17182006
+#define DDRSS_PI_229_DATA 0x0000C610
+#define DDRSS_PI_230_DATA 0x000007BC
+#define DDRSS_PI_231_DATA 0x00001850
+#define DDRSS_PI_232_DATA 0x0000F320
+#define DDRSS_PI_233_DATA 0x00001850
+#define DDRSS_PI_234_DATA 0x0000F320
+#define DDRSS_PI_235_DATA 0x01CC0010
+#define DDRSS_PI_236_DATA 0x030301CC
 #define DDRSS_PI_237_DATA 0x002AF803
 #define DDRSS_PI_238_DATA 0x0001ADAF
 #define DDRSS_PI_239_DATA 0x00000005
 #define DDRSS_PI_240_DATA 0x0000006E
 #define DDRSS_PI_241_DATA 0x00000010
-#define DDRSS_PI_242_DATA 0x000411AB
+#define DDRSS_PI_242_DATA 0x0004E200
 #define DDRSS_PI_243_DATA 0x0001ADAF
 #define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000A6B
-#define DDRSS_PI_246_DATA 0x00000180
-#define DDRSS_PI_247_DATA 0x000411AB
+#define DDRSS_PI_245_DATA 0x00000C80
+#define DDRSS_PI_246_DATA 0x000001CC
+#define DDRSS_PI_247_DATA 0x0004E200
 #define DDRSS_PI_248_DATA 0x0001ADAF
 #define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000A6B
-#define DDRSS_PI_251_DATA 0x01000180
+#define DDRSS_PI_250_DATA 0x00000C80
+#define DDRSS_PI_251_DATA 0x010001CC
 #define DDRSS_PI_252_DATA 0x00370040
 #define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x05360040
-#define DDRSS_PI_255_DATA 0x00010028
-#define DDRSS_PI_256_DATA 0x05360040
-#define DDRSS_PI_257_DATA 0x00000328
-#define DDRSS_PI_258_DATA 0x00430043
+#define DDRSS_PI_254_DATA 0x06400040
+#define DDRSS_PI_255_DATA 0x00010030
+#define DDRSS_PI_256_DATA 0x06400040
+#define DDRSS_PI_257_DATA 0x00000330
+#define DDRSS_PI_258_DATA 0x00500050
 #define DDRSS_PI_259_DATA 0x08040404
 #define DDRSS_PI_260_DATA 0x00000055
 #define DDRSS_PI_261_DATA 0x55083C5A
@@ -745,29 +753,29 @@
 #define DDRSS_PI_272_DATA 0x00080804
 #define DDRSS_PI_273_DATA 0x00000000
 #define DDRSS_PI_274_DATA 0x00000000
-#define DDRSS_PI_275_DATA 0x002B0084
+#define DDRSS_PI_275_DATA 0x00EB0084
 #define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x362B24C4
+#define DDRSS_PI_277_DATA 0x36EB2DD4
 #define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x362B24C4
+#define DDRSS_PI_279_DATA 0x36EB2DD4
 #define DDRSS_PI_280_DATA 0x00150F27
-#define DDRSS_PI_281_DATA 0x002B0084
+#define DDRSS_PI_281_DATA 0x00EB0084
 #define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x362B24C4
+#define DDRSS_PI_283_DATA 0x36EB2DD4
 #define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x362B24C4
+#define DDRSS_PI_285_DATA 0x36EB2DD4
 #define DDRSS_PI_286_DATA 0x00150F27
-#define DDRSS_PI_287_DATA 0x002B0084
+#define DDRSS_PI_287_DATA 0x00EB0084
 #define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x362B24C4
+#define DDRSS_PI_289_DATA 0x36EB2DD4
 #define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x362B24C4
+#define DDRSS_PI_291_DATA 0x36EB2DD4
 #define DDRSS_PI_292_DATA 0x00150F27
-#define DDRSS_PI_293_DATA 0x002B0084
+#define DDRSS_PI_293_DATA 0x00EB0084
 #define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x362B24C4
+#define DDRSS_PI_295_DATA 0x36EB2DD4
 #define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x362B24C4
+#define DDRSS_PI_297_DATA 0x36EB2DD4
 #define DDRSS_PI_298_DATA 0x00150F27
 #define DDRSS_PI_299_DATA 0x00000000

@@ -783,7 +791,7 @@
 #define DDRSS_PHY_09_DATA 0x00000000
 #define DDRSS_PHY_10_DATA 0x00000000
 #define DDRSS_PHY_11_DATA 0x01000001
-#define DDRSS_PHY_12_DATA 0x00000100
+#define DDRSS_PHY_12_DATA 0x00000200
 #define DDRSS_PHY_13_DATA 0x000800C0
 #define DDRSS_PHY_14_DATA 0x060100CC
 #define DDRSS_PHY_15_DATA 0x00030066
@@ -802,9 +810,9 @@
 #define DDRSS_PHY_28_DATA 0x2A000000
 #define DDRSS_PHY_29_DATA 0x00000808
 #define DDRSS_PHY_30_DATA 0x0F000000
-#define DDRSS_PHY_31_DATA 0x00000F0F
-#define DDRSS_PHY_32_DATA 0x10200000
-#define DDRSS_PHY_33_DATA 0x0C002007
+#define DDRSS_PHY_31_DATA 0x00000F08
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
 #define DDRSS_PHY_34_DATA 0x00000000
 #define DDRSS_PHY_35_DATA 0x00000000
 #define DDRSS_PHY_36_DATA 0x55555555
@@ -871,20 +879,20 @@
 #define DDRSS_PHY_97_DATA 0x00050010
 #define DDRSS_PHY_98_DATA 0x51517041
 #define DDRSS_PHY_99_DATA 0x31C06000
-#define DDRSS_PHY_100_DATA 0x07AB0340
+#define DDRSS_PHY_100_DATA 0x07AB01AB
 #define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x09080001
+#define DDRSS_PHY_102_DATA 0x0B0A0101
 #define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C063E42
-#define DDRSS_PHY_105_DATA 0x0F0C2701
+#define DDRSS_PHY_104_DATA 0x0C073E42
+#define DDRSS_PHY_105_DATA 0x0F0C2D01
 #define DDRSS_PHY_106_DATA 0x01000140
-#define DDRSS_PHY_107_DATA 0x04000420
+#define DDRSS_PHY_107_DATA 0x0C000420
 #define DDRSS_PHY_108_DATA 0x00000198
 #define DDRSS_PHY_109_DATA 0x0A0000D0
 #define DDRSS_PHY_110_DATA 0x00030200
 #define DDRSS_PHY_111_DATA 0x02800000
 #define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x00092010
+#define DDRSS_PHY_113_DATA 0x000B2010
 #define DDRSS_PHY_114_DATA 0x76543210
 #define DDRSS_PHY_115_DATA 0x00000008
 #define DDRSS_PHY_116_DATA 0x02800280
@@ -901,8 +909,8 @@
 #define DDRSS_PHY_127_DATA 0x00A000A0
 #define DDRSS_PHY_128_DATA 0x00A000A0
 #define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x01C400A0
-#define DDRSS_PHY_131_DATA 0x01A00003
+#define DDRSS_PHY_130_DATA 0x011900A0
+#define DDRSS_PHY_131_DATA 0x01A00004
 #define DDRSS_PHY_132_DATA 0x00000000
 #define DDRSS_PHY_133_DATA 0x00000000
 #define DDRSS_PHY_134_DATA 0x00080200
@@ -1039,7 +1047,7 @@
 #define DDRSS_PHY_265_DATA 0x00000000
 #define DDRSS_PHY_266_DATA 0x00000000
 #define DDRSS_PHY_267_DATA 0x01000001
-#define DDRSS_PHY_268_DATA 0x00000100
+#define DDRSS_PHY_268_DATA 0x00000200
 #define DDRSS_PHY_269_DATA 0x000800C0
 #define DDRSS_PHY_270_DATA 0x060100CC
 #define DDRSS_PHY_271_DATA 0x00030066
@@ -1058,9 +1066,9 @@
 #define DDRSS_PHY_284_DATA 0x2A000000
 #define DDRSS_PHY_285_DATA 0x00000808
 #define DDRSS_PHY_286_DATA 0x0F000000
-#define DDRSS_PHY_287_DATA 0x00000F0F
-#define DDRSS_PHY_288_DATA 0x10200000
-#define DDRSS_PHY_289_DATA 0x0C002007
+#define DDRSS_PHY_287_DATA 0x00000F08
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
 #define DDRSS_PHY_290_DATA 0x00000000
 #define DDRSS_PHY_291_DATA 0x00000000
 #define DDRSS_PHY_292_DATA 0x55555555
@@ -1127,20 +1135,20 @@
 #define DDRSS_PHY_353_DATA 0x00050010
 #define DDRSS_PHY_354_DATA 0x51517041
 #define DDRSS_PHY_355_DATA 0x31C06000
-#define DDRSS_PHY_356_DATA 0x07AB0340
+#define DDRSS_PHY_356_DATA 0x07AB01AB
 #define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x09080001
+#define DDRSS_PHY_358_DATA 0x0B0A0101
 #define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C063E42
-#define DDRSS_PHY_361_DATA 0x0F0C2701
+#define DDRSS_PHY_360_DATA 0x0C073E42
+#define DDRSS_PHY_361_DATA 0x0F0C2D01
 #define DDRSS_PHY_362_DATA 0x01000140
-#define DDRSS_PHY_363_DATA 0x04000420
+#define DDRSS_PHY_363_DATA 0x0C000420
 #define DDRSS_PHY_364_DATA 0x00000198
 #define DDRSS_PHY_365_DATA 0x0A0000D0
 #define DDRSS_PHY_366_DATA 0x00030200
 #define DDRSS_PHY_367_DATA 0x02800000
 #define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x00092010
+#define DDRSS_PHY_369_DATA 0x000B2010
 #define DDRSS_PHY_370_DATA 0x76543210
 #define DDRSS_PHY_371_DATA 0x00000008
 #define DDRSS_PHY_372_DATA 0x02800280
@@ -1157,8 +1165,8 @@
 #define DDRSS_PHY_383_DATA 0x00A000A0
 #define DDRSS_PHY_384_DATA 0x00A000A0
 #define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x01C400A0
-#define DDRSS_PHY_387_DATA 0x01A00003
+#define DDRSS_PHY_386_DATA 0x011900A0
+#define DDRSS_PHY_387_DATA 0x01A00004
 #define DDRSS_PHY_388_DATA 0x00000000
 #define DDRSS_PHY_389_DATA 0x00000000
 #define DDRSS_PHY_390_DATA 0x00080200
@@ -1295,7 +1303,7 @@
 #define DDRSS_PHY_521_DATA 0x00000000
 #define DDRSS_PHY_522_DATA 0x00000000
 #define DDRSS_PHY_523_DATA 0x01000001
-#define DDRSS_PHY_524_DATA 0x00000100
+#define DDRSS_PHY_524_DATA 0x00000200
 #define DDRSS_PHY_525_DATA 0x000800C0
 #define DDRSS_PHY_526_DATA 0x060100CC
 #define DDRSS_PHY_527_DATA 0x00030066
@@ -1314,9 +1322,9 @@
 #define DDRSS_PHY_540_DATA 0x2A000000
 #define DDRSS_PHY_541_DATA 0x00000808
 #define DDRSS_PHY_542_DATA 0x0F000000
-#define DDRSS_PHY_543_DATA 0x00000F0F
-#define DDRSS_PHY_544_DATA 0x10200000
-#define DDRSS_PHY_545_DATA 0x0C002007
+#define DDRSS_PHY_543_DATA 0x00000F08
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
 #define DDRSS_PHY_546_DATA 0x00000000
 #define DDRSS_PHY_547_DATA 0x00000000
 #define DDRSS_PHY_548_DATA 0x55555555
@@ -1383,20 +1391,20 @@
 #define DDRSS_PHY_609_DATA 0x00050010
 #define DDRSS_PHY_610_DATA 0x51517041
 #define DDRSS_PHY_611_DATA 0x31C06000
-#define DDRSS_PHY_612_DATA 0x07AB0340
+#define DDRSS_PHY_612_DATA 0x07AB01AB
 #define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x09080001
+#define DDRSS_PHY_614_DATA 0x0B0A0101
 #define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C063E42
-#define DDRSS_PHY_617_DATA 0x0F0C2701
+#define DDRSS_PHY_616_DATA 0x0C073E42
+#define DDRSS_PHY_617_DATA 0x0F0C2D01
 #define DDRSS_PHY_618_DATA 0x01000140
-#define DDRSS_PHY_619_DATA 0x04000420
+#define DDRSS_PHY_619_DATA 0x0C000420
 #define DDRSS_PHY_620_DATA 0x00000198
 #define DDRSS_PHY_621_DATA 0x0A0000D0
 #define DDRSS_PHY_622_DATA 0x00030200
 #define DDRSS_PHY_623_DATA 0x02800000
 #define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x00092010
+#define DDRSS_PHY_625_DATA 0x000B2010
 #define DDRSS_PHY_626_DATA 0x76543210
 #define DDRSS_PHY_627_DATA 0x00000008
 #define DDRSS_PHY_628_DATA 0x02800280
@@ -1413,8 +1421,8 @@
 #define DDRSS_PHY_639_DATA 0x00A000A0
 #define DDRSS_PHY_640_DATA 0x00A000A0
 #define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x01C400A0
-#define DDRSS_PHY_643_DATA 0x01A00003
+#define DDRSS_PHY_642_DATA 0x011900A0
+#define DDRSS_PHY_643_DATA 0x01A00004
 #define DDRSS_PHY_644_DATA 0x00000000
 #define DDRSS_PHY_645_DATA 0x00000000
 #define DDRSS_PHY_646_DATA 0x00080200
@@ -1551,7 +1559,7 @@
 #define DDRSS_PHY_777_DATA 0x00000000
 #define DDRSS_PHY_778_DATA 0x00000000
 #define DDRSS_PHY_779_DATA 0x01000001
-#define DDRSS_PHY_780_DATA 0x00000100
+#define DDRSS_PHY_780_DATA 0x00000200
 #define DDRSS_PHY_781_DATA 0x000800C0
 #define DDRSS_PHY_782_DATA 0x060100CC
 #define DDRSS_PHY_783_DATA 0x00030066
@@ -1570,9 +1578,9 @@
 #define DDRSS_PHY_796_DATA 0x2A000000
 #define DDRSS_PHY_797_DATA 0x00000808
 #define DDRSS_PHY_798_DATA 0x0F000000
-#define DDRSS_PHY_799_DATA 0x00000F0F
-#define DDRSS_PHY_800_DATA 0x10200000
-#define DDRSS_PHY_801_DATA 0x0C002007
+#define DDRSS_PHY_799_DATA 0x00000F08
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
 #define DDRSS_PHY_802_DATA 0x00000000
 #define DDRSS_PHY_803_DATA 0x00000000
 #define DDRSS_PHY_804_DATA 0x55555555
@@ -1639,20 +1647,20 @@
 #define DDRSS_PHY_865_DATA 0x00050010
 #define DDRSS_PHY_866_DATA 0x51517041
 #define DDRSS_PHY_867_DATA 0x31C06000
-#define DDRSS_PHY_868_DATA 0x07AB0340
+#define DDRSS_PHY_868_DATA 0x07AB01AB
 #define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x09080001
+#define DDRSS_PHY_870_DATA 0x0B0A0101
 #define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C063E42
-#define DDRSS_PHY_873_DATA 0x0F0C2701
+#define DDRSS_PHY_872_DATA 0x0C073E42
+#define DDRSS_PHY_873_DATA 0x0F0C2D01
 #define DDRSS_PHY_874_DATA 0x01000140
-#define DDRSS_PHY_875_DATA 0x04000420
+#define DDRSS_PHY_875_DATA 0x0C000420
 #define DDRSS_PHY_876_DATA 0x00000198
 #define DDRSS_PHY_877_DATA 0x0A0000D0
 #define DDRSS_PHY_878_DATA 0x00030200
 #define DDRSS_PHY_879_DATA 0x02800000
 #define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x00092010
+#define DDRSS_PHY_881_DATA 0x000B2010
 #define DDRSS_PHY_882_DATA 0x76543210
 #define DDRSS_PHY_883_DATA 0x00000008
 #define DDRSS_PHY_884_DATA 0x02800280
@@ -1669,8 +1677,8 @@
 #define DDRSS_PHY_895_DATA 0x00A000A0
 #define DDRSS_PHY_896_DATA 0x00A000A0
 #define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x01C400A0
-#define DDRSS_PHY_899_DATA 0x01A00003
+#define DDRSS_PHY_898_DATA 0x011900A0
+#define DDRSS_PHY_899_DATA 0x01A00004
 #define DDRSS_PHY_900_DATA 0x00000000
 #define DDRSS_PHY_901_DATA 0x00000000
 #define DDRSS_PHY_902_DATA 0x00080200
@@ -1810,7 +1818,7 @@
 #define DDRSS_PHY_1036_DATA 0x00000080
 #define DDRSS_PHY_1037_DATA 0x00DCBA98
 #define DDRSS_PHY_1038_DATA 0x03000000
-#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1039_DATA 0x00200001
 #define DDRSS_PHY_1040_DATA 0x00000000
 #define DDRSS_PHY_1041_DATA 0x00000000
 #define DDRSS_PHY_1042_DATA 0x00000000
@@ -1826,7 +1834,7 @@
 #define DDRSS_PHY_1052_DATA 0x00000033
 #define DDRSS_PHY_1053_DATA 0x00543210
 #define DDRSS_PHY_1054_DATA 0x003F0000
-#define DDRSS_PHY_1055_DATA 0x000F013F
+#define DDRSS_PHY_1055_DATA 0x000F3F3F
 #define DDRSS_PHY_1056_DATA 0x20202003
 #define DDRSS_PHY_1057_DATA 0x00202020
 #define DDRSS_PHY_1058_DATA 0x20008008
@@ -1835,7 +1843,7 @@
 #define DDRSS_PHY_1061_DATA 0x00000000
 #define DDRSS_PHY_1062_DATA 0x00000000
 #define DDRSS_PHY_1063_DATA 0x00000000
-#define DDRSS_PHY_1064_DATA 0x000205BB
+#define DDRSS_PHY_1064_DATA 0x000305CC
 #define DDRSS_PHY_1065_DATA 0x00030000
 #define DDRSS_PHY_1066_DATA 0x00000300
 #define DDRSS_PHY_1067_DATA 0x00000300
@@ -1844,8 +1852,8 @@
 #define DDRSS_PHY_1070_DATA 0x00000300
 #define DDRSS_PHY_1071_DATA 0x42080010
 #define DDRSS_PHY_1072_DATA 0x0000803E
-#define DDRSS_PHY_1073_DATA 0x00000001
-#define DDRSS_PHY_1074_DATA 0x01000102
+#define DDRSS_PHY_1073_DATA 0x00000004
+#define DDRSS_PHY_1074_DATA 0x01000002
 #define DDRSS_PHY_1075_DATA 0x00008000
 #define DDRSS_PHY_1076_DATA 0x00000000
 #define DDRSS_PHY_1077_DATA 0x00000000
@@ -2074,14 +2082,14 @@
 #define DDRSS_PHY_1300_DATA 0x00040101
 #define DDRSS_PHY_1301_DATA 0x0000010F
 #define DDRSS_PHY_1302_DATA 0x00000000
-#define DDRSS_PHY_1303_DATA 0x0000FFFF
+#define DDRSS_PHY_1303_DATA 0x00000064
 #define DDRSS_PHY_1304_DATA 0x00000000
 #define DDRSS_PHY_1305_DATA 0x01010000
 #define DDRSS_PHY_1306_DATA 0x01080402
 #define DDRSS_PHY_1307_DATA 0x01200F02
 #define DDRSS_PHY_1308_DATA 0x00194280
 #define DDRSS_PHY_1309_DATA 0x00000004
-#define DDRSS_PHY_1310_DATA 0x00052000
+#define DDRSS_PHY_1310_DATA 0x00042000
 #define DDRSS_PHY_1311_DATA 0x00000000
 #define DDRSS_PHY_1312_DATA 0x00000000
 #define DDRSS_PHY_1313_DATA 0x00000000
@@ -2165,10 +2173,10 @@
 #define DDRSS_PHY_1391_DATA 0x00000000
 #define DDRSS_PHY_1392_DATA 0x00000000
 #define DDRSS_PHY_1393_DATA 0x0001F7C0
-#define DDRSS_PHY_1394_DATA 0x00000002
+#define DDRSS_PHY_1394_DATA 0x00000003
 #define DDRSS_PHY_1395_DATA 0x00000000
 #define DDRSS_PHY_1396_DATA 0x00001142
-#define DDRSS_PHY_1397_DATA 0x010207AB
+#define DDRSS_PHY_1397_DATA 0x040207AB
 #define DDRSS_PHY_1398_DATA 0x01000080
 #define DDRSS_PHY_1399_DATA 0x03900390
 #define DDRSS_PHY_1400_DATA 0x03900390
@@ -2177,20 +2185,23 @@
 #define DDRSS_PHY_1403_DATA 0x00000390
 #define DDRSS_PHY_1404_DATA 0x00000390
 #define DDRSS_PHY_1405_DATA 0x00000005
-#define DDRSS_PHY_1406_DATA 0x01813FBB
-#define DDRSS_PHY_1407_DATA 0x000000BB
+#define DDRSS_PHY_1406_DATA 0x01813FCC
+#define DDRSS_PHY_1407_DATA 0x000000CC
 #define DDRSS_PHY_1408_DATA 0x0C000DFF
 #define DDRSS_PHY_1409_DATA 0x30000DFF
 #define DDRSS_PHY_1410_DATA 0x3F0DFF11
 #define DDRSS_PHY_1411_DATA 0x000100F0
-#define DDRSS_PHY_1412_DATA 0x780DFFBB
+#define DDRSS_PHY_1412_DATA 0x780DFFCC
 #define DDRSS_PHY_1413_DATA 0x00007E31
 #define DDRSS_PHY_1414_DATA 0x000CBF11
-#define DDRSS_PHY_1415_DATA 0x01770010
+#define DDRSS_PHY_1415_DATA 0x01990010
 #define DDRSS_PHY_1416_DATA 0x000CBF11
-#define DDRSS_PHY_1417_DATA 0x01770010
+#define DDRSS_PHY_1417_DATA 0x01990010
 #define DDRSS_PHY_1418_DATA 0x3F0DFF11
-#define DDRSS_PHY_1419_DATA 0x017700F0
+#define DDRSS_PHY_1419_DATA 0x00EF00F0
 #define DDRSS_PHY_1420_DATA 0x3F0DFF11
 #define DDRSS_PHY_1421_DATA 0x01FF00F0
 #define DDRSS_PHY_1422_DATA 0x20040006
+
+
+
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -6,7 +6,7 @@
 /dts-v1/;

 #include "k3-j7200-common-proc-board.dts"
-#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
+#include "k3-j7200-ddr-evm-lp4-3200.dtsi"
 #include "k3-j721e-ddr.dtsi"
 #include "k3-j7200-common-proc-board-u-boot.dtsi"
 #include "k3-j7200-r5.dtsi"
--- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
--- a/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j742s2-ddr-evm-lp4-4266.dtsi
--- a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
--- a/doc/board/ti/k3.rst
+++ b/doc/board/ti/k3.rst
@@ -651,6 +651,17 @@ Refer (:ref:`U-boot ARMV8 build <k3_rst_include_start_build_steps_uboot>`)
   This will need to be explicitly disabled by changing the boot_targets to
   disallow fallback during testing.

+DDR Configuration
+-----------------
+
+The K3 DDRSS driver (drivers/ram/k3-ddrss/k3-ddrss.c) configures the DDR during
+the R5 SPL stage. The driver utilizes an auto-generated configuration file
+containing necessary settings for the DDR. It configures the frequency, timing
+parameters, training algorithms etc. for DDR initialization. The configuration
+DTSI can be generated using the `Sysconfig tool <https://dev.ti.com/sysconfig>`_
+and selecting the software product as "DDR Configuration for \*" as well as the
+required device.
+
 Saving environment
 ------------------

--- a/doc/sphinx/requirements.txt
+++ b/doc/sphinx/requirements.txt
@@ -23,4 +23,4 @@ sphinxcontrib-jquery==4.1
 sphinxcontrib-jsmath==1.0.1
 sphinxcontrib-qthelp==2.0.0
 sphinxcontrib-serializinghtml==2.0.0
-urllib3==2.6.3
+urllib3==2.7.0
--- a/drivers/usb/host/usb-uclass.c
+++ b/drivers/usb/host/usb-uclass.c
@@ -134,7 +134,7 @@ int usb_alloc_device(struct usb_device *udev)
 	struct udevice *bus = udev->controller_dev;
 	struct dm_usb_ops *ops = usb_get_ops(bus);

-	/* This is only requird by some controllers - current XHCI */
+	/* This is only required by some controllers - currently XHCI */
 	if (!ops->alloc_device)
 		return 0;

--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -108,11 +108,13 @@ void efi_print_image_infos(void *pc)
 * @rel_size:		size of the relocation table in bytes
 * @efi_reloc:		actual load address of the image
 * @pref_address:	preferred load address of the image
+ * @virt_size:		virtual image size as provided in the PE-COFF header
 * Return:		status code
 */
 static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
-			unsigned long rel_size, void *efi_reloc,
-			unsigned long pref_address)
+					unsigned long rel_size, void *efi_reloc,
+					unsigned long pref_address,
+					unsigned long virt_size)
 {
 	unsigned long delta = (unsigned long)efi_reloc - pref_address;
 	const IMAGE_BASE_RELOCATION *end;
@@ -122,34 +124,95 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
 		return EFI_SUCCESS;

 	end = (const IMAGE_BASE_RELOCATION *)((const char *)rel + rel_size);
-	while (rel + 1 < end && rel->SizeOfBlock) {
+	while (rel + 1 < end) {
 		const uint16_t *relocs = (const uint16_t *)(rel + 1);
+
+		/* Each block must start on a 32-bit boundary */
+		if (!IS_ALIGNED((uintptr_t)rel, sizeof(uint32_t))) {
+			log_debug("Relocation block not 32-bit aligned\n");
+			return EFI_LOAD_ERROR;
+		}
+		/* Relocation block cannot be shorter than its header */
+		if (rel->SizeOfBlock < sizeof(*rel)) {
+			log_debug("Relocation block too small: %u\n",
+				rel->SizeOfBlock);
+			return EFI_LOAD_ERROR;
+		}
+		/* All relocation entries must be inside the .reloc section */
+		if ((const char *)rel + rel->SizeOfBlock > (const char *)end) {
+			log_debug("Relocation block exceeds relocation data\n");
+			return EFI_LOAD_ERROR;
+		}
+		/*
+		 * Relocations must be within the virtual address range.
+		 * This also ensures that there is no overflow in the
+		 * entry_offset check below.
+		 */
+		if (rel->VirtualAddress > virt_size) {
+			log_debug("relocation address out of bounds\n");
+			return EFI_LOAD_ERROR;
+		}
+
 		i = (rel->SizeOfBlock - sizeof(*rel)) / sizeof(uint16_t);
 		while (i--) {
-			uint32_t offset = (uint32_t)(*relocs & 0xfff) +
-					  rel->VirtualAddress;
+			uint32_t entry_offset = *relocs & 0xfff;
+			unsigned long offset;
 			int type = *relocs >> EFI_PAGE_SHIFT;
-			uint64_t *x64 = efi_reloc + offset;
-			uint32_t *x32 = efi_reloc + offset;
-			uint16_t *x16 = efi_reloc + offset;
+			uint64_t *x64;
+			uint32_t *x32;
+			uint16_t *x16;
+
+			/*
+			 * Relocation address must be within virtual address
+			 * range.
+			 */
+			if (entry_offset > virt_size - rel->VirtualAddress) {
+				log_debug("relocation address out of bounds\n");
+				return EFI_LOAD_ERROR;
+			}
+
+			offset = rel->VirtualAddress + entry_offset;
+			x64 = efi_reloc + offset;
+			x32 = efi_reloc + offset;
+			x16 = efi_reloc + offset;

 			switch (type) {
 			case IMAGE_REL_BASED_ABSOLUTE:
 				break;
 			case IMAGE_REL_BASED_HIGH:
+				if (sizeof(uint16_t) > virt_size - offset) {
+					log_debug("relocation address out of bounds\n");
+					return EFI_LOAD_ERROR;
+				}
 				*x16 += ((uint32_t)delta) >> 16;
 				break;
 			case IMAGE_REL_BASED_LOW:
+				if (sizeof(uint16_t) > virt_size - offset) {
+					log_debug("relocation address out of bounds\n");
+					return EFI_LOAD_ERROR;
+				}
 				*x16 += (uint16_t)delta;
 				break;
 			case IMAGE_REL_BASED_HIGHLOW:
+				if (sizeof(uint32_t) > virt_size - offset) {
+					log_debug("relocation address out of bounds\n");
+					return EFI_LOAD_ERROR;
+				}
 				*x32 += (uint32_t)delta;
 				break;
 			case IMAGE_REL_BASED_DIR64:
+				if (sizeof(uint64_t) > virt_size - offset) {
+					log_debug("relocation address out of bounds\n");
+					return EFI_LOAD_ERROR;
+				}
 				*x64 += (uint64_t)delta;
 				break;
 #ifdef __riscv
 			case IMAGE_REL_BASED_RISCV_HI20:
+				if (sizeof(uint32_t) > virt_size - offset) {
+					log_debug("relocation address out of bounds\n");
+					return EFI_LOAD_ERROR;
+				}
 				*x32 = ((*x32 & 0xfffff000) + (uint32_t)delta) |
 					(*x32 & 0x00000fff);
 				break;
@@ -163,7 +226,7 @@ static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
 				break;
 #endif
 			default:
-				log_err("Unknown Relocation off %x type %x\n",
+				log_err("Unknown Relocation off %lx type %x\n",
 					offset, type);
 				return EFI_LOAD_ERROR;
 			}
@@ -970,8 +1033,9 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle,

 	/* Run through relocations */
 	if (efi_loader_relocate(rel, rel_size, efi_reloc,
-				(unsigned long)image_base) != EFI_SUCCESS) {
-		efi_free_pages((uintptr_t) efi_reloc,
+				(unsigned long)image_base,
+				virt_size) != EFI_SUCCESS) {
+		efi_free_pages((uintptr_t)efi_reloc,
 			       (virt_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT);
 		ret = EFI_LOAD_ERROR;
 		goto err;
--- a/tools/dtoc/test_fdt.py
+++ b/tools/dtoc/test_fdt.py
@@ -986,7 +986,7 @@ def main():
                        default=False, help='run tests')
    parser.add_argument('-T', '--test-coverage', action='store_true',
                        default=False,
-                        help='run tests and check for 100% coverage')
+                        help='run tests and check for 100%% coverage')
    parser.add_argument('name', nargs='*')
    args = parser.parse_args()
Author	SHA1	Message	Date
Tom Rini	3f79f77761	Merge tag 'efi-2026-07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi Pull request efi-2026-07-rc5 CI: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/30365 Documentation: * Update urllib3 version for building * usb: typos 'requird', 'current' UEFI * Improve PE-COFF relocation data validation Devicetree-to-C generator: * dtoc: test: add missing escape in help text	2026-06-09 10:27:02 -06:00
Tom Rini	cf81e36fa0	Merge patch series "ti: j7: Update to v0.12.0 of DDR config tool" Neha Malcom Francis <n-francis@ti.com> says: Update all DDR configuration DTSIs to the latest auto-generated output of the Sysconfig Tool (DDR Configuration for TDA4x, DRA8x, AM67x, AM68x, AM69x (0.12.00.0000)) [0] The auto-generated files must not be modified, but effort will be taken to change the tool output to adhere to the latest checkpatch.pl rules. J722S and J721E will also be updated in a subsequent series. All the changes have been kernel boot tested and memtester has passed (same as v1, as no functional changes made). [0] https://dev.ti.com/sysconfig/#/start Link: https://lore.kernel.org/r/20251103071035.674604-1-n-francis@ti.com	2026-06-09 10:26:36 -06:00
Neha Malcom Francis	11dc7c0608	doc: ti: k3: Add section for DDR configuration Add a concise section for DDR configuration pointing to the public tool that can be used to generate the configuration DTSI. Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Romain Naour <romain.naour@smile.fr>	2026-06-09 10:26:21 -06:00
Neha Malcom Francis	54fb646ca4	arm: dts: k3-j742s2: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J742S2 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>	2026-06-09 10:26:21 -06:00
Neha Malcom Francis	fe22382b64	arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for AM69 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>	2026-06-09 10:26:21 -06:00
Neha Malcom Francis	c70fd4e5a2	arm: dts: k3-j784s4: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J784S4 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>	2026-06-09 10:26:21 -06:00
Neha Malcom Francis	1686817959	arm: dts: k3-am68: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for AM68 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>	2026-06-09 10:26:21 -06:00
Neha Malcom Francis	9627d70840	arm: dts: k3-j721s2: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J721S2 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>	2026-06-09 10:26:20 -06:00
Neha Malcom Francis	e126a99992	arm: dts: k3-j7200: ddr: Update to v0.12.0 of DDR config tool Update the DDR configuration for J7200 according to the SysConfig DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0 is [0]. [0] https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html Tested-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>	2026-06-09 10:26:20 -06:00
Heinrich Schuchardt	5a1818d54c	usb: typos 'requird', 'current' %s/requird/required/ %s/current XHCI/currently XHCI/ Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>	2026-06-07 16:44:04 +02:00
Heinrich Schuchardt	bc82aa5b41	efi_loader: validate PE-COFF relocation data When applying base relocations from a PE-COFF binary all data must be treated as untrusted. Add the following checks to efi_loader_relocate(): * Reject relocation blocks that don't start on a 32-bit aligned address. * Reject relocation blocks whose SizeOfBlock is smaller than the block header, which would cause an unsigned underflow when computing the entry count. * A block with SizeOfBlock == 0 is invalid and does not mark the end of the relocation table. * Reject relocation blocks that extend beyond the end of the relocation section. * Reject individual relocation entries whose target offset, together with the access width, exceeds the mapped image size, preventing out-of-bounds writes. Pass virt_size to efi_loader_relocate() from efi_load_pe() to enable the per-entry bounds check. Reported-by: Anas Cherni <anas@calif.io> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>	2026-06-07 16:43:06 +02:00
Francesco Valla	badf750282	dtoc: test: add missing escape in help text A single percent sign might be interpreted as a string format directive and shall thus be escaped - doubling it - to actually indicate a percentage. Without the escape, pytest fails to run test_fdt.py with the following error: ValueError: Test coverage failure fdt code coverage: Traceback (most recent call last): File "/usr/lib64/python3.14/argparse.py", line 1748, in _check_help formatter._expand_help(action) ~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^ File "/usr/lib64/python3.14/argparse.py", line 676, in _expand_help return help_string % params ~~~~~~~~~~~~^~~~~~~~ TypeError: %c requires an int or a unicode character, not dict The above exception was the direct cause of the following exception: Traceback (most recent call last): File "/home/user/u-boot/./tools/dtoc/test_fdt", line 1002, in <module> sys.exit(main()) ~~~~^^ File "/home/user/u-boot/./tools/dtoc/test_fdt", line 987, in main parser.add_argument('-T', '--test-coverage', action='store_true', ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ default=False, ^^^^^^^^^^^^^^ help='run tests and check for 100% coverage') ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/usr/lib64/python3.14/argparse.py", line 1562, in add_argument self._check_help(action) ~~~~~~~~~~~~~~~~^^^^^^^^ File "/usr/lib64/python3.14/argparse.py", line 1750, in _check_help raise ValueError('badly formed help string') from exc ValueError: badly formed help string Fixes: `7640b16660` ("test_fdt: Convert to use argparse") Signed-off-by: Francesco Valla <francesco@valla.it>	2026-06-07 16:42:50 +02:00
Tom Rini	969a1dde3a	doc: Update urllib3 version for building The GitHub dependabot tool has reported two "high" priority bug, CVE-2026-44431 and CVE-2026-44432, with this package. Update to the patched version. Reported-by: GitHub dependabot Signed-off-by: Tom Rini <trini@konsulko.com>	2026-06-07 16:41:27 +02:00