Prepare v2014.07

Signed-off-by: Tom Rini <trini@ti.com>

Makefile

@@ -8,7 +8,7 @@
 VERSION = 2014
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*
@@ -788,7 +788,8 @@ OBJCOPYFLAGS_u-boot.bin := -O binary
 binary_size_check: u-boot.bin System.map FORCE
 	@file_size=`stat -c %s u-boot.bin` ; \
 	map_size=$(shell cat System.map | \
-		awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print strtonum("0x" end) - strtonum("0x" start)}'); \
+		awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print "ibase=16; " toupper(end) " - " toupper(start)}' \
+		| bc); \
 	if [ "" != "$$map_size" ]; then \
 		if test $$map_size -ne $$file_size; then \
 			echo "System.map shows a binary size of $$map_size" >&2 ; \
@@ -1273,7 +1274,7 @@ $(mrproper-dirs):
 mrproper: clobber $(mrproper-dirs)
 	$(call cmd,rmdirs)
 	$(call cmd,rmfiles)
-	@rm -f arch/*/include/asm/arch arch/*/include/asm/proc
+	@rm -f arch/*/include/asm/arch
 
 # distclean
 #

README

@@ -2288,6 +2288,21 @@ CBFS (Coreboot Filesystem) support
 		    9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
 		    with a fix speed from 100000 and the slave addr 0!
 
+		- drivers/i2c/ihs_i2c.c
+		  - activate this driver with CONFIG_SYS_I2C_IHS
+		  - CONFIG_SYS_I2C_IHS_CH0 activate hardware channel 0
+		  - CONFIG_SYS_I2C_IHS_SPEED_0 speed channel 0
+		  - CONFIG_SYS_I2C_IHS_SLAVE_0 slave addr channel 0
+		  - CONFIG_SYS_I2C_IHS_CH1 activate hardware channel 1
+		  - CONFIG_SYS_I2C_IHS_SPEED_1 speed channel 1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_1 slave addr channel 1
+		  - CONFIG_SYS_I2C_IHS_CH2 activate hardware channel 2
+		  - CONFIG_SYS_I2C_IHS_SPEED_2 speed channel 2
+		  - CONFIG_SYS_I2C_IHS_SLAVE_2 slave addr channel 2
+		  - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
+		  - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
+		  - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+
 		additional defines:
 
 		CONFIG_SYS_NUM_I2C_BUSES
@@ -3254,6 +3269,11 @@ FIT uImage format:
 		disabled. If a board need legacy image format support
 		enable this through CONFIG_IMAGE_FORMAT_LEGACY
 
+		CONFIG_FIT_DISABLE_SHA256
+		Supporting SHA256 hashes has quite an impact on binary size.
+		For constrained systems sha256 hash support can be disabled
+		with this option.
+
 - Standalone program support:
 		CONFIG_STANDALONE_LOAD_ADDR
 
@@ -4069,6 +4089,43 @@ to save the current settings.
 	  environment area within the total memory of your DataFlash placed
 	  at the specified address.
 
+- CONFIG_ENV_IS_IN_SPI_FLASH:
+
+	Define this if you have a SPI Flash memory device which you
+	want to use for the environment.
+
+	- CONFIG_ENV_OFFSET:
+	- CONFIG_ENV_SIZE:
+
+	  These two #defines specify the offset and size of the
+	  environment area within the SPI Flash. CONFIG_ENV_OFFSET must be
+	  aligned to an erase sector boundary.
+
+	- CONFIG_ENV_SECT_SIZE:
+
+	  Define the SPI flash's sector size.
+
+	- CONFIG_ENV_OFFSET_REDUND (optional):
+
+	  This setting describes a second storage area of CONFIG_ENV_SIZE
+	  size used to hold a redundant copy of the environment data, so
+	  that there is a valid backup copy in case there is a power failure
+	  during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be
+	  aligned to an erase sector boundary.
+
+	- CONFIG_ENV_SPI_BUS (optional):
+	- CONFIG_ENV_SPI_CS (optional):
+
+	  Define the SPI bus and chip select. If not defined they will be 0.
+
+	- CONFIG_ENV_SPI_MAX_HZ (optional):
+
+	  Define the SPI max work clock. If not defined then use 1MHz.
+
+	- CONFIG_ENV_SPI_MODE (optional):
+
+	  Define the SPI work mode. If not defined then use SPI_MODE_3.
+
 - CONFIG_ENV_IS_IN_REMOTE:
 
 	Define this if you have a remote memory space which you
@@ -4156,6 +4213,37 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface.
 	  You will probably want to define these to avoid a really noisy system
 	  when storing the env in UBI.
 
+- CONFIG_ENV_IS_IN_FAT:
+       Define this if you want to use the FAT file system for the environment.
+
+       - FAT_ENV_INTERFACE:
+
+         Define this to a string that is the name of the block device.
+
+       - FAT_ENV_DEV_AND_PART:
+
+         Define this to a string to specify the partition of the device. It can
+         be as following:
+
+           "D:P", "D:0", "D", "D:" or "D:auto" (D, P are integers. And P >= 1)
+               - "D:P": device D partition P. Error occurs if device D has no
+                        partition table.
+               - "D:0": device D.
+               - "D" or "D:": device D partition 1 if device D has partition
+                              table, or the whole device D if has no partition
+                              table.
+               - "D:auto": first partition in device D with bootable flag set.
+                           If none, first valid paratition in device D. If no
+                           partition table then means device D.
+
+       - FAT_ENV_FILE:
+
+         It's a string of the FAT file name. This file use to store the
+         envrionment.
+
+       - CONFIG_FAT_WRITE:
+         This should be defined. Otherwise it cannot save the envrionment file.
+
 - CONFIG_ENV_IS_IN_MMC:
 
 	Define this if you have an MMC device which you want to use for the
@@ -4676,6 +4764,33 @@ within that device.
 	window->master inbound window->master LAW->the ucode address in
 	master's memory space.
 
+Freescale Layerscape Management Complex Firmware Support:
+---------------------------------------------------------
+The Freescale Layerscape Management Complex (MC) supports the loading of
+"firmware".
+This firmware often needs to be loaded during U-Boot booting, so macros
+are used to identify the storage device (NOR flash, SPI, etc) and the address
+within that device.
+
+- CONFIG_FSL_MC_ENET
+	Enable the MC driver for Layerscape SoCs.
+
+- CONFIG_SYS_LS_MC_FW_ADDR
+	The address in the storage device where the firmware is located.  The
+	meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro
+	is also specified.
+
+- CONFIG_SYS_LS_MC_FW_LENGTH
+	The maximum possible size of the firmware.  The firmware binary format
+	has a field that specifies the actual size of the firmware, but it
+	might not be possible to read any part of the firmware unless some
+	local storage is allocated to hold the entire firmware first.
+
+- CONFIG_SYS_LS_MC_FW_IN_NOR
+	Specifies that MC firmware is located in NOR flash, mapped as
+	normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the
+	virtual address in NOR flash.
+
 Building the Software:
 ======================
 

arch/arm/config.mk

@@ -116,6 +116,10 @@ else
 OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn
 endif
 
+ifdef CONFIG_OF_EMBED
+OBJCOPYFLAGS += -j .dtb.init.rodata
+endif
+
 ifneq ($(CONFIG_IMX_CONFIG),)
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD

arch/arm/cpu/arm720t/tegra-common/spl.c

@@ -15,7 +15,7 @@
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch/spl.h>
+#include <asm/spl.h>
 #include "cpu.h"
 
 void spl_board_init(void)

arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S

@@ -2,48 +2,457 @@
  * Low-level initialization for EP93xx
  *
  * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ * Copyright (C) 2013
+ * Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
  *
  * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
+ * Copyright (C) 2006 Cirrus Logic Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <version.h>
-#include <asm/arch/ep93xx.h>
+#include <config.h>
+#include <asm/arch-ep93xx/ep93xx.h>
+
+/*
+/* Configure the SDRAM based on the supplied settings.
+ *
+ * Input:	r0 - SDRAM DEVCFG register
+ *		r2 - configuration for SDRAM chips
+ * Output:	none
+ * Modifies:	r3, r4
+ */
+ep93xx_sdram_config:
+	/* Program the SDRAM device configuration register. */
+	ldr	r3, =SDRAM_BASE
+#ifdef CONFIG_EDB93XX_SDCS0
+	str	r0, [r3, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	str	r0, [r3, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	str	r0, [r3, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	str	r0, [r3, #SDRAM_OFF_DEVCFG3]
+#endif
+
+	/* Set the Initialize and MRS bits (issue continuous NOP commands
+	 * (INIT & MRS set))
+	 */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Delay for 200us. */
+	mov	r4, #0x3000
+delay1:
+	subs	r4, r4, #1
+	bne	delay1
+
+	/* Clear the MRS bit to issue a precharge all. */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Temporarily set the refresh timer to 0x10. Make it really low so
+	 * that refresh cycles are generated.
+	 */
+	ldr	r4, =0x10
+	str	r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Delay for at least 80 SDRAM clock cycles. */
+	mov	r4, #80
+delay2:
+	subs	r4, r4, #1
+	bne	delay2
+
+	/* Set the refresh timer to the fastest required for any device
+	 * that might be used. Set 9.6 ms refresh time.
+	 */
+	ldr	r4, =0x01e0
+	str	r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Select mode register update mode. */
+	ldr	r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
+			EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Program the mode register on the SDRAM by performing fake read */
+	ldr	r4, [r2]
+
+	/* Select normal operating mode. */
+	ldr	r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
+	str	r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+/*
+ * Test to see if the SDRAM has been configured in a usable mode.
+ *
+ * Input:	r0 - Test address of SDRAM
+ * Output:	r0 - 0 -- Test OK, -1 -- Failed
+ * Modifies:	r0-r5
+ */
+ep93xx_sdram_test:
+	/* Load the test patterns to be written to SDRAM. */
+	ldr	r1, =0xf00dface
+	ldr	r2, =0xdeadbeef
+	ldr	r3, =0x08675309
+	ldr	r4, =0xdeafc0ed
+
+	/* Store the test patterns to SDRAM. */
+	stmia	r0, {r1-r4}
+
+	/* Load the test patterns from SDRAM one at a time and compare them
+	 * to the actual pattern.
+	 */
+	ldr	r5, [r0]
+	cmp	r5, r1
+	ldreq	r5, [r0, #0x0004]
+	cmpeq	r5, r2
+	ldreq	r5, [r0, #0x0008]
+	cmpeq	r5, r3
+	ldreq	r5, [r0, #0x000c]
+	cmpeq	r5, r4
+
+	/* Return -1 if a mismatch was encountered, 0 otherwise. */
+	mvnne	r0, #0xffffffff
+	moveq	r0, #0x00000000
+
+	/* Return to the caller. */
+	mov	pc, lr
+
+/*
+ * Determine the size of the SDRAM. Use data=address for the scan.
+ *
+ * Input:	r0 - Start SDRAM address
+ * Return:	r0 - Single block size
+ *		r1 - Valid block mask
+ *		r2 - Total block count
+ * Modifies:	r0-r5
+ */
+ep93xx_sdram_size:
+	/* Store zero at offset zero. */
+	str	r0, [r0]
+
+	/* Start checking for an alias at 1MB into SDRAM. */
+	ldr	r1, =0x00100000
+
+	/* Store the offset at the current offset. */
+check_block_size:
+	str	r1, [r0, r1]
+
+	/* Read back from zero. */
+	ldr	r2, [r0]
+
+	/* Stop searching of an alias was found. */
+	cmp	r1, r2
+	beq	found_block_size
+
+	/* Advance to the next power of two boundary. */
+	mov	r1, r1, lsl #1
+
+	/* Loop back if the size has not reached 256MB. */
+	cmp	r1, #0x10000000
+	bne	check_block_size
+
+	/* A full 256MB of memory was found, so return it now. */
+	ldr	r0, =0x10000000
+	ldr	r1, =0x00000000
+	ldr	r2, =0x00000001
+	mov	pc, lr
+
+	/* An alias was found. See if the first block is 128MB in size. */
+found_block_size:
+	cmp	r1, #0x08000000
+
+	/* The first block is 128MB, so there is no further memory. Return it
+	 * now.
+	 */
+	ldreq	r0, =0x08000000
+	ldreq	r1, =0x00000000
+	ldreq	r2, =0x00000001
+	moveq	pc, lr
+
+	/* Save the block size, set the block address bits to zero, and
+	 * initialize the block count to one.
+	 */
+	mov	r3, r1
+	ldr	r4, =0x00000000
+	ldr	r5, =0x00000001
+
+	/* Look for additional blocks of memory by searching for non-aliases. */
+find_blocks:
+	/* Store zero back to address zero. It may be overwritten. */
+	str	r0, [r0]
+
+	/* Advance to the next power of two boundary. */
+	mov	r1, r1, lsl #1
+
+	/* Store the offset at the current offset. */
+	str	r1, [r0, r1]
+
+	/* Read back from zero. */
+	ldr	r2, [r0]
+
+	/* See if a non-alias was found. */
+	cmp	r1, r2
+
+	/* If a non-alias was found, then or in the block address bit and
+	 * multiply the block count by two (since there are two unique
+	 * blocks, one with this bit zero and one with it one).
+	 */
+	orrne	r4, r4, r1
+	movne	r5, r5, lsl #1
+
+	/* Continue searching if there are more address bits to check. */
+	cmp	r1, #0x08000000
+	bne	find_blocks
+
+	/* Return the block size, address mask, and count. */
+	mov	r0, r3
+	mov	r1, r4
+	mov	r2, r5
+
+	/* Return to the caller. */
+	mov	pc, lr
+
 
 .globl lowlevel_init
 lowlevel_init:
-	/* backup return address */
-	ldr r1, =SYSCON_SCRATCH0
-	str lr, [r1]
 
-	/* Turn on both LEDs */
-	bl red_led_on
-	bl green_led_on
+	mov	r6, lr
 
-	/* Configure flash wait states before we switch to the PLL */
-	bl flash_cfg
+	/* Make sure caches are off and invalidated. */
+	ldr	r0, =0x00000000
+	mcr	p15, 0, r0, c1, c0, 0
+	nop
+	nop
+	nop
+	nop
+	nop
 
-	/* Set up PLL */
-	bl pll_cfg
+	/* Turn off the green LED and turn on the red LED. If the red LED
+	 * is left on for too long, the external reset circuit described
+	 * by application note AN258 will cause the system to reset.
+	 */
+	ldr	r1, =EP93XX_LED_DATA
+	ldr	r0, [r1]
+	bic	r0, r0, #EP93XX_LED_GREEN_ON
+	orr	r0, r0, #EP93XX_LED_RED_ON
+	str	r0, [r1]
 
-	/* Turn off the Green LED and leave the Red LED on */
-	bl green_led_off
+	/* Undo the silly static memory controller programming performed
+	 * by the boot rom.
+	 */
+	ldr	r0, =SMC_BASE
 
-	/* Setup SDRAM */
-	bl sdram_cfg
+	/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
+	ldr	r1, =0x0000fbe0
 
-	/* Turn on Green LED, Turn off the Red LED */
-	bl green_led_on
-	bl red_led_off
+	/* Reset EP93XX_OFF_SMCBCR0 */
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
 
-	/* FIXME: we use async mode for now */
-	mrc p15, 0, r0, c1, c0, 0
-	orr r0, r0, #0xc0000000
-	mcr p15, 0, r0, c1, c0, 0
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR1]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR1]
 
-	/* restore return address */
-	ldr r1, =SYSCON_SCRATCH0
-	ldr lr, [r1]
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR2]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR2]
 
-	mov pc, lr
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR3]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR3]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR6]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR6]
+
+	ldr	r2, [r0, #EP93XX_OFF_SMCBCR7]
+	orr	r2, r2, r1
+	str	r2, [r0, #EP93XX_OFF_SMCBCR7]
+
+	/* Set the PLL1 and processor clock. */
+	ldr	r0, =SYSCON_BASE
+#ifdef CONFIG_EDB9301
+	/* 332MHz, giving a 166MHz processor clock. */
+	ldr	r1, = 0x02b49907
+#else
+
+#ifdef CONFIG_EDB93XX_INDUSTRIAL
+	/* 384MHz, giving a 196MHz processor clock. */
+	ldr	r1, =0x02a4bb38
+#else
+	/* 400MHz, giving a 200MHz processor clock. */
+	ldr	r1, =0x02a4e39e
+#endif
+#endif
+	str	r1, [r0, #SYSCON_OFF_CLKSET1]
+
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* Need to make sure that SDRAM is configured correctly before
+	 * coping the code into it.
+	 */
+
+#ifdef CONFIG_EDB93XX_SDCS0
+	mov	r11, #SDRAM_DEVCFG0_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	mov	r11, #SDRAM_DEVCFG1_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	mov	r11, #SDRAM_DEVCFG2_BASE
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	ldr	r0, =SYSCON_BASE
+	ldr	r0, [r0, #SYSCON_OFF_SYSCFG]
+	ands	r0, r0, #SYSCON_SYSCFG_LASDO
+	moveq	r11, #SDRAM_DEVCFG3_ASD0_BASE
+	movne	r11, #SDRAM_DEVCFG3_ASD1_BASE
+#endif
+	/* See Table 13-5 in EP93xx datasheet for more info about DRAM
+	 * register mapping */
+
+	/* Try a 32-bit wide configuration of SDRAM. */
+	ldr	r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+			EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+			EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
+
+	/* Set burst count: 4 and CAS: 2
+	 * Burst mode [A11:A10]; CAS [A16:A14]
+	 */
+	orr	r2, r11, #0x00008800
+	bl	ep93xx_sdram_config
+
+	/* Test the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_test
+	cmp	r0, #0x00000000
+	beq	ep93xx_sdram_done
+
+	/* Try a 16-bit wide configuration of SDRAM. */
+	ldr	r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
+			EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
+			EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
+			EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
+
+	/* Set burst count: 8, CAS: 2, sequential burst
+	 * Accoring to Table 13-3 for 16bit operations mapping must be shifted.
+	 * Burst mode [A10:A9]; CAS [A15:A13]
+	 */
+	orr	r2, r11, #0x00004600
+	bl	ep93xx_sdram_config
+
+	/* Test the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_test
+	cmp	r0, #0x00000000
+	beq	ep93xx_sdram_done
+
+	/* Turn off the red LED. */
+	ldr	r0, =EP93XX_LED_DATA
+	ldr	r1, [r0]
+	bic	r1, r1, #EP93XX_LED_RED_ON
+	str	r1, [r0]
+
+	/* There is no SDRAM so flash the green LED. */
+flash_green:
+	orr	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_1:
+	subs	r2, r2, #1
+	bne	flash_green_delay_1
+	bic	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_2:
+	subs	r2, r2, #1
+	bne	flash_green_delay_2
+	orr	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00010000
+flash_green_delay_3:
+	subs	r2, r2, #1
+	bne	flash_green_delay_3
+	bic	r1, r1, #EP93XX_LED_GREEN_ON
+	str	r1, [r0]
+	ldr	r2, =0x00050000
+flash_green_delay_4:
+	subs	r2, r2, #1
+	bne	flash_green_delay_4
+	b	flash_green
+
+
+ep93xx_sdram_done:
+	ldr	r1, =EP93XX_LED_DATA
+	ldr	r0, [r1]
+	bic	r0, r0, #EP93XX_LED_RED_ON
+	str	r0, [r1]
+
+	/* Determine the size of the SDRAM. */
+	mov	r0, r11
+	bl	ep93xx_sdram_size
+
+	/* Save the SDRAM characteristics. */
+	mov	r8, r0
+	mov	r9, r1
+	mov	r10, r2
+
+	/* Compute total memory size into r1 */
+	mul	r1, r8, r10
+#ifdef CONFIG_EDB93XX_SDCS0
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+	ldr	r2, [r0, #SDRAM_OFF_DEVCFG3]
+#endif
+
+	/* Consider small DRAM size as:
+	 * < 32Mb for 32bit bus
+	 * < 64Mb for 16bit bus
+	 */
+	tst	r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
+	moveq	r1, r1, lsr #1
+	cmp	r1, #0x02000000
+
+#if defined(CONFIG_EDB9301)
+	/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
+	movlt	r1, #0x03f0
+	movge	r1, #0x01e0
+#else
+	/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
+	movlt	r1, #0x0600
+	movge	r1, #0x2f0
+#endif
+	str	r1, [r0, #SDRAM_OFF_REFRSHTIMR]
+
+	/* Save the memory configuration information. */
+	orr	r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
+	stmia	r0, {r8-r11}
+
+	mov	lr, r6
+	mov	pc, lr

arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c

@@ -14,7 +14,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/davinci_misc.h>
 #include <asm/arch/ddr2_defs.h>
-#include <asm/arch/emif_defs.h>
+#include <asm/ti-common/davinci_nand.h>
 #include <asm/arch/pll_defs.h>
 
 void davinci_enable_uart0(void)

arch/arm/cpu/arm926ejs/davinci/dm365_lowlevel.c

@@ -11,6 +11,7 @@
 #include <nand.h>
 #include <ns16550.h>
 #include <post.h>
+#include <asm/ti-common/davinci_nand.h>
 #include <asm/arch/dm365_lowlevel.h>
 #include <asm/arch/hardware.h>
 

arch/arm/cpu/armv7/am33xx/ddr.c

@@ -94,7 +94,20 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
 	writel(regs->emif_rd_wr_exec_thresh,
 	       &emif_reg[nr]->emif_rd_wr_exec_thresh);
 
+	/*
+	 * for most SOCs these registers won't need to be changed so only
+	 * write to these registers if someone explicitly has set the
+	 * register's value.
+	 */
+	if(regs->emif_cos_config) {
+		writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
+		writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
+		writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
+		writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
+	}
+
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 	writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 

arch/arm/cpu/armv7/am33xx/emif4.c

@@ -115,7 +115,7 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 #endif
 #ifdef CONFIG_AM43XX
 	writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
-	while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+	while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
 		;
 	writel(0x80000000, &ddrctrl->ddrioctrl);
 

arch/arm/cpu/armv7/at91/cpu.c

@@ -61,6 +61,8 @@ int print_cpuinfo(void)
 
 void enable_caches(void)
 {
+	icache_enable();
+	dcache_enable();
 }
 
 unsigned int get_chip_id(void)

arch/arm/cpu/armv7/cache_v7.c

@@ -354,41 +354,10 @@ void invalidate_icache_all(void)
 }
 #endif
 
-/*
- * Stub implementations for outer cache operations
- */
-void __v7_outer_cache_enable(void)
-{
-}
-void v7_outer_cache_enable(void)
-	__attribute__((weak, alias("__v7_outer_cache_enable")));
-
-void __v7_outer_cache_disable(void)
-{
-}
-void v7_outer_cache_disable(void)
-	__attribute__((weak, alias("__v7_outer_cache_disable")));
-
-void __v7_outer_cache_flush_all(void)
-{
-}
-void v7_outer_cache_flush_all(void)
-	__attribute__((weak, alias("__v7_outer_cache_flush_all")));
-
-void __v7_outer_cache_inval_all(void)
-{
-}
-void v7_outer_cache_inval_all(void)
-	__attribute__((weak, alias("__v7_outer_cache_inval_all")));
-
-void __v7_outer_cache_flush_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_flush_range(u32 start, u32 end)
-	__attribute__((weak, alias("__v7_outer_cache_flush_range")));
-
-void __v7_outer_cache_inval_range(u32 start, u32 end)
-{
-}
-void v7_outer_cache_inval_range(u32 start, u32 end)
-	__attribute__((weak, alias("__v7_outer_cache_inval_range")));
+/*  Stub implementations for outer cache operations */
+__weak void v7_outer_cache_enable(void) {}
+__weak void v7_outer_cache_disable(void) {}
+__weak void v7_outer_cache_flush_all(void) {}
+__weak void v7_outer_cache_inval_all(void) {}
+__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
+__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}

arch/arm/cpu/armv7/exynos/dmc_common.c

@@ -162,7 +162,7 @@ void mem_ctrl_init(int reset)
 
 	/* If there are any other memory variant, add their init call below */
 	if (param->mem_type == DDR_MODE_DDR3) {
-		ret = ddr3_mem_ctrl_init(mem, param->mem_iv_size, reset);
+		ret = ddr3_mem_ctrl_init(mem, reset);
 		if (ret) {
 			/* will hang if failed to init memory control */
 			while (1)

arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c

@@ -6,6 +6,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -16,7 +17,11 @@
 #include "exynos5_setup.h"
 #include "clock_init.h"
 
-#define TIMEOUT	10000
+#define TIMEOUT_US		10000
+#define NUM_BYTE_LANES		4
+#define DEFAULT_DQS		8
+#define DEFAULT_DQS_X4		(DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
+				|| (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)
 
 #ifdef CONFIG_EXYNOS5250
 static void reset_phy_ctrl(void)
@@ -28,8 +33,7 @@ static void reset_phy_ctrl(void)
 	writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
 }
 
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-		       int reset)
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 {
 	unsigned int val;
 	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@@ -177,7 +181,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(val, &phy1_ctrl->phy_con1);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
-		i = TIMEOUT;
+		i = TIMEOUT_US;
 		while ((readl(&dmc->phystatus) &
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
@@ -221,8 +225,220 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 #endif
 
 #ifdef CONFIG_EXYNOS5420
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-		       int reset)
+/**
+ * RAM address to use in the test.
+ *
+ * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
+ * interleaves channels every 128 bytes).  This will allow us to evaluate all of
+ * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
+ * chip per channel (4GB) system.  We can't test the 2nd chip since we need to
+ * do tests before the 2nd chip is enabled.  Looking at the 2nd chip isn't
+ * critical because the 1st and 2nd chip have very similar timings (they'd
+ * better have similar timings, since there's only a single adjustment that is
+ * shared by both chips).
+ */
+const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
+
+/* Test pattern with which RAM will be tested */
+static const unsigned int test_pattern[] = {
+	0x5a5a5a5a,
+	0xa5a5a5a5,
+	0xf0f0f0f0,
+	0x0f0f0f0f,
+};
+
+/**
+ * This function is a test vector for sw read leveling,
+ * it compares the read data with the written data.
+ *
+ * @param ch			DMC channel number
+ * @param byte_lane		which DQS byte offset,
+ *				possible values are 0,1,2,3
+ * @return			TRUE if memory was good, FALSE if not.
+ */
+static bool dmc_valid_window_test_vector(int ch, int byte_lane)
+{
+	unsigned int read_data;
+	unsigned int mask;
+	int i;
+
+	mask = 0xFF << (8 * byte_lane);
+
+	for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
+		read_data = readl(test_addr + i * 4 + ch * 0x80);
+		if ((read_data & mask) != (test_pattern[i] & mask))
+			return false;
+	}
+
+	return true;
+}
+
+/**
+ * This function returns current read offset value.
+ *
+ * @param phy_ctrl	pointer to the current phy controller
+ */
+static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
+					       *phy_ctrl)
+{
+	return readl(&phy_ctrl->phy_con4);
+}
+
+/**
+ * This function performs resync, so that slave DLL is updated.
+ *
+ * @param phy_ctrl	pointer to the current phy controller
+ */
+static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
+{
+	setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
+	clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
+}
+
+/**
+ * This function sets read offset value register with 'offset'.
+ *
+ * ...we also call call ddr_phy_set_do_resync().
+ *
+ * @param phy_ctrl	pointer to the current phy controller
+ * @param offset	offset to read DQS
+ */
+static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
+				      unsigned int offset)
+{
+	writel(offset, &phy_ctrl->phy_con4);
+	ddr_phy_set_do_resync(phy_ctrl);
+}
+
+/**
+ * Convert a 2s complement byte to a byte with a sign bit.
+ *
+ * NOTE: you shouldn't use normal math on the number returned by this function.
+ *   As an example, -10 = 0xf6.  After this function -10 = 0x8a.  If you wanted
+ *   to do math and get the average of 10 and -10 (should be 0):
+ *     0x8a + 0xa = 0x94 (-108)
+ *     0x94 / 2   = 0xca (-54)
+ *   ...and 0xca = sign bit plus 0x4a, or -74
+ *
+ * Also note that you lose the ability to represent -128 since there are two
+ * representations of 0.
+ *
+ * @param b	The byte to convert in two's complement.
+ * @return	The 7-bit value + sign bit.
+ */
+
+unsigned char make_signed_byte(signed char b)
+{
+	if (b < 0)
+		return 0x80 | -b;
+	else
+		return b;
+}
+
+/**
+ * Test various shifts starting at 'start' and going to 'end'.
+ *
+ * For each byte lane, we'll walk through shift starting at 'start' and going
+ * to 'end' (inclusive).  When we are finally able to read the test pattern
+ * we'll store the value in the results array.
+ *
+ * @param phy_ctrl		pointer to the current phy controller
+ * @param ch			channel number
+ * @param start			the start shift.  -127 to 127
+ * @param end			the end shift.  -127 to 127
+ * @param results		we'll store results for each byte lane.
+ */
+
+void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
+		 int start, int end, int results[NUM_BYTE_LANES])
+{
+	int incr = (start < end) ? 1 : -1;
+	int byte_lane;
+
+	for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
+		int shift;
+
+		dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
+		results[byte_lane] = DEFAULT_DQS;
+
+		for (shift = start; shift != (end + incr); shift += incr) {
+			unsigned int byte_offsetr;
+			unsigned int offsetr;
+
+			byte_offsetr = make_signed_byte(shift);
+
+			offsetr = dmc_get_read_offset_value(phy_ctrl);
+			offsetr &= ~(0xFF << (8 * byte_lane));
+			offsetr |= (byte_offsetr << (8 * byte_lane));
+			dmc_set_read_offset_value(phy_ctrl, offsetr);
+
+			if (dmc_valid_window_test_vector(ch, byte_lane)) {
+				results[byte_lane] = shift;
+				break;
+			}
+		}
+	}
+}
+
+/**
+ * This function performs SW read leveling to compensate DQ-DQS skew at
+ * receiver it first finds the optimal read offset value on each DQS
+ * then applies the value to PHY.
+ *
+ * Read offset value has its min margin and max margin. If read offset
+ * value exceeds its min or max margin, read data will have corruption.
+ * To avoid this we are doing sw read leveling.
+ *
+ * SW read leveling is:
+ * 1> Finding offset value's left_limit and right_limit
+ * 2> and calculate its center value
+ * 3> finally programs that center value to PHY
+ * 4> then PHY gets its optimal offset value.
+ *
+ * @param phy_ctrl		pointer to the current phy controller
+ * @param ch			channel number
+ * @param coarse_lock_val	The coarse lock value read from PHY_CON13.
+ *				(0 - 0x7f)
+ */
+static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
+				      int ch, unsigned int coarse_lock_val)
+{
+	unsigned int offsetr_cent;
+	int byte_lane;
+	int left_limit;
+	int right_limit;
+	int left[NUM_BYTE_LANES];
+	int right[NUM_BYTE_LANES];
+	int i;
+
+	/* Fill the memory with test patterns */
+	for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
+		writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
+
+	/* Figure out the limits we'll test with; keep -127 < limit < 127 */
+	left_limit = DEFAULT_DQS - coarse_lock_val;
+	right_limit = DEFAULT_DQS + coarse_lock_val;
+	if (right_limit > 127)
+		right_limit = 127;
+
+	/* Fill in the location where reads were OK from left and right */
+	test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
+	test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
+
+	/* Make a final value by taking the center between the left and right */
+	offsetr_cent = 0;
+	for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
+		int temp_center;
+		unsigned int vmwc;
+
+		temp_center = (left[byte_lane] + right[byte_lane]) / 2;
+		vmwc = make_signed_byte(temp_center);
+		offsetr_cent |= vmwc << (8 * byte_lane);
+	}
+	dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
+}
+
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 {
 	struct exynos5420_clock *clk =
 		(struct exynos5420_clock *)samsung_get_base_clock();
@@ -231,7 +447,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
 	struct exynos5420_dmc *drex0, *drex1;
 	struct exynos5420_tzasc *tzasc0, *tzasc1;
+	struct exynos5_power *pmu;
 	uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
+	uint32_t lock0_info, lock1_info;
 	int chip;
 	int i;
 
@@ -244,6 +462,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
 	tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
 							+ DMC_OFFSET);
+	pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
 
 	/* Enable PAUSE for DREX */
 	setbits_le32(&clk->pause, ENABLE_BIT);
@@ -394,7 +613,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		 */
 		dmc_config_mrs(mem, &drex0->directcmd);
 		dmc_config_mrs(mem, &drex1->directcmd);
-	} else {
+	}
+
+	/*
+	 * Get PHY_CON13 from both phys.  Gate CLKM around reading since
+	 * PHY_CON13 is glitchy when CLKM is running.  We're paranoid and
+	 * wait until we get a "fine lock", though a coarse lock is probably
+	 * OK (we only use the coarse numbers below).  We try to gate the
+	 * clock for as short a time as possible in case SDRAM is somehow
+	 * sensitive.  sdelay(10) in the loop is arbitrary to make sure
+	 * there is some time for PHY_CON13 to get updated.  In practice
+	 * no delay appears to be needed.
+	 */
+	val = readl(&clk->gate_bus_cdrex);
+	while (true) {
+		writel(val & ~0x1, &clk->gate_bus_cdrex);
+		lock0_info = readl(&phy0_ctrl->phy_con13);
+		writel(val, &clk->gate_bus_cdrex);
+
+		if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
+			break;
+
+		sdelay(10);
+	}
+	while (true) {
+		writel(val & ~0x2, &clk->gate_bus_cdrex);
+		lock1_info = readl(&phy1_ctrl->phy_con13);
+		writel(val, &clk->gate_bus_cdrex);
+
+		if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
+			break;
+
+		sdelay(10);
+	}
+
+	if (!reset) {
 		/*
 		 * During Suspend-Resume & S/W-Reset, as soon as PMU releases
 		 * pad retention, CKE goes high. This causes memory contents
@@ -445,15 +698,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
 		writel(val, &phy1_ctrl->phy_con1);
 
-		n_lock_r = readl(&phy0_ctrl->phy_con13);
-		n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
 		n_lock_r = readl(&phy0_ctrl->phy_con12);
 		n_lock_r &= ~CTRL_DLL_ON;
 		n_lock_r |= n_lock_w_phy0;
 		writel(n_lock_r, &phy0_ctrl->phy_con12);
 
-		n_lock_r = readl(&phy1_ctrl->phy_con13);
-		n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2;
+		n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
 		n_lock_r = readl(&phy1_ctrl->phy_con12);
 		n_lock_r &= ~CTRL_DLL_ON;
 		n_lock_r |= n_lock_w_phy1;
@@ -482,7 +733,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(val, &phy1_ctrl->phy_con1);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
-		i = TIMEOUT;
+		i = TIMEOUT_US;
 		while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
 			RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
@@ -497,7 +748,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
 
 		writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
-		i = TIMEOUT;
+		i = TIMEOUT_US;
 		while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
 			RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
@@ -522,77 +773,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			       &drex1->directcmd);
 		}
 
-		if (mem->read_leveling_enable) {
-			/* Set Read DQ Calibration */
-			val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
-			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex0->directcmd);
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex1->directcmd);
-			}
-
-			val = readl(&phy0_ctrl->phy_con1);
-			val |= READ_LEVELLING_DDR3;
-			writel(val, &phy0_ctrl->phy_con1);
-			val = readl(&phy1_ctrl->phy_con1);
-			val |= READ_LEVELLING_DDR3;
-			writel(val, &phy1_ctrl->phy_con1);
-
-			val = readl(&phy0_ctrl->phy_con2);
-			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
-			writel(val, &phy0_ctrl->phy_con2);
-			val = readl(&phy1_ctrl->phy_con2);
-			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
-			writel(val, &phy1_ctrl->phy_con2);
-
-			setbits_le32(&drex0->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			i = TIMEOUT;
-			while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
-				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
-				/*
-				 * TODO(waihong): Comment on how long this take
-				 * to timeout
-				 */
-				sdelay(100);
-				i--;
-			}
-			if (!i)
-				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-
-			clrbits_le32(&drex0->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			setbits_le32(&drex1->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			i = TIMEOUT;
-			while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
-				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
-				/*
-				 * TODO(waihong): Comment on how long this take
-				 * to timeout
-				 */
-				sdelay(100);
-				i--;
-			}
-			if (!i)
-				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-
-			clrbits_le32(&drex1->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-
-			val = (0x3 << DIRECT_CMD_BANK_SHIFT);
-			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex0->directcmd);
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex1->directcmd);
-			}
-
-			update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
-			update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
-		}
-
 		/* Common Settings for Leveling */
 		val = PHY_CON12_RESET_VAL;
 		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
@@ -602,6 +782,27 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
 	}
 
+	/*
+	 * Do software read leveling
+	 *
+	 * Do this before we turn on auto refresh since the auto refresh can
+	 * be in conflict with the resync operation that's part of setting
+	 * read leveling.
+	 */
+	if (!reset) {
+		/* restore calibrated value after resume */
+		dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
+		dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
+	} else {
+		software_find_read_offset(phy0_ctrl, 0,
+					  CTRL_LOCK_COARSE(lock0_info));
+		software_find_read_offset(phy1_ctrl, 1,
+					  CTRL_LOCK_COARSE(lock1_info));
+		/* save calibrated value to restore after resume */
+		writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
+		writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
+	}
+
 	/* Send PALL command */
 	dmc_config_prech(mem, &drex0->directcmd);
 	dmc_config_prech(mem, &drex1->directcmd);

arch/arm/cpu/armv7/exynos/exynos5_setup.h

@@ -282,8 +282,12 @@
 #define PHY_CON12_VAL		0x10107F50
 #define CTRL_START		(1 << 6)
 #define CTRL_DLL_ON		(1 << 5)
+#define CTRL_LOCK_COARSE_OFFSET	10
+#define CTRL_LOCK_COARSE_MASK	(0x7F << CTRL_LOCK_COARSE_OFFSET)
+#define CTRL_LOCK_COARSE(x)	(((x) & CTRL_LOCK_COARSE_MASK) >> \
+				 CTRL_LOCK_COARSE_OFFSET)
 #define CTRL_FORCE_MASK		(0x7F << 8)
-#define CTRL_LOCK_COARSE_MASK	(0x7F << 10)
+#define CTRL_FINE_LOCKED	0x7
 
 #define CTRL_OFFSETD_RESET_VAL	0x8
 #define CTRL_OFFSETD_VAL	0x7F
@@ -431,10 +435,10 @@
 
 /*
  * Definitions that differ with SoC's.
- * Below is the part defining macros for smdk5250.
- * Else part introduces macros for smdk5420.
+ * Below is the part defining macros for Exynos5250.
+ * Else part introduces macros for Exynos5420.
  */
-#ifndef CONFIG_SMDK5420
+#ifndef CONFIG_EXYNOS5420
 
 /* APLL_CON1 */
 #define APLL_CON1_VAL	(0x00203800)
@@ -890,16 +894,11 @@ enum {
 /*
  * Memory variant specific initialization code for DDR3
  *
- * @param mem		Memory timings for this memory type.
- * @param mem_iv_size	Memory interleaving size is a configurable parameter
- *			which the DMC uses to decide how to split a memory
- *			chunk into smaller chunks to support concurrent
- *			accesses; may vary across boards.
+ * @param mem          Memory timings for this memory type.
  * @param reset         Reset DDR PHY during initialization.
  * @return 0 if ok, SETUP_ERR_... if there is a problem
  */
-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
-			int reset);
+int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset);
 
 /* Memory variant specific initialization code for LPDDR3 */
 void lpddr3_mem_ctrl_init(void);

arch/arm/cpu/armv7/exynos/lowlevel_init.c

@@ -49,8 +49,6 @@ int do_lowlevel_init(void)
 
 	arch_cpu_init();
 
-	set_ps_hold_ctrl();
-
 	reset_status = get_reset_status();
 
 	switch (reset_status) {

arch/arm/cpu/armv7/keystone/Makefile

@@ -5,7 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y	+= aemif.o
 obj-y	+= init.o
 obj-y	+= psc.o
 obj-y	+= clock.o

arch/arm/cpu/armv7/mx6/Makefile

@@ -8,4 +8,5 @@
 #
 
 obj-y	:= soc.o clock.o
+obj-$(CONFIG_SPL_BUILD)	     += ddr.o
 obj-$(CONFIG_SECURE_BOOT)    += hab.o

arch/arm/cpu/armv7/mx6/clock.c

@@ -80,7 +80,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 		div = __raw_readl(&imx_ccm->analog_pll_sys);
 		div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
 
-		return infreq * (div >> 1);
+		return (infreq * div) >> 1;
 	case PLL_BUS:
 		div = __raw_readl(&imx_ccm->analog_pll_528);
 		div &= BM_ANADIG_PLL_528_DIV_SELECT;

arch/arm/cpu/armv7/mx6/ddr.c

@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+		      const struct mx6dq_iomux_ddr_regs *ddr,
+		      const struct mx6dq_iomux_grp_regs *grp)
+{
+	volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+	volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+	mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+	mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+	/* DDR IO Type */
+	mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+	mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+	/* Clock */
+	mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+	mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+	/* Address */
+	mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+	mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+	mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+	/* Control */
+	mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+	mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+	mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+	mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+	mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+	mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+	mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+	/* Data Strobes */
+	mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+	mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+	mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+	if (width >= 32) {
+		mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+		mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+	}
+	if (width >= 64) {
+		mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+		mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+		mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+		mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+	}
+
+	/* Data */
+	mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+	mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+	mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+	if (width >= 32) {
+		mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+		mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+	}
+	if (width >= 64) {
+		mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+		mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+		mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+		mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+	}
+	mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+	mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+	if (width >= 32) {
+		mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+		mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+	}
+	if (width >= 64) {
+		mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+		mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+		mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+		mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+	}
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+		       const struct mx6sdl_iomux_ddr_regs *ddr,
+		       const struct mx6sdl_iomux_grp_regs *grp)
+{
+	volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
+	volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
+
+	mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
+	mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
+
+	/* DDR IO Type */
+	mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+	mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+	/* Clock */
+	mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+	mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+	/* Address */
+	mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+	mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+	mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+	/* Control */
+	mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+	mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+	mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+	mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+	mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+	mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+	mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+	/* Data Strobes */
+	mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+	mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+	mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+	if (width >= 32) {
+		mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+		mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+	}
+	if (width >= 64) {
+		mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+		mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+		mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+		mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+	}
+
+	/* Data */
+	mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+	mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+	mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+	if (width >= 32) {
+		mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+		mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+	}
+	if (width >= 64) {
+		mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+		mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+		mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+		mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+	}
+	mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+	mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+	if (width >= 32) {
+		mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+		mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+	}
+	if (width >= 64) {
+		mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+		mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+		mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+		mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+	}
+}
+#endif
+
+/*
+ * Configure mx6 mmdc registers based on:
+ *  - board-specific memory configuration
+ *  - board-specific calibration data
+ *  - ddr3 chip details
+ *
+ * The various calculations here are derived from the Freescale
+ * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
+ * configuration registers based on memory system and memory chip parameters.
+ *
+ * The defaults here are those which were specified in the spreadsheet.
+ * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
+ * section titled MMDC initialization
+ */
+#define MR(val, ba, cmd, cs1) \
+	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
+		  const struct mx6_mmdc_calibration *c,
+		  const struct mx6_ddr3_cfg *m)
+{
+	volatile struct mmdc_p_regs *mmdc0;
+	volatile struct mmdc_p_regs *mmdc1;
+	u32 reg;
+	u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+	u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
+	u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
+	u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
+	u16 CS0_END;
+	u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
+	int clkper; /* clock period in picoseconds */
+	int clock; /* clock freq in mHz */
+	int cs;
+
+	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+	mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+	/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+		clock = 528;
+		tcwl = 4;
+	}
+	/* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+	else {
+		clock = 400;
+		tcwl = 3;
+	}
+	clkper = (1000*1000)/clock; /* ps */
+	todtlon = tcwl;
+	taxpd = tcwl;
+	tanpd = tcwl;
+	tcwl = tcwl;
+
+	switch (m->density) {
+	case 1: /* 1Gb per chip */
+		trfc = DIV_ROUND_UP(110000, clkper) - 1;
+		txs = DIV_ROUND_UP(120000, clkper) - 1;
+		break;
+	case 2: /* 2Gb per chip */
+		trfc = DIV_ROUND_UP(160000, clkper) - 1;
+		txs = DIV_ROUND_UP(170000, clkper) - 1;
+		break;
+	case 4: /* 4Gb per chip */
+		trfc = DIV_ROUND_UP(260000, clkper) - 1;
+		txs = DIV_ROUND_UP(270000, clkper) - 1;
+		break;
+	case 8: /* 8Gb per chip */
+		trfc = DIV_ROUND_UP(350000, clkper) - 1;
+		txs = DIV_ROUND_UP(360000, clkper) - 1;
+		break;
+	default:
+		/* invalid density */
+		printf("invalid chip density\n");
+		hang();
+		break;
+	}
+	txpr = txs;
+
+	switch (m->mem_speed) {
+	case 800:
+		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+		if (m->pagesz == 1) {
+			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+		} else {
+			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+		}
+		break;
+	case 1066:
+		txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
+		if (m->pagesz == 1) {
+			tfaw = DIV_ROUND_UP(37500, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+		} else {
+			tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+		}
+		break;
+	case 1333:
+		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
+		if (m->pagesz == 1) {
+			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+		} else {
+			tfaw = DIV_ROUND_UP(45000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+		}
+		break;
+	case 1600:
+		txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
+		tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
+		if (m->pagesz == 1) {
+			tfaw = DIV_ROUND_UP(30000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+		} else {
+			tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+			trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+		}
+		break;
+	default:
+		printf("invalid memory speed\n");
+		hang();
+		break;
+	}
+	txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
+	tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
+	tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
+	tcksrx = tcksre;
+	taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+	taofpd = taonpd;
+	trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+	trcd = trp;
+	trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
+	tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
+	twr = DIV_ROUND_UP(15000, clkper) - 1;
+	tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
+	twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
+	trtp = twtr;
+	CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
+	debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+	debug("clock: %dMHz (%d ps)\n", clock, clkper);
+	debug("memspd:%d\n", m->mem_speed);
+	debug("tcke=%d\n", tcke);
+	debug("tcksrx=%d\n", tcksrx);
+	debug("tcksre=%d\n", tcksre);
+	debug("taofpd=%d\n", taofpd);
+	debug("taonpd=%d\n", taonpd);
+	debug("todtlon=%d\n", todtlon);
+	debug("tanpd=%d\n", tanpd);
+	debug("taxpd=%d\n", taxpd);
+	debug("trfc=%d\n", trfc);
+	debug("txs=%d\n", txs);
+	debug("txp=%d\n", txp);
+	debug("txpdll=%d\n", txpdll);
+	debug("tfaw=%d\n", tfaw);
+	debug("tcl=%d\n", tcl);
+	debug("trcd=%d\n", trcd);
+	debug("trp=%d\n", trp);
+	debug("trc=%d\n", trc);
+	debug("tras=%d\n", tras);
+	debug("twr=%d\n", twr);
+	debug("tmrd=%d\n", tmrd);
+	debug("tcwl=%d\n", tcwl);
+	debug("tdllk=%d\n", tdllk);
+	debug("trtp=%d\n", trtp);
+	debug("twtr=%d\n", twtr);
+	debug("trrd=%d\n", trrd);
+	debug("txpr=%d\n", txpr);
+	debug("CS0_END=%d\n", CS0_END);
+	debug("ncs=%d\n", i->ncs);
+	debug("Rtt_wr=%d\n", i->rtt_wr);
+	debug("Rtt_nom=%d\n", i->rtt_nom);
+	debug("SRT=%d\n", m->SRT);
+	debug("tcl=%d\n", tcl);
+	debug("twr=%d\n", twr);
+
+	/*
+	 * board-specific configuration:
+	 *  These values are determined empirically and vary per board layout
+	 *  see:
+	 *   appnote, ddr3 spreadsheet
+	 */
+	mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
+	mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
+	mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
+	mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
+	mmdc0->mprddlctl = c->p0_mprddlctl;
+	mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
+	if (i->dsize > 1) {
+		mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
+		mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
+		mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
+		mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
+		mmdc1->mprddlctl = c->p1_mprddlctl;
+		mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+	}
+
+	/* Read data DQ Byte0-3 delay */
+	mmdc0->mprddqby0dl = (u32)0x33333333;
+	mmdc0->mprddqby1dl = (u32)0x33333333;
+	if (i->dsize > 0) {
+		mmdc0->mprddqby2dl = (u32)0x33333333;
+		mmdc0->mprddqby3dl = (u32)0x33333333;
+	}
+	if (i->dsize > 1) {
+		mmdc1->mprddqby0dl = (u32)0x33333333;
+		mmdc1->mprddqby1dl = (u32)0x33333333;
+		mmdc1->mprddqby2dl = (u32)0x33333333;
+		mmdc1->mprddqby3dl = (u32)0x33333333;
+	}
+
+	/* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
+	reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+	mmdc0->mpodtctrl = reg;
+	if (i->dsize > 1)
+		mmdc1->mpodtctrl = reg;
+
+	/* complete calibration */
+	reg = (1 << 11); /* Force measurement on delay-lines */
+	mmdc0->mpmur0 = reg;
+	if (i->dsize > 1)
+		mmdc1->mpmur0 = reg;
+
+	/* Step 1: configuration request */
+	mmdc0->mdscr = (u32)(1 << 15); /* config request */
+
+	/* Step 2: Timing configuration */
+	reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
+	      (tfaw << 4) | tcl;
+	mmdc0->mdcfg0 = reg;
+	reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
+	      (1 << 15) |		/* trpa */
+	      (twr << 9) | (tmrd << 5) | tcwl;
+	mmdc0->mdcfg1 = reg;
+	reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+	mmdc0->mdcfg2 = reg;
+	reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
+	      (todtlon << 12) | (todt_idle_off << 4);
+	mmdc0->mdotc = reg;
+	mmdc0->mdasp = CS0_END; /* CS addressing */
+
+	/* Step 3: Configure DDR type */
+	reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
+	      (i->mif3_mode << 9) | (i->ralat << 6);
+	mmdc0->mdmisc = reg;
+
+	/* Step 4: Configure delay while leaving reset */
+	reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
+	mmdc0->mdor = reg;
+
+	/* Step 5: Configure DDR physical parameters (density and burst len) */
+	reg = (m->rowaddr - 11) << 24 |		/* ROW */
+	      (m->coladdr - 9) << 20 |		/* COL */
+	      (1 << 19) |			/* Burst Length = 8 for DDR3 */
+	      (i->dsize << 16);			/* DDR data bus size */
+	mmdc0->mdctl = reg;
+
+	/* Step 6: Perform ZQ calibration */
+	reg = (u32)0xa1390001; /* one-time HW ZQ calib */
+	mmdc0->mpzqhwctrl = reg;
+	if (i->dsize > 1)
+		mmdc1->mpzqhwctrl = reg;
+
+	/* Step 7: Enable MMDC with desired chip select */
+	reg = mmdc0->mdctl |
+	      (1 << 31) |			/* SDE_0 for CS0 */
+	      ((i->ncs == 2) ? 1 : 0) << 30;	/* SDE_1 for CS1 */
+	mmdc0->mdctl = reg;
+
+	/* Step 8: Write Mode Registers to Init DDR3 devices */
+	for (cs = 0; cs < i->ncs; cs++) {
+		/* MR2 */
+		reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+		      ((tcwl - 3) & 3) << 3;
+		mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+		/* MR3 */
+		mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+		/* MR1 */
+		reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
+		      ((i->rtt_nom & 2) ? 1 : 0) << 6;
+		mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
+		reg = ((tcl - 1) << 4) |	/* CAS */
+		      (1 << 8)   |		/* DLL Reset */
+		      ((twr - 3) << 9);		/* Write Recovery */
+		/* MR0 */
+		mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+		/* ZQ calibration */
+		reg = (1 << 10);
+		mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+	}
+
+	/* Step 10: Power down control and self-refresh */
+	reg = (tcke & 0x7) << 16 |
+	      5            << 12 |  /* PWDT_1: 256 cycles */
+	      5            <<  8 |  /* PWDT_0: 256 cycles */
+	      1            <<  6 |  /* BOTH_CS_PD */
+	      (tcksrx & 0x7) << 3 |
+	      (tcksre & 0x7);
+	mmdc0->mdpdc = reg;
+	mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+
+	/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
+	mmdc0->mpzqhwctrl = (u32)0xa1390003;
+	if (i->dsize > 1)
+		mmdc1->mpzqhwctrl = (u32)0xa1390003;
+
+	/* Step 12: Configure and activate periodic refresh */
+	reg = (1 << 14) |	/* REF_SEL: Periodic refresh cycles of 32kHz */
+	      (7 << 11);	/* REFR: Refresh Rate - 8 refreshes */
+	mmdc0->mdref = reg;
+
+	/* Step 13: Deassert config request - init complete */
+	mmdc0->mdscr = (u32)0x00000000;
+
+	/* wait for auto-ZQ calibration to complete */
+	mdelay(1);
+}

arch/arm/cpu/armv7/mx6/hab.c

@@ -7,15 +7,69 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/hab.h>
+#include <asm/arch/sys_proto.h>
 
 /* -------- start of HAB API updates ------------*/
-#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
-#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
-#define hab_rvt_authenticate_image \
-	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
-#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
-#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
-#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
+
+#define hab_rvt_report_event_p					\
+(								\
+	((is_cpu_type(MXC_CPU_MX6Q) ||				\
+	  is_cpu_type(MXC_CPU_MX6D)) &&				\
+	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
+	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)	\
+)
+
+#define hab_rvt_report_status_p					\
+(								\
+	((is_cpu_type(MXC_CPU_MX6Q) ||				\
+	  is_cpu_type(MXC_CPU_MX6D)) &&				\
+	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)	\
+)
+
+#define hab_rvt_authenticate_image_p				\
+(								\
+	((is_cpu_type(MXC_CPU_MX6Q) ||				\
+	  is_cpu_type(MXC_CPU_MX6D)) &&				\
+	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)	\
+)
+
+#define hab_rvt_entry_p						\
+(								\
+	((is_cpu_type(MXC_CPU_MX6Q) ||				\
+	  is_cpu_type(MXC_CPU_MX6D)) &&				\
+	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
+	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY)			\
+)
+
+#define hab_rvt_exit_p						\
+(								\
+	((is_cpu_type(MXC_CPU_MX6Q) ||				\
+	  is_cpu_type(MXC_CPU_MX6D)) &&				\
+	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
+	(is_cpu_type(MXC_CPU_MX6DL) &&				\
+	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT)			\
+)
 
 bool is_hab_enabled(void)
 {
@@ -52,6 +106,11 @@ int get_hab_status(void)
 	size_t bytes = sizeof(event_data); /* Event size in bytes */
 	enum hab_config config = 0;
 	enum hab_state state = 0;
+	hab_rvt_report_event_t *hab_rvt_report_event;
+	hab_rvt_report_status_t *hab_rvt_report_status;
+
+	hab_rvt_report_event = hab_rvt_report_event_p;
+	hab_rvt_report_status = hab_rvt_report_status_p;
 
 	if (is_hab_enabled())
 		puts("\nSecure boot enabled\n");

arch/arm/cpu/armv7/mx6/soc.c

@@ -124,10 +124,9 @@ static void clear_ldo_ramp(void)
 }
 
 /*
- * Set the VDDSOC
+ * Set the PMU_REG_CORE register
  *
- * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
- * them to the specified millivolt level.
+ * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */

arch/arm/cpu/armv7/omap-common/mem-common.c

@@ -121,7 +121,8 @@ void gpmc_init(void)
 	writel(0x00000008, &gpmc_cfg->sysconfig);
 	writel(0x00000000, &gpmc_cfg->irqstatus);
 	writel(0x00000000, &gpmc_cfg->irqenable);
-	writel(0x00000000, &gpmc_cfg->timeout_control);
+	/* disable timeout, set a safe reset value */
+	writel(0x00001ff0, &gpmc_cfg->timeout_control);
 #ifdef CONFIG_NOR
 	writel(0x00000200, &gpmc_cfg->config);
 #else
@@ -133,5 +134,6 @@ void gpmc_init(void)
 	writel(0, &gpmc_cfg->cs[0].config7);
 	sdelay(1000);
 	/* enable chip-select specific configurations */
-	enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
+	if (base != 0)
+		enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 }

arch/arm/cpu/armv7/omap3/board.c

@@ -147,7 +147,7 @@ void secure_unlock_mem(void)
  *		configure secure registers and exit secure world
  *              general use.
  *****************************************************************************/
-void secureworld_exit()
+void secureworld_exit(void)
 {
 	unsigned long i;
 
@@ -178,7 +178,7 @@ void secureworld_exit()
  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  *              general use.
  *****************************************************************************/
-void try_unlock_memory()
+void try_unlock_memory(void)
 {
 	int mode;
 	int in_sdram = is_running_in_sdram();

arch/arm/cpu/armv7/socfpga/Makefile

@@ -9,4 +9,4 @@
 
 obj-y	:= lowlevel_init.o
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o

arch/arm/cpu/armv7/socfpga/misc.c

@@ -14,3 +14,27 @@ int dram_init(void)
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 	return 0;
 }
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
+defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+int misc_init_r(void)
+{
+	return 0;
+}

arch/arm/cpu/armv7/socfpga/scan_manager.c

@@ -0,0 +1,209 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/scan_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_scan_manager *scan_manager_base =
+		(void *)(SOCFPGA_SCANMGR_ADDRESS);
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Function to check IO scan chain engine status and wait if the engine is
+ * is active. Poll the IO scan chain engine till maximum iteration reached.
+ */
+static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
+{
+	uint32_t scanmgr_status;
+
+	scanmgr_status = readl(&scan_manager_base->stat);
+
+	/* Poll the engine until the scan engine is inactive */
+	while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status) ||
+	      (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
+		max_iter--;
+		if (max_iter > 0)
+			scanmgr_status = readl(&scan_manager_base->stat);
+		else
+			return 0;
+	}
+	return 1;
+}
+
+/* Program HPS IO Scan Chain */
+uint32_t scan_mgr_io_scan_chain_prg(
+	uint32_t io_scan_chain_id,
+	uint32_t io_scan_chain_len_in_bits,
+	const uint32_t *iocsr_scan_chain)
+{
+	uint16_t tdi_tdo_header;
+	uint32_t io_program_iter;
+	uint32_t io_scan_chain_data_residual;
+	uint32_t residual;
+	uint32_t i;
+	uint32_t index = 0;
+
+	/*
+	 * De-assert reinit if the IO scan chain is intended for HIO. In
+	 * this, its the chain 3.
+	 */
+	if (io_scan_chain_id == 3)
+		clrbits_le32(&freeze_controller_base->hioctrl,
+			     SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Check if the scan chain engine is inactive and the
+	 * WFIFO is empty before enabling the IO scan chain
+	 */
+	if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+		return 1;
+
+	/*
+	 * Enable IO Scan chain based on scan chain id
+	 * Note: only one chain can be enabled at a time
+	 */
+	setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+
+	/*
+	 * Calculate number of iteration needed for full 128-bit (4 x32-bits)
+	 * bits shifting. Each TDI_TDO packet can shift in maximum 128-bits
+	 */
+	io_program_iter	= io_scan_chain_len_in_bits >>
+		IO_SCAN_CHAIN_128BIT_SHIFT;
+	io_scan_chain_data_residual = io_scan_chain_len_in_bits &
+		IO_SCAN_CHAIN_128BIT_MASK;
+
+	/* Construct TDI_TDO packet for 128-bit IO scan chain (2 bytes) */
+	tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
+		(TDI_TDO_MAX_PAYLOAD <<	TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+	/* Program IO scan chain in 128-bit iteration */
+	for (i = 0; i < io_program_iter; i++) {
+		/* write TDI_TDO packet header to scan manager */
+		writel(tdi_tdo_header,	&scan_manager_base->fifo_double_byte);
+
+		/* calculate array index. Multiply by 4 as write 4 x 32bits */
+		index = i * 4;
+
+		/* write 4 successive 32-bit IO scan chain data into WFIFO */
+		writel(iocsr_scan_chain[index],
+		       &scan_manager_base->fifo_quad_byte);
+		writel(iocsr_scan_chain[index + 1],
+		       &scan_manager_base->fifo_quad_byte);
+		writel(iocsr_scan_chain[index + 2],
+		       &scan_manager_base->fifo_quad_byte);
+		writel(iocsr_scan_chain[index + 3],
+		       &scan_manager_base->fifo_quad_byte);
+
+		/*
+		 * Check if the scan chain engine has completed the
+		 * IO scan chain data shifting
+		 */
+		if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+			goto error;
+	}
+
+	/* Calculate array index for final TDI_TDO packet */
+	index = io_program_iter * 4;
+
+	/* Final TDI_TDO packet if any */
+	if (io_scan_chain_data_residual) {
+		/*
+		 * Calculate number of quad bytes FIFO write
+		 * needed for the final TDI_TDO packet
+		 */
+		io_program_iter	= io_scan_chain_data_residual >>
+			IO_SCAN_CHAIN_32BIT_SHIFT;
+
+		/*
+		 * Construct TDI_TDO packet for remaining IO
+		 * scan chain (2 bytes)
+		 */
+		tdi_tdo_header	= TDI_TDO_HEADER_FIRST_BYTE |
+			((io_scan_chain_data_residual - 1) <<
+			TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
+
+		/*
+		 * Program the last part of IO scan chain write TDI_TDO packet
+		 * header (2 bytes) to scan manager
+		 */
+		writel(tdi_tdo_header, &scan_manager_base->fifo_double_byte);
+
+		for (i = 0; i < io_program_iter; i++) {
+			/*
+			 * write remaining scan chain data into scan
+			 * manager WFIFO with 4 bytes write
+			*/
+			writel(iocsr_scan_chain[index + i],
+			       &scan_manager_base->fifo_quad_byte);
+		}
+
+		index += io_program_iter;
+		residual = io_scan_chain_data_residual &
+			IO_SCAN_CHAIN_32BIT_MASK;
+
+		if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
+			/*
+			 * write the last 4B scan chain data
+			 * into scan manager WFIFO
+			 */
+			writel(iocsr_scan_chain[index],
+			       &scan_manager_base->fifo_quad_byte);
+		} else {
+			/*
+			 * write the remaining 1 - 3 bytes scan chain
+			 * data into scan manager WFIFO byte by byte
+			 * to prevent JTAG engine shifting unused data
+			 * from the FIFO and mistaken the data as a
+			 * valid command (even though unused bits are
+			 * set to 0, but just to prevent hardware
+			 * glitch)
+			 */
+			for (i = 0; i < residual; i += 8) {
+				writel(((iocsr_scan_chain[index] >> i)
+					& IO_SCAN_CHAIN_BYTE_MASK),
+					&scan_manager_base->fifo_single_byte);
+			}
+		}
+
+		/*
+		 * Check if the scan chain engine has completed the
+		 * IO scan chain data shifting
+		 */
+		if (!scan_chain_engine_is_idle(SCAN_MAX_DELAY))
+			goto error;
+	}
+
+	/* Disable IO Scan chain when configuration done*/
+	clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+	return 0;
+
+error:
+	/* Disable IO Scan chain when error detected */
+	clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
+	return 1;
+}
+
+int scan_mgr_configure_iocsr(void)
+{
+	int status = 0;
+
+	/* configure the IOCSR through scan chain */
+	status |= scan_mgr_io_scan_chain_prg(0,
+		CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table);
+	status |= scan_mgr_io_scan_chain_prg(1,
+		CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table);
+	status |= scan_mgr_io_scan_chain_prg(2,
+		CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table);
+	status |= scan_mgr_io_scan_chain_prg(3,
+		CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table);
+	return status;
+}

arch/arm/cpu/armv7/socfpga/spl.c

@@ -121,6 +121,10 @@ void spl_board_init(void)
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);
 
+	/* configure the IOCSR / IO buffer settings */
+	if (scan_mgr_configure_iocsr())
+		hang();
+
 	/* configure the pin muxing through system manager */
 	sysmgr_pinmux_init();
 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */

arch/arm/cpu/armv7/tegra20/display.c

@@ -328,7 +328,7 @@ static int tegra_display_decode_config(const void *blob,
 	rgb = fdt_subnode_offset(blob, node, "rgb");
 
 	config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
-	if (!config->panel_node < 0) {
+	if (config->panel_node < 0) {
 		debug("%s: Cannot find panel information\n", __func__);
 		return -1;
 	}

arch/arm/cpu/armv7/zynq/u-boot.lds

@@ -18,6 +18,7 @@ SECTIONS
 	.text :
 	{
 		*(.__image_copy_start)
+		*(.vectors)
 		CPUDIR/start.o (.text*)
 		*(.text*)
 	}

arch/arm/cpu/armv8/cache_v8.c

@@ -12,15 +12,14 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-
-static void set_pgtable_section(u64 section, u64 memory_type)
+void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+			 u64 memory_type)
 {
-	u64 *page_table = (u64 *)gd->arch.tlb_addr;
 	u64 value;
 
-	value = (section << SECTION_SHIFT) | PMD_TYPE_SECT | PMD_SECT_AF;
+	value = section | PMD_TYPE_SECT | PMD_SECT_AF;
 	value |= PMD_ATTRINDX(memory_type);
-	page_table[section] = value;
+	page_table[index] = value;
 }
 
 /* to activate the MMU we need to set up virtual memory */
@@ -28,10 +27,13 @@ static void mmu_setup(void)
 {
 	int i, j, el;
 	bd_t *bd = gd->bd;
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
 
 	/* Setup an identity-mapping for all spaces */
-	for (i = 0; i < (PGTABLE_SIZE >> 3); i++)
-		set_pgtable_section(i, MT_DEVICE_NGNRNE);
+	for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
+		set_pgtable_section(page_table, i, i << SECTION_SHIFT,
+				    MT_DEVICE_NGNRNE);
+	}
 
 	/* Setup an identity-mapping for all RAM space */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
@@ -39,38 +41,26 @@ static void mmu_setup(void)
 		ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
 		for (j = start >> SECTION_SHIFT;
 		     j < end >> SECTION_SHIFT; j++) {
-			set_pgtable_section(j, MT_NORMAL);
+			set_pgtable_section(page_table, j, j << SECTION_SHIFT,
+					    MT_NORMAL);
 		}
 	}
 
 	/* load TTBR0 */
 	el = current_el();
 	if (el == 1) {
-		asm volatile("msr ttbr0_el1, %0"
-			     : : "r" (gd->arch.tlb_addr) : "memory");
-		asm volatile("msr tcr_el1, %0"
-			     : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
-			     : "memory");
-		asm volatile("msr mair_el1, %0"
-			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+				  TCR_FLAGS | TCR_EL1_IPS_BITS,
+				  MEMORY_ATTRIBUTES);
 	} else if (el == 2) {
-		asm volatile("msr ttbr0_el2, %0"
-			     : : "r" (gd->arch.tlb_addr) : "memory");
-		asm volatile("msr tcr_el2, %0"
-			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
-			     : "memory");
-		asm volatile("msr mair_el2, %0"
-			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+				  TCR_FLAGS | TCR_EL2_IPS_BITS,
+				  MEMORY_ATTRIBUTES);
 	} else {
-		asm volatile("msr ttbr0_el3, %0"
-			     : : "r" (gd->arch.tlb_addr) : "memory");
-		asm volatile("msr tcr_el3, %0"
-			     : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
-			     : "memory");
-		asm volatile("msr mair_el3, %0"
-			     : : "r" (MEMORY_ATTRIBUTES) : "memory");
+		set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+				  TCR_FLAGS | TCR_EL3_IPS_BITS,
+				  MEMORY_ATTRIBUTES);
 	}
-
 	/* enable the mmu */
 	set_sctlr(get_sctlr() | CR_M);
 }
@@ -83,12 +73,17 @@ void invalidate_dcache_all(void)
 	__asm_invalidate_dcache_all();
 }
 
+void __weak flush_l3_cache(void)
+{
+}
+
 /*
  * Performs a clean & invalidation of the entire data cache at all levels
  */
 void flush_dcache_all(void)
 {
 	__asm_flush_dcache_all();
+	flush_l3_cache();
 }
 
 /*
@@ -221,7 +216,7 @@ void invalidate_icache_all(void)
  * Enable dCache & iCache, whether cache is actually enabled
  * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
  */
-void enable_caches(void)
+void __weak enable_caches(void)
 {
 	icache_enable();
 	dcache_enable();

arch/arm/cpu/armv8/fsl-lsch3/Makefile

@@ -0,0 +1,9 @@
+#
+# Copyright 2014, Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += speed.o

arch/arm/cpu/armv8/fsl-lsch3/README

@@ -0,0 +1,10 @@
+#
+# Copyright 2014 Freescale Semiconductor
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 3
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
+for example LS2085A.

arch/arm/cpu/armv8/fsl-lsch3/cpu.c

@@ -0,0 +1,436 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include "cpu.h"
+#include "speed.h"
+#include <fsl_mc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * To start MMU before DDR is available, we create MMU table in SRAM.
+ * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * levels of translation tables here to cover 40-bit address space.
+ * We use 4KB granule size, with 40 bits physical address, T0SZ=24
+ * Level 0 IA[39], table address @0
+ * Level 1 IA[31:30], table address @01000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000
+ */
+
+#define SECTION_SHIFT_L0	39UL
+#define SECTION_SHIFT_L1	30UL
+#define SECTION_SHIFT_L2	21UL
+#define BLOCK_SIZE_L0		0x8000000000UL
+#define BLOCK_SIZE_L1		(1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2		(1 << SECTION_SHIFT_L2)
+#define CONFIG_SYS_IFC_BASE	0x30000000
+#define CONFIG_SYS_IFC_SIZE	0x10000000
+#define CONFIG_SYS_IFC_BASE2	0x500000000
+#define CONFIG_SYS_IFC_SIZE2	0x100000000
+#define TCR_EL2_PS_40BIT	(2 << 16)
+#define LSCH3_VA_BITS		(40)
+#define LSCH3_TCR	(TCR_TG0_4K		| \
+			TCR_EL2_PS_40BIT	| \
+			TCR_SHARED_NON		| \
+			TCR_ORGN_NC		| \
+			TCR_IRGN_NC		| \
+			TCR_T0SZ(LSCH3_VA_BITS))
+
+/*
+ * Final MMU
+ * Let's start from the same layout as early MMU and modify as needed.
+ * IFC regions will be cache-inhibit.
+ */
+#define FINAL_QBMAN_CACHED_MEM	0x818000000UL
+#define FINAL_QBMAN_CACHED_SIZE	0x4000000
+
+
+static inline void early_mmu_setup(void)
+{
+	int el;
+	u64 i;
+	u64 section_l1t0, section_l1t1, section_l2;
+	u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
+	u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
+	u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
+	u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
+	 * set level 1 table 1 to cache enabled, covering 512GB to 1TB
+	 * set level 2 table to cache-inhibit, covering 0 to 1GB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0;
+	section_l2 = 0;
+	for (i = 0; i < 512; i++) {
+		set_pgtable_section(level1_table_0, i, section_l1t0,
+				    MT_DEVICE_NGNRNE);
+		set_pgtable_section(level1_table_1, i, section_l1t1,
+				    MT_NORMAL);
+		set_pgtable_section(level2_table, i, section_l2,
+				    MT_DEVICE_NGNRNE);
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+		section_l2 += BLOCK_SIZE_L2;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table | PMD_TYPE_TABLE;
+	level1_table_0[1] =
+		0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_DEVICE_NGNRNE);
+	level1_table_0[2] =
+		0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_NORMAL);
+	level1_table_0[3] =
+		0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_NORMAL);
+
+	/* Rewrite table to enable cache */
+	set_pgtable_section(level2_table,
+			    CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
+			    CONFIG_SYS_FSL_OCRAM_BASE,
+			    MT_NORMAL);
+	for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
+	     i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
+	     >> SECTION_SHIFT_L2; i++) {
+		section_l2 = i << SECTION_SHIFT_L2;
+		set_pgtable_section(level2_table, i,
+				    section_l2, MT_NORMAL);
+	}
+
+	el = current_el();
+	set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+/*
+ * This final tale looks similar to early table, but different in detail.
+ * These tables are in regular memory. Cache on IFC is disabled. One sub table
+ * is added to enable cache for QBMan.
+ */
+static inline void final_mmu_setup(void)
+{
+	int el;
+	u64 i, tbl_base, tbl_limit, section_base;
+	u64 section_l1t0, section_l1t1, section_l2;
+	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
+	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
+	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
+	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0 to cache_inhibit, covering 0 to 512GB
+	 * set level 1 table 1 to cache enabled, covering 512GB to 1TB
+	 * set level 2 table 0 to cache-inhibit, covering 0 to 1GB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0;
+	section_l2 = 0;
+	for (i = 0; i < 512; i++) {
+		set_pgtable_section(level1_table_0, i, section_l1t0,
+				    MT_DEVICE_NGNRNE);
+		set_pgtable_section(level1_table_1, i, section_l1t1,
+				    MT_NORMAL);
+		set_pgtable_section(level2_table_0, i, section_l2,
+				    MT_DEVICE_NGNRNE);
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+		section_l2 += BLOCK_SIZE_L2;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
+	level1_table_0[2] =
+		0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_NORMAL);
+	level1_table_0[3] =
+		0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
+		PMD_ATTRINDX(MT_NORMAL);
+
+	/* Rewrite table to enable cache */
+	set_pgtable_section(level2_table_0,
+			    CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
+			    CONFIG_SYS_FSL_OCRAM_BASE,
+			    MT_NORMAL);
+
+	/*
+	 * Fill in other part of tables if cache is needed
+	 * If finer granularity than 1GB is needed, sub table
+	 * should be created.
+	 */
+	section_base = FINAL_QBMAN_CACHED_MEM & ~(BLOCK_SIZE_L1 - 1);
+	i = section_base >> SECTION_SHIFT_L1;
+	level1_table_0[i] = (u64)level2_table_1 | PMD_TYPE_TABLE;
+	section_l2 = section_base;
+	for (i = 0; i < 512; i++) {
+		set_pgtable_section(level2_table_1, i, section_l2,
+				    MT_DEVICE_NGNRNE);
+		section_l2 += BLOCK_SIZE_L2;
+	}
+	tbl_base = FINAL_QBMAN_CACHED_MEM & (BLOCK_SIZE_L1 - 1);
+	tbl_limit = (FINAL_QBMAN_CACHED_MEM + FINAL_QBMAN_CACHED_SIZE) &
+		    (BLOCK_SIZE_L1 - 1);
+	for (i = tbl_base >> SECTION_SHIFT_L2;
+	     i < tbl_limit >> SECTION_SHIFT_L2; i++) {
+		section_l2 = section_base + (i << SECTION_SHIFT_L2);
+		set_pgtable_section(level2_table_1, i,
+				    section_l2, MT_NORMAL);
+	}
+
+	/* flush new MMU table */
+	flush_dcache_range(gd->arch.tlb_addr,
+			   gd->arch.tlb_addr +  gd->arch.tlb_size);
+
+	/* point TTBR to the new table */
+	el = current_el();
+	asm volatile("dsb sy");
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0"
+			     : : "r" ((u64)level0_table) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0"
+			     : : "r" ((u64)level0_table) : "memory");
+	} else if (el == 3) {
+		asm volatile("msr ttbr0_el3, %0"
+			     : : "r" ((u64)level0_table) : "memory");
+	} else {
+		hang();
+	}
+	asm volatile("isb");
+
+	/*
+	 * MMU is already enabled, just need to invalidate TLB to load the
+	 * new table. The new table is compatible with the current table, if
+	 * MMU somehow walks through the new table before invalidation TLB,
+	 * it still works. So we don't need to turn off MMU here.
+	 */
+}
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+	__asm_invalidate_dcache_all();
+	__asm_invalidate_tlb_all();
+	early_mmu_setup();
+	set_sctlr(get_sctlr() | CR_C);
+	return 0;
+}
+
+/*
+ * flush_l3_cache
+ * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power
+ * state, by writing to HP-F P-state request register.
+ * Fixme: This function should moved to a common file if other SoCs also use
+ * the same Dickens.
+ */
+#define HNF0_PSTATE_REQ 0x04200010
+#define HNF1_PSTATE_REQ 0x04210010
+#define HNF2_PSTATE_REQ 0x04220010
+#define HNF3_PSTATE_REQ 0x04230010
+#define HNF4_PSTATE_REQ 0x04240010
+#define HNF5_PSTATE_REQ 0x04250010
+#define HNF6_PSTATE_REQ 0x04260010
+#define HNF7_PSTATE_REQ 0x04270010
+#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC)
+#define HNFPSTAT_FAM	0x3
+#define HNFPSTAT_SFONLY 0x01
+
+static void hnf_pstate_req(u64 *ptr, u64 state)
+{
+	int timeout = 1000;
+	out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3));
+	ptr++;
+	/* checking if the transition is completed */
+	while (timeout > 0) {
+		if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3))
+			break;
+		udelay(100);
+		timeout--;
+	}
+}
+
+void flush_l3_cache(void)
+{
+	hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY);
+	hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM);
+	hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM);
+}
+
+/*
+ * This function is called from lib/board.c.
+ * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
+ * There is no need to disable d-cache for this operation.
+ */
+void enable_caches(void)
+{
+	final_mmu_setup();
+	__asm_invalidate_tlb_all();
+}
+#endif
+
+static inline u32 initiator_type(u32 cluster, int init_id)
+{
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
+	u32 type = in_le32(&gur->tp_ityp[idx]);
+
+	if (type & TP_ITYP_AV)
+		return type;
+
+	return 0;
+}
+
+u32 cpu_mask(void)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster, type, mask = 0;
+
+	do {
+		int j;
+		cluster = in_le32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = initiator_type(cluster, j);
+			if (type) {
+				if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
+					mask |= 1 << count;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+	return mask;
+}
+
+/*
+ * Return the number of cores on this SOC.
+ */
+int cpu_numcores(void)
+{
+	return hweight32(cpu_mask());
+}
+
+int fsl_qoriq_core_to_cluster(unsigned int core)
+{
+	struct ccsr_gur __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster;
+
+	do {
+		int j;
+		cluster = in_le32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			if (initiator_type(cluster, j)) {
+				if (count == core)
+					return i;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+	return -1;      /* cannot identify the cluster */
+}
+
+u32 fsl_qoriq_core_to_type(unsigned int core)
+{
+	struct ccsr_gur __iomem *gur =
+		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	int i = 0, count = 0;
+	u32 cluster, type;
+
+	do {
+		int j;
+		cluster = in_le32(&gur->tp_cluster[i].lower);
+		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
+			type = initiator_type(cluster, j);
+			if (type) {
+				if (count == core)
+					return type;
+				count++;
+			}
+		}
+		i++;
+	} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+
+	return -1;      /* cannot identify the cluster */
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	struct sys_info sysinfo;
+	char buf[32];
+	unsigned int i, core;
+	u32 type;
+
+	get_sys_info(&sysinfo);
+	puts("Clock Configuration:");
+	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
+		if (!(i % 3))
+			puts("\n       ");
+		type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
+		printf("CPU%d(%s):%-4s MHz  ", core,
+		       type == TY_ITYP_VER_A7 ? "A7 " :
+		       (type == TY_ITYP_VER_A53 ? "A53" :
+			(type == TY_ITYP_VER_A57 ? "A57" : "   ")),
+		       strmhz(buf, sysinfo.freq_processor[core]));
+	}
+	printf("\n       Bus:      %-4s MHz  ",
+	       strmhz(buf, sysinfo.freq_systembus));
+	printf("DDR:      %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus));
+	puts("\n");
+
+	return 0;
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+	int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+	error = mc_init(bis);
+#endif
+	return error;
+}

arch/arm/cpu/armv8/fsl-lsch3/cpu.h

@@ -0,0 +1,7 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+int fsl_qoriq_core_to_cluster(unsigned int core);

arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S

@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Extracted from armv8/start.S
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+	/* Set the SMMU page size in the sACR register */
+	ldr	x1, =SMMU_BASE
+	ldr	w0, [x1, #0x10]
+	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
+	str	w0, [x1, #0x10]
+
+	/* Initialize GIC Secure Bank Status */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#ifdef CONFIG_GICV3
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+	branch_if_master x0, x1, 1f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All processors will enter EL2 and optionally EL1.
+	 */
+	bl	armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	armv8_switch_to_el1
+#endif
+	b	2f
+
+1:
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)

arch/arm/cpu/armv8/fsl-lsch3/speed.c

@@ -0,0 +1,176 @@
+/*
+ * Copyright 2014, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from arch/power/cpu/mpc85xx/speed.c
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <fsl_ifc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/clock.h>
+#include "cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
+#endif
+
+
+void get_sys_info(struct sys_info *sys_info)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	u32 ccr;
+#endif
+	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
+		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+		(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+	};
+	struct ccsr_clk_ctrl __iomem *clk_ctrl =
+		(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+	unsigned int cpu;
+	const u8 core_cplx_pll[16] = {
+		[0] = 0,	/* CC1 PPL / 1 */
+		[1] = 0,	/* CC1 PPL / 2 */
+		[2] = 0,	/* CC1 PPL / 4 */
+		[4] = 1,	/* CC2 PPL / 1 */
+		[5] = 1,	/* CC2 PPL / 2 */
+		[6] = 1,	/* CC2 PPL / 4 */
+		[8] = 2,	/* CC3 PPL / 1 */
+		[9] = 2,	/* CC3 PPL / 2 */
+		[10] = 2,	/* CC3 PPL / 4 */
+		[12] = 3,	/* CC4 PPL / 1 */
+		[13] = 3,	/* CC4 PPL / 2 */
+		[14] = 3,	/* CC4 PPL / 4 */
+	};
+
+	const u8 core_cplx_pll_div[16] = {
+		[0] = 1,	/* CC1 PPL / 1 */
+		[1] = 2,	/* CC1 PPL / 2 */
+		[2] = 4,	/* CC1 PPL / 4 */
+		[4] = 1,	/* CC2 PPL / 1 */
+		[5] = 2,	/* CC2 PPL / 2 */
+		[6] = 4,	/* CC2 PPL / 4 */
+		[8] = 1,	/* CC3 PPL / 1 */
+		[9] = 2,	/* CC3 PPL / 2 */
+		[10] = 4,	/* CC3 PPL / 4 */
+		[12] = 1,	/* CC4 PPL / 1 */
+		[13] = 2,	/* CC4 PPL / 2 */
+		[14] = 4,	/* CC4 PPL / 4 */
+	};
+
+	uint i, cluster;
+	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+	u32 c_pll_sel, cplx_pll;
+	void *offset;
+
+	sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+	sys_info->freq_ddrbus = sysclk;
+#endif
+
+	sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
+	sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
+			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
+
+	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+		/*
+		 * fixme: prefer to combine the following into one line, but
+		 * cannot pass compiling without warning about in_le32.
+		 */
+		offset = (void *)((size_t)clk_grp[i/3] +
+			 offsetof(struct ccsr_clk_cluster_group,
+				  pllngsr[i%3].gsr));
+		ratio[i] = (in_le32(offset) >> 1) & 0x3f;
+		if (ratio[i] > 4)
+			freq_c_pll[i] = sysclk * ratio[i];
+		else
+			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+	}
+
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		cluster = fsl_qoriq_core_to_cluster(cpu);
+		c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
+			    & 0xf;
+		cplx_pll = core_cplx_pll[c_pll_sel];
+		cplx_pll += cc_group[cluster] - 1;
+		sys_info->freq_processor[cpu] =
+			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+	}
+
+#if defined(CONFIG_FSL_IFC)
+	ccr = in_le32(&ifc_regs->ifc_ccr);
+	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+
+int get_clocks(void)
+{
+	struct sys_info sys_info;
+	get_sys_info(&sys_info);
+	gd->cpu_clk = sys_info.freq_processor[0];
+	gd->bus_clk = sys_info.freq_systembus;
+	gd->mem_clk = sys_info.freq_ddrbus;
+
+#if defined(CONFIG_FSL_ESDHC)
+	gd->arch.sdhc_clk = gd->bus_clk / 2;
+#endif /* defined(CONFIG_FSL_ESDHC) */
+
+	if (gd->cpu_clk != 0)
+		return 0;
+	else
+		return 1;
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq(ulong dummy)
+{
+	if (!gd->bus_clk)
+		get_clocks();
+
+	return gd->bus_clk;
+}
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+	if (!gd->mem_clk)
+		get_clocks();
+
+	return gd->mem_clk;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_I2C_CLK:
+		return get_bus_freq(0) / 2;
+	default:
+		printf("Unsupported clock\n");
+	}
+	return 0;
+}

arch/arm/cpu/armv8/fsl-lsch3/speed.h

@@ -0,0 +1,7 @@
+/*
+ * Copyright 2014, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void get_sys_info(struct sys_info *sys_info);

arch/arm/cpu/armv8/transition.S

@@ -43,7 +43,7 @@ ENTRY(armv8_switch_to_el1)
 	mrs	x0, cnthctl_el2
 	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
 	msr	cnthctl_el2, x0
-	msr	cntvoff_el2, x0
+	msr	cntvoff_el2, xzr
 	mrs	x0, cntkctl_el1
 	orr	x0, x0, #0x3		/* Enable EL0 access to timers */
 	msr	cntkctl_el1, x0

arch/arm/dts/Makefile

@@ -6,7 +6,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-smdk5250.dtb \
-	exynos5420-smdk5420.dtb
+	exynos5420-smdk5420.dtb \
+	exynos5420-peach-pit.dtb
 dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \

arch/arm/dts/exynos5420-peach-pit.dts

@@ -0,0 +1,127 @@
+/*
+ * SAMSUNG/GOOGLE Peach-Pit board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos54xx.dtsi"
+
+/ {
+	model = "Samsung/Google Peach Pit board based on Exynos5420";
+
+	compatible = "google,pit-rev#", "google,pit",
+		"google,peach", "samsung,exynos5420", "samsung,exynos5";
+
+	config {
+		google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+		hwid = "PIT TEST A-A 7848";
+		lazy-init = <1>;
+	};
+
+	aliases {
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+		pmic = "/i2c@12ca0000";
+	};
+
+	dmc {
+		mem-manuf = "samsung";
+		mem-type = "ddr3";
+		clock-frequency = <800000000>;
+		arm-frequency = <1700000000>;
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	/* MAX77802 is on i2c bus 4 */
+	i2c@12ca0000 {
+		clock-frequency = <400000>;
+		power-regulator@9 {
+			compatible = "maxim,max77802-pmic";
+			reg = <0x9>;
+		};
+	};
+
+	i2c@12cd0000 { /* i2c7 */
+		clock-frequency = <100000>;
+	       soundcodec@20 {
+	              reg = <0x20>;
+	              compatible = "maxim,max98090-codec";
+	       };
+	};
+
+        sound@3830000 {
+                samsung,codec-type = "max98090";
+        };
+
+	i2c@12e10000 { /* i2c9 */
+		clock-frequency = <400000>;
+                tpm@20 {
+                        compatible = "infineon,slb9645-tpm";
+                        reg = <0x20>;
+		};
+	};
+
+	spi@12d30000 { /* spi1 */
+		spi-max-frequency = <50000000>;
+		firmware_storage_spi: flash@0 {
+			reg = <0>;
+
+			/*
+			 * A region for the kernel to store a panic event
+			 * which the firmware will add to the log.
+			*/
+			elog-panic-event-offset = <0x01e00000 0x100000>;
+
+			elog-shrink-size = <0x400>;
+			elog-full-threshold = <0xc00>;
+		};
+	};
+
+	spi@12d40000 { /* spi2 */
+		spi-max-frequency = <4000000>;
+		spi-deactivate-delay = <200>;
+		cros-ec@0 {
+			reg = <0>;
+			compatible = "google,cros-ec";
+			spi-half-duplex;
+			spi-max-timeout-ms = <1100>;
+			spi-frame-header = <0xec>;
+			ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+
+			/*
+			 * This describes the flash memory within the EC. Note
+			 * that the STM32L flash erases to 0, not 0xff.
+			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			flash@8000000 {
+				reg = <0x08000000 0x20000>;
+				erase-value = <0>;
+			};
+		};
+	};
+
+	xhci@12000000 {
+		samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+	};
+
+	xhci@12400000 {
+		samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+	};
+};

arch/arm/dts/exynos5420-smdk5420.dts

@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos5420.dtsi"
+/include/ "exynos54xx.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
@@ -19,27 +19,6 @@
 	};
 
 	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		i2c8 = "/i2c@12e00000";
-		i2c9 = "/i2c@12e10000";
-		i2c10 = "/i2c@12e20000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		xhci0 = "/xhci@12000000";
-		xhci1 = "/xhci@12400000";
 		serial0 = "/serial@12C30000";
 		console = "/serial@12C30000";
 	};

arch/arm/dts/exynos5420.dtsi

@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2013 SAMSUNG Electronics
- * SAMSUNG EXYNOS5420 SoC device tree source
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/include/ "exynos5.dtsi"
-
-/ {
-	config {
-		machine-arch-id = <4151>;
-	};
-
-	i2c@12ca0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CA0000 0x100>;
-		interrupts = <0 60 0>;
-	};
-
-	i2c@12cb0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CB0000 0x100>;
-		interrupts = <0 61 0>;
-	};
-
-	i2c@12cc0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CC0000 0x100>;
-		interrupts = <0 62 0>;
-	};
-
-	i2c@12cd0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CD0000 0x100>;
-		interrupts = <0 63 0>;
-	};
-
-	i2c@12e00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12E00000 0x100>;
-		interrupts = <0 87 0>;
-	};
-
-	i2c@12e10000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12E10000 0x100>;
-		interrupts = <0 88 0>;
-	};
-
-	i2c@12e20000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12E20000 0x100>;
-		interrupts = <0 203 0>;
-	};
-};

arch/arm/dts/exynos54xx.dtsi

@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+	config {
+		machine-arch-id = <4151>;
+	};
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		i2c8 = "/i2c@12e00000";
+		i2c9 = "/i2c@12e10000";
+		i2c10 = "/i2c@12e20000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		xhci0 = "/xhci@12000000";
+		xhci1 = "/xhci@12400000";
+	};
+
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c@12cb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c@12cc0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c@12cd0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c@12e00000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E00000 0x100>;
+		interrupts = <0 87 0>;
+	};
+
+	i2c@12e10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E10000 0x100>;
+		interrupts = <0 88 0>;
+	};
+
+	i2c@12e20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E20000 0x100>;
+		interrupts = <0 203 0>;
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+		samsung,pre-init;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	fimd@14400000 {
+		/* sysmmu is not used in U-Boot */
+		samsung,disable-sysmmu;
+	};
+
+	dp@145b0000 {
+		samsung,lt-status = <0>;
+
+		samsung,master-mode = <0>;
+		samsung,bist-mode = <0>;
+		samsung,bist-pattern = <0>;
+		samsung,h-sync-polarity = <0>;
+		samsung,v-sync-polarity = <0>;
+		samsung,interlaced = <0>;
+		samsung,color-space = <0>;
+		samsung,dynamic-range = <0>;
+		samsung,ycbcr-coeff = <0>;
+		samsung,color-depth = <1>;
+	};
+
+	dmc {
+		mem-type = "ddr3";
+	};
+
+	xhci1: xhci@12400000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12400000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12500000 0x100>;
+		};
+	};
+};

arch/arm/imx-common/Makefile

@@ -16,6 +16,7 @@ obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
 obj-y	+= misc.o
+obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o

arch/arm/imx-common/cpu.c

@@ -58,6 +58,7 @@ char *get_reset_cause(void)
 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
 static const unsigned char bank_lookup[] = {3, 2};
 
+/* these MMDC registers are common to the IMX53 and IMX6 */
 struct esd_mmdc_regs {
 	uint32_t	ctl;
 	uint32_t	pdc;
@@ -66,15 +67,6 @@ struct esd_mmdc_regs {
 	uint32_t	cfg1;
 	uint32_t	cfg2;
 	uint32_t	misc;
-	uint32_t	scr;
-	uint32_t	ref;
-	uint32_t	rsvd1;
-	uint32_t	rsvd2;
-	uint32_t	rwd;
-	uint32_t	or;
-	uint32_t	mrr;
-	uint32_t	cfg3lp;
-	uint32_t	mr4;
 };
 
 #define ESD_MMDC_CTL_GET_ROW(mdctl)	((ctl >> 24) & 7)
@@ -83,6 +75,12 @@ struct esd_mmdc_regs {
 #define ESD_MMDC_CTL_GET_CS1(mdctl)	((ctl >> 30) & 1)
 #define ESD_MMDC_MISC_GET_BANK(mdmisc)	((misc >> 5) & 1)
 
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
 unsigned imx_ddr_size(void)
 {
 	struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;

arch/arm/imx-common/iomux-v3.c

@@ -11,6 +11,9 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
+#include <asm/arch/sys_proto.h>
+#endif
 #include <asm/imx-common/iomux-v3.h>
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -54,12 +57,23 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #endif
 }
 
+/* configures a list of pads within declared with IOMUX_PADS macro */
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 				      unsigned count)
 {
 	iomux_v3_cfg_t const *p = pad_list;
+	int stride;
 	int i;
 
-	for (i = 0; i < count; i++)
-		imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+	stride = 2;
+	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+		p += 1;
+#else
+	stride = 1;
+#endif
+	for (i = 0; i < count; i++) {
+		imx_iomux_v3_setup_pad(*p);
+		p += stride;
+	}
 }

arch/arm/imx-common/sata.c

@@ -8,13 +8,18 @@
 #include <asm/arch/iomux.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 
 int setup_sata(void)
 {
 	struct iomuxc_base_regs *const iomuxc_regs
 		= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+	int ret;
 
-	int ret = enable_sata_clock();
+	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+		return 1;
+
+	ret = enable_sata_clock();
 	if (ret)
 		return ret;
 

arch/arm/imx-common/spl.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/spl.h>
+#include <spl.h>
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+	struct src *psrc = (struct src *)SRC_BASE_ADDR;
+	unsigned reg = readl(&psrc->sbmr1);
+
+	/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+	switch ((reg & 0x000000FF) >> 4) {
+	 /* EIM: See 8.5.1, Table 8-9 */
+	case 0x0:
+		/* BOOT_CFG1[3]: NOR/OneNAND Selection */
+		if ((reg & 0x00000008) >> 3)
+			return BOOT_DEVICE_ONENAND;
+		else
+			return BOOT_DEVICE_NOR;
+		break;
+	/* SATA: See 8.5.4, Table 8-20 */
+	case 0x2:
+		return BOOT_DEVICE_SATA;
+	/* Serial ROM: See 8.5.5.1, Table 8-22 */
+	case 0x3:
+		/* BOOT_CFG4[2:0] */
+		switch ((reg & 0x07000000) >> 24) {
+		case 0x0 ... 0x4:
+			return BOOT_DEVICE_SPI;
+		case 0x5 ... 0x7:
+			return BOOT_DEVICE_I2C;
+		}
+		break;
+	/* SD/eSD: 8.5.3, Table 8-15  */
+	case 0x4:
+	case 0x5:
+		return BOOT_DEVICE_MMC1;
+	/* MMC/eMMC: 8.5.3 */
+	case 0x6:
+	case 0x7:
+		return BOOT_DEVICE_MMC1;
+	/* NAND Flash: 8.5.2 */
+	case 0x8 ... 0xf:
+		return BOOT_DEVICE_NAND;
+	}
+	return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	/* for MMC return either RAW or FAT mode */
+	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	default:
+		puts("spl: ERROR:  unsupported device\n");
+		hang();
+	}
+}
+#endif

arch/arm/include/asm/arch-am33xx/cpu.h

@@ -489,6 +489,12 @@ struct ctrl_stat {
 #define OMAP_GPIO_SETDATAOUT		0x0194
 
 /* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK	0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK	0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK		0xFFFFFF8F
+
 struct ctrl_dev {
 	unsigned int deviceid;		/* offset 0x00 */
 	unsigned int resv1[7];
@@ -502,10 +508,25 @@ struct ctrl_dev {
 	unsigned int macid1h;		/* offset 0x3c */
 	unsigned int resv4[4];
 	unsigned int miisel;		/* offset 0x50 */
-	unsigned int resv5[106];
+	unsigned int resv5[7];
+	unsigned int mreqprio_0;	/* offset 0x70 */
+	unsigned int mreqprio_1;	/* offset 0x74 */
+	unsigned int resv6[97];
 	unsigned int efuse_sma;		/* offset 0x1FC */
 };
 
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+	u32 padding0[2];
+	u32 modena_init0_bw_fractional;
+	u32 modena_init0_bw_integer;
+	u32 modena_init0_watermark_0;
+};
+
 /* gmii_sel register defines */
 #define GMII1_SEL_MII		0x0
 #define GMII1_SEL_RMII		0x1

arch/arm/include/asm/arch-am33xx/hardware_am43xx.h

@@ -13,6 +13,9 @@
 
 /* Module base addresses */
 
+/* L3 Fast Configuration Bandwidth Limiter Base Address */
+#define L3F_CFG_BWLIMITER		0x44005200
+
 /* UART Base Address */
 #define UART0_BASE			0x44E09000
 
@@ -40,6 +43,11 @@
 #define VTP0_CTRL_ADDR			0x44E10E0C
 #define VTP1_CTRL_ADDR			0x48140E10
 
+/* USB CTRL Base Address */
+#define USB1_CTRL			0x44e10628
+#define USB1_CTRL_CM_PWRDN		BIT(0)
+#define USB1_CTRL_OTG_PWRDN		BIT(1)
+
 /* DDR Base address */
 #define DDR_PHY_CMD_ADDR		0x44E12000
 #define DDR_PHY_DATA_ADDR		0x44E120C8

arch/arm/include/asm/arch-am33xx/omap.h

@@ -29,6 +29,8 @@
 #define SRAM_SCRATCH_SPACE_ADDR	0x40337C00
 #define AM4372_BOARD_NAME_START	SRAM_SCRATCH_SPACE_ADDR
 #define AM4372_BOARD_NAME_END	SRAM_SCRATCH_SPACE_ADDR + 0xC
+#define AM4372_BOARD_VERSION_START	SRAM_SCRATCH_SPACE_ADDR + 0xD
+#define AM4372_BOARD_VERSION_END	SRAM_SCRATCH_SPACE_ADDR + 0x14
 #define QSPI_BASE              0x47900000
 #endif
 #endif

arch/arm/include/asm/arch-at91/spl.h

@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2013 Atmel Corporation
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_
-
-enum {
-	BOOT_DEVICE_NONE,
-#ifdef CONFIG_SYS_USE_MMC
-	BOOT_DEVICE_MMC1,
-	BOOT_DEVICE_MMC2,
-	BOOT_DEVICE_MMC2_2,
-#elif CONFIG_SYS_USE_NANDFLASH
-	BOOT_DEVICE_NAND,
-#elif CONFIG_SYS_USE_SERIALFLASH
-	BOOT_DEVICE_SPI,
-#endif
-};
-
-#endif

arch/arm/include/asm/arch-davinci/emif_defs.h

@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _EMIF_DEFS_H_
-#define _EMIF_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-struct davinci_emif_regs {
-	u_int32_t	ercsr;
-	u_int32_t	awccr;
-	u_int32_t	sdbcr;
-	u_int32_t	sdrcr;
-	u_int32_t	ab1cr;
-	u_int32_t	ab2cr;
-	u_int32_t	ab3cr;
-	u_int32_t	ab4cr;
-	u_int32_t	sdtimr;
-	u_int32_t	ddrsr;
-	u_int32_t	ddrphycr;
-	u_int32_t	ddrphysr;
-	u_int32_t	totar;
-	u_int32_t	totactr;
-	u_int32_t	ddrphyid_rev;
-	u_int32_t	sdsretr;
-	u_int32_t	eirr;
-	u_int32_t	eimr;
-	u_int32_t	eimsr;
-	u_int32_t	eimcr;
-	u_int32_t	ioctrlr;
-	u_int32_t	iostatr;
-	u_int8_t	rsvd0[8];
-	u_int32_t	nandfcr;
-	u_int32_t	nandfsr;
-	u_int8_t	rsvd1[8];
-	u_int32_t	nandfecc[4];
-	u_int8_t	rsvd2[60];
-	u_int32_t	nand4biteccload;
-	u_int32_t	nand4bitecc[4];
-	u_int32_t	nanderradd1;
-	u_int32_t	nanderradd2;
-	u_int32_t	nanderrval1;
-	u_int32_t	nanderrval2;
-};
-
-#define davinci_emif_regs \
-	((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
-
-#define DAVINCI_NANDFCR_NAND_ENABLE(n)			(1 << (n-2))
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK		(3 << 4)
-#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n)			((n-2) << 4)
-#define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + (n-2)))
-#define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
-#define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
-#define DAVINCI_NANDFCR_CS2NAND				(1 << 0)
-
-/* Chip Select setup */
-#define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
-#define DAVINCI_ABCR_EXT_WAIT				(1 << 30)
-#define DAVINCI_ABCR_WSETUP(n)				(n << 26)
-#define DAVINCI_ABCR_WSTROBE(n)				(n << 20)
-#define DAVINCI_ABCR_WHOLD(n)				(n << 17)
-#define DAVINCI_ABCR_RSETUP(n)				(n << 13)
-#define DAVINCI_ABCR_RSTROBE(n)				(n << 7)
-#define DAVINCI_ABCR_RHOLD(n)				(n << 4)
-#define DAVINCI_ABCR_TA(n)				(n << 2)
-#define DAVINCI_ABCR_ASIZE_16BIT			1
-#define DAVINCI_ABCR_ASIZE_8BIT				0
-
-#endif

arch/arm/include/asm/arch-davinci/hardware.h

@@ -597,7 +597,6 @@ static inline enum davinci_clk_ids get_async3_src(void)
 #if defined(CONFIG_SOC_DM365)
 #include <asm/arch/aintc_defs.h>
 #include <asm/arch/ddr2_defs.h>
-#include <asm/arch/emif_defs.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pll_defs.h>
 #include <asm/arch/psc_defs.h>

arch/arm/include/asm/arch-davinci/nand_defs.h

@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Parts shamelesly stolen from Linux Kernel source tree.
- *
- * ------------------------------------------------------------
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_SOC_DM646X
-#define	MASK_CLE	0x80000
-#define	MASK_ALE	0x40000
-#else
-#define	MASK_CLE	0x10
-#define	MASK_ALE	0x08
-#endif
-
-#ifdef CONFIG_SYS_NAND_MASK_CLE
-#undef MASK_CLE
-#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
-#endif
-#ifdef CONFIG_SYS_NAND_MASK_ALE
-#undef MASK_ALE
-#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
-#endif
-
-#define NAND_READ_START		0x00
-#define NAND_READ_END		0x30
-#define NAND_STATUS		0x70
-
-extern void davinci_nand_init(struct nand_chip *nand);
-
-#endif

arch/arm/include/asm/arch-davinci/spl.h

@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NAND	1
-#define BOOT_DEVICE_SPI		2
-#define BOOT_DEVICE_MMC1	3
-#define BOOT_DEVICE_MMC2	4	/* dummy */
-#define BOOT_DEVICE_MMC2_2	5	/* dummy */
-
-#endif

arch/arm/include/asm/arch-ep93xx/ep93xx.h

@@ -1,6 +1,9 @@
 /*
  * Cirrus Logic EP93xx register definitions.
  *
+ * Copyright (C) 2013
+ * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
+ *
  * Copyright (C) 2009
  * Matthias Kaehlcke <matthias@kaehlcke.net>
  *
@@ -287,6 +290,20 @@ struct sdram_regs {
 #define SDRAM_DEVCFG_CASLAT_2		0x00010000
 #define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
 
+#define SDRAM_OFF_GLCONFIG		0x0004
+#define SDRAM_OFF_REFRSHTIMR		0x0008
+
+#define SDRAM_OFF_DEVCFG0		0x0010
+#define SDRAM_OFF_DEVCFG1		0x0014
+#define SDRAM_OFF_DEVCFG2		0x0018
+#define SDRAM_OFF_DEVCFG3		0x001C
+
+#define SDRAM_DEVCFG0_BASE		0xC0000000
+#define SDRAM_DEVCFG1_BASE		0xD0000000
+#define SDRAM_DEVCFG2_BASE		0xE0000000
+#define SDRAM_DEVCFG3_ASD0_BASE		0xF0000000
+#define SDRAM_DEVCFG3_ASD1_BASE		0x00000000
+
 #define GLCONFIG_INIT			(1 << 0)
 #define GLCONFIG_MRS			(1 << 1)
 #define GLCONFIG_SMEMBUSY		(1 << 5)
@@ -295,6 +312,43 @@ struct sdram_regs {
 #define GLCONFIG_CLKSHUTDOWN		(1 << 30)
 #define GLCONFIG_CKE			(1 << 31)
 
+#define EP93XX_SDRAMCTRL			0x80060000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_INIT		0x00000001
+#define EP93XX_SDRAMCTRL_GLOBALCFG_MRS		0x00000002
+#define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY	0x00000020
+#define EP93XX_SDRAMCTRL_GLOBALCFG_LCR		0x00000040
+#define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN	0x00000080
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN	0x40000000
+#define EP93XX_SDRAMCTRL_GLOBALCFG_CKE		0x80000000
+
+#define EP93XX_SDRAMCTRL_REFRESH_MASK		0x0000FFFF
+
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32	0x00000002
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16	0x00000001
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8	0x00000000
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK	0x00000003
+#define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA	0x00000004
+
+#define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH	0x00000004
+#define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT	0x00000008
+#define EP93XX_SDRAMCTRL_DEVCFG_SROM512		0x00000010
+#define EP93XX_SDRAMCTRL_DEVCFG_SROMLL		0x00000020
+#define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE		0x00000040
+#define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR	0x00000080
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK	0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2	0x00010000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3	0x00020000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4	0x00030000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5	0x00040000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6	0x00050000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7	0x00060000
+#define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8	0x00070000
+#define EP93XX_SDRAMCTRL_DEVCFG_WBL		0x00080000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK	0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2	0x00200000
+#define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3	0x00300000
+#define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE	0x01000000
+
 /*
  * 0x80070000 - 0x8007FFFF: Reserved
  */
@@ -324,6 +378,13 @@ struct smc_regs {
 };
 #endif
 
+#define EP93XX_OFF_SMCBCR0		0x00
+#define EP93XX_OFF_SMCBCR1		0x04
+#define EP93XX_OFF_SMCBCR2		0x08
+#define EP93XX_OFF_SMCBCR3		0x0C
+#define EP93XX_OFF_SMCBCR6		0x18
+#define EP93XX_OFF_SMCBCR7		0x1C
+
 #define SMC_BCR_IDCY_SHIFT	0
 #define SMC_BCR_WST1_SHIFT	5
 #define SMC_BCR_BLE		(1 << 10)
@@ -445,6 +506,14 @@ struct gpio_regs {
 };
 #endif
 
+#define EP93XX_LED_DATA		0x80840020
+#define EP93XX_LED_GREEN_ON	0x0001
+#define EP93XX_LED_RED_ON	0x0002
+
+#define EP93XX_LED_DDR		0x80840024
+#define EP93XX_LED_GREEN_ENABLE	0x0001
+#define EP93XX_LED_RED_ENABLE	0x00020000
+
 /*
  * 0x80850000 - 0x8087FFFF: Reserved
  */
@@ -519,6 +588,9 @@ struct gpio_regs {
 #define SYSCON_OFFSET		0x930000
 #define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
 
+/* Security */
+#define SECURITY_EXTENSIONID	0x80832714
+
 #ifndef __ASSEMBLY__
 struct syscon_regs {
 	uint32_t pwrsts;
@@ -553,7 +625,11 @@ struct syscon_regs {
 #define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
 #endif
 
+#define SYSCON_OFF_CLKSET1			0x0020
+#define SYSCON_OFF_SYSCFG			0x009c
+
 #define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
+#define SYSCON_PWRCNT_USH_EN			(1 << 28)
 
 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
@@ -571,6 +647,8 @@ struct syscon_regs {
 #define SYSCON_CHIPID_REV_MASK			0xF0000000
 #define SYSCON_DEVICECFG_SWRST			(1 << 31)
 
+#define SYSCON_SYSCFG_LASDO			0x00000020
+
 /*
  * 0x80930000 - 0x8093FFFF: Watchdog Timer
  */
@@ -580,3 +658,10 @@ struct syscon_regs {
 /*
  * 0x80950000 - 0x9000FFFF: Reserved
  */
+
+/*
+ * During low_level init we store memory layout in memory at specific location
+ */
+#define UBOOT_MEMORYCNF_BANK_SIZE		0x2000
+#define UBOOT_MEMORYCNF_BANK_MASK		0x2004
+#define UBOOT_MEMORYCNF_BANK_COUNT		0x2008

arch/arm/include/asm/arch-exynos/dmc.h

@@ -467,6 +467,9 @@ enum mem_manuf {
 /* PHY_CON1 register fields */
 #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
 
+/* PHY_CON4 rgister fields */
+#define PHY_CON10_CTRL_OFFSETR3		(1 << 24)
+
 /* PHY_CON12 register fields */
 #define PHY_CON12_CTRL_START_POINT_SHIFT	24
 #define PHY_CON12_CTRL_INC_SHIFT	16

arch/arm/include/asm/arch-exynos/power.h

@@ -906,8 +906,8 @@ struct exynos5420_power {
 	unsigned int	sysip_dat3;
 	unsigned char	res11[0xe0];
 	unsigned int	pmu_spare0;
-	unsigned int	pmu_spare1;
-	unsigned int	pmu_spare2;
+	unsigned int	pmu_spare1; /* Store PHY0_CON4 for read leveling */
+	unsigned int	pmu_spare2; /* Store PHY1_CON4 for read leveling */
 	unsigned int	pmu_spare3;
 	unsigned char	res12[0x4];
 	unsigned int	cg_status0;

arch/arm/include/asm/arch-fsl-lsch3/clock.h

@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_BUS_CLK,
+	MXC_UART_CLK,
+	MXC_ESDHC_CLK,
+	MXC_I2C_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */

arch/arm/include/asm/arch-fsl-lsch3/config.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
+#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
+
+#include <fsl_ddrc_version.h>
+
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+
+#define CONFIG_SYS_IMMR				0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR		(CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR			(CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
+#define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
+#define CONFIG_SYS_FSL_TIMER_ADDR		0x023d0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
+						 0x18A0)
+
+#define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01030000)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE		0x06000000
+#define GICR_BASE		0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE		0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_FSL_DDR_LE
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
+#define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
+#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+
+
+/* IFC */
+#define CONFIG_SYS_FSL_IFC_LE
+
+#ifdef CONFIG_LS2085A
+#define CONFIG_MAX_CPUS				16
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
+#define CONFIG_NUM_DDR_CONTROLLERS		2
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */

arch/arm/include/asm/arch-fsl-lsch3/gpio.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
+#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
+#endif	/* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */

arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h

@@ -0,0 +1,116 @@
+/*
+ * LayerScape Internal Memory Map
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H
+#define __ARCH_FSL_LSCH3_IMMAP_H_
+
+/* This is chassis generation 3 */
+
+struct sys_info {
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+	unsigned long freq_qe;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	unsigned long freq_qman;
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	unsigned long freq_pme;
+#endif
+};
+
+/* Global Utilities Block */
+struct ccsr_gur {
+	u32	porsr1;		/* POR status 1 */
+	u32	porsr2;		/* POR status 2 */
+	u8	res_008[0x20-0x8];
+	u32	gpporcr1;	/* General-purpose POR configuration */
+	u32	gpporcr2;	/* General-purpose POR configuration 2 */
+	u32	dcfg_fusesr;	/* Fuse status register */
+	u32	gpporcr3;
+	u32	gpporcr4;
+	u8	res_034[0x70-0x34];
+	u32	devdisr;	/* Device disable control */
+	u32	devdisr2;	/* Device disable control 2 */
+	u32	devdisr3;	/* Device disable control 3 */
+	u32	devdisr4;	/* Device disable control 4 */
+	u32	devdisr5;	/* Device disable control 5 */
+	u32	devdisr6;	/* Device disable control 6 */
+	u32	devdisr7;	/* Device disable control 7 */
+	u8	res_08c[0x90-0x8c];
+	u32	coredisru;	/* uppper portion for support of 64 cores */
+	u32	coredisrl;	/* lower portion for support of 64 cores */
+	u8	res_098[0xa0-0x98];
+	u32	pvr;		/* Processor version */
+	u32	svr;		/* System version */
+	u32	mvr;		/* Manufacturing version */
+	u8	res_0ac[0x100-0xac];
+	u32	rcwsr[32];	/* Reset control word status */
+
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT	2
+#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK	0x1f
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT	10
+#define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+	u8	res_180[0x200-0x180];
+	u32	scratchrw[32];	/* Scratch Read/Write */
+	u8	res_280[0x300-0x280];
+	u32	scratchw1r[4];	/* Scratch Read (Write once) */
+	u8	res_310[0x400-0x310];
+	u32	bootlocptrl;	/* Boot location pointer low-order addr */
+	u32	bootlocptrh;	/* Boot location pointer high-order addr */
+	u8	res_408[0x500-0x408];
+	u8	res_500[0x740-0x500];	/* add more registers when needed */
+	u32	tp_ityp[64];	/* Topology Initiator Type Register */
+	struct {
+		u32	upper;
+		u32	lower;
+	} tp_cluster[3];	/* Core Cluster n Topology Register */
+	u8	res_858[0x1000-0x858];
+};
+
+#define TP_ITYP_AV		0x00000001	/* Initiator available */
+#define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
+#define TP_ITYP_TYPE_ARM	0x0
+#define TP_ITYP_TYPE_PPC	0x1		/* PowerPC */
+#define TP_ITYP_TYPE_OTHER	0x2		/* StarCore DSP */
+#define TP_ITYP_TYPE_HA		0x3		/* HW Accelerator */
+#define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
+#define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
+#define TY_ITYP_VER_A7		0x1
+#define TY_ITYP_VER_A53		0x2
+#define TY_ITYP_VER_A57		0x3
+
+#define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
+#define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
+#define TP_INIT_PER_CLUSTER     4
+
+struct ccsr_clk_cluster_group {
+	struct {
+		u8	res_00[0x10];
+		u32	csr;
+		u8	res_14[0x20-0x14];
+	} hwncsr[3];
+	u8	res_60[0x80-0x60];
+	struct {
+		u32	gsr;
+		u8	res_84[0xa0-0x84];
+	} pllngsr[3];
+	u8	res_e0[0x100-0xe0];
+};
+
+struct ccsr_clk_ctrl {
+	struct {
+		u32 csr;	/* core cluster n clock control status */
+		u8  res_04[0x20-0x04];
+	} clkcncsr[8];
+};
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H */

arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
+#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
+
+#define I2C_QUIRK_REG	/* enable 8-bit driver */
+
+#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */

arch/arm/include/asm/arch-keystone/hardware-k2hk.h

@@ -9,13 +9,6 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define K2HK_ASYNC_EMIF_CNTRL_BASE      0x21000a00
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   K2HK_ASYNC_EMIF_CNTRL_BASE
-#define K2HK_ASYNC_EMIF_DATA_CE0_BASE   0x30000000
-#define K2HK_ASYNC_EMIF_DATA_CE1_BASE   0x34000000
-#define K2HK_ASYNC_EMIF_DATA_CE2_BASE   0x38000000
-#define K2HK_ASYNC_EMIF_DATA_CE3_BASE   0x3c000000
-
 #define K2HK_PLL_CNTRL_BASE             0x02310000
 #define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
 #define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)

arch/arm/include/asm/arch-keystone/hardware.h

@@ -22,32 +22,6 @@
 typedef volatile unsigned int   dv_reg;
 typedef volatile unsigned int   *dv_reg_p;
 
-#define ASYNC_EMIF_NUM_CS               4
-#define ASYNC_EMIF_MODE_NOR             0
-#define ASYNC_EMIF_MODE_NAND            1
-#define ASYNC_EMIF_MODE_ONENAND         2
-#define ASYNC_EMIF_PRESERVE             -1
-
-struct async_emif_config {
-	unsigned mode;
-	unsigned select_strobe;
-	unsigned extend_wait;
-	unsigned wr_setup;
-	unsigned wr_strobe;
-	unsigned wr_hold;
-	unsigned rd_setup;
-	unsigned rd_strobe;
-	unsigned rd_hold;
-	unsigned turn_around;
-	enum {
-		ASYNC_EMIF_8	= 0,
-		ASYNC_EMIF_16	= 1,
-		ASYNC_EMIF_32	= 2,
-	} width;
-};
-
-void init_async_emif(int num_cs, struct async_emif_config *config);
-
 struct ddr3_phy_config {
 	unsigned int pllcr;
 	unsigned int pgcr1_mask;
@@ -145,6 +119,10 @@ struct ddr3_emif_config {
 #define KS2_UART0_BASE                	0x02530c00
 #define KS2_UART1_BASE                	0x02531000
 
+/* AEMIF */
+#define KS2_AEMIF_CNTRL_BASE       	0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif

arch/arm/include/asm/arch-keystone/nand_defs.h

@@ -1,23 +0,0 @@
-/*
- * nand driver definitions to re-use davinci nand driver on Keystone2
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <linux/mtd/nand.h>
-
-#define MASK_CLE         0x4000
-#define	MASK_ALE         0x2000
-
-#define NAND_READ_START  0x00
-#define NAND_READ_END    0x30
-#define NAND_STATUS      0x70
-
-#endif

arch/arm/include/asm/arch-keystone/spl.h

@@ -5,7 +5,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _ASM_ARCH_SPL_H_
-#define _ASM_SPL_H_
+#define _ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_SPI        2
 

arch/arm/include/asm/arch-mx35/spl.h

@@ -1,22 +0,0 @@
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_XIP		1
-#define BOOT_DEVICE_XIPWAIT	2
-#define BOOT_DEVICE_NAND	3
-#define BOOT_DEVICE_ONENAND	4
-#define BOOT_DEVICE_MMC1	5
-#define BOOT_DEVICE_MMC2	6
-#define BOOT_DEVICE_MMC2_2	7
-#define BOOT_DEVICE_NOR		8
-#define BOOT_DEVICE_I2C		9
-#define BOOT_DEVICE_SPI		10
-
-#endif

arch/arm/include/asm/arch-mx5/spl.h

@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_SPL_H__
-#define __ASM_ARCH_SPL_H__
-
-#define BOOT_DEVICE_NONE	0
-#define BOOT_DEVICE_NAND	1
-
-#endif	/* __ASM_ARCH_SPL_H__ */

arch/arm/include/asm/arch-mx6/hab.h

@@ -53,12 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
 		void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
-#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
-#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
-#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
-#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
+#define HAB_RVT_REPORT_EVENT                   (*(uint32_t *)0x000000B4)
+#define HAB_RVT_REPORT_STATUS                  (*(uint32_t *)0x000000B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE             (*(uint32_t *)0x000000A4)
+#define HAB_RVT_ENTRY                          (*(uint32_t *)0x00000098)
+#define HAB_RVT_EXIT                           (*(uint32_t *)0x0000009C)
+
+#define HAB_RVT_REPORT_EVENT_NEW               (*(uint32_t *)0x000000B8)
+#define HAB_RVT_REPORT_STATUS_NEW              (*(uint32_t *)0x000000BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW         (*(uint32_t *)0x000000A8)
+#define HAB_RVT_ENTRY_NEW                      (*(uint32_t *)0x0000009C)
+#define HAB_RVT_EXIT_NEW                       (*(uint32_t *)0x000000A0)
 
 #define HAB_CID_ROM 0 /**< ROM Caller ID */
 #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -217,6 +217,8 @@
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 #define CHIP_REV_1_0                 0x10
+#define CHIP_REV_1_2                 0x12
+#define CHIP_REV_1_5                 0x15
 #define IRAM_SIZE                    0x00040000
 #define FEC_QUIRK_ENET_MAC
 

arch/arm/include/asm/arch-mx6/iomux.h

@@ -39,7 +39,7 @@
 #define IOMUXC_GPR12_LOS_LEVEL_MASK		(0x1f << 4)
 #define IOMUXC_GPR12_APPS_LTSSM_ENABLE		(1 << 10)
 #define IOMUXC_GPR12_DEVICE_TYPE_EP		(0x0 << 12)
-#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC		(0x4 << 12)
 #define IOMUXC_GPR12_DEVICE_TYPE_MASK		(0xf << 12)
 
 /*

arch/arm/include/asm/arch-mx6/mx6-ddr.h

@@ -6,6 +6,7 @@
 #ifndef __ASM_ARCH_MX6_DDR_H__
 #define __ASM_ARCH_MX6_DDR_H__
 
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_MX6Q
 #include "mx6q-ddr.h"
 #else
@@ -15,6 +16,236 @@
 #error "Please select cpu"
 #endif	/* CONFIG_MX6DL or CONFIG_MX6S */
 #endif	/* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdscr;
+	u32 mdref;
+	u32 res1[2];
+	u32 mdrwd;
+	u32 mdor;
+	u32 res2[3];
+	u32 mdasp;
+	u32 res3[240];
+	u32 mapsr;
+	u32 res4[254];
+	u32 mpzqhwctrl;
+	u32 res5[2];
+	u32 mpwldectrl0;
+	u32 mpwldectrl1;
+	u32 res6;
+	u32 mpodtctrl;
+	u32 mprddqby0dl;
+	u32 mprddqby1dl;
+	u32 mprddqby2dl;
+	u32 mprddqby3dl;
+	u32 res7[4];
+	u32 mpdgctrl0;
+	u32 mpdgctrl1;
+	u32 res8;
+	u32 mprddlctl;
+	u32 res9;
+	u32 mpwrdlctl;
+	u32 res10[25];
+	u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE      0x020e0500
+struct mx6dq_iomux_ddr_regs {
+	u32 res1[3];
+	u32 dram_sdqs5;
+	u32 dram_dqm5;
+	u32 dram_dqm4;
+	u32 dram_sdqs4;
+	u32 dram_sdqs3;
+	u32 dram_dqm3;
+	u32 dram_sdqs2;
+	u32 dram_dqm2;
+	u32 res2[16];
+	u32 dram_cas;
+	u32 res3[2];
+	u32 dram_ras;
+	u32 dram_reset;
+	u32 res4[2];
+	u32 dram_sdclk_0;
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdclk_1;
+	u32 dram_sdcke1;
+	u32 dram_sdodt0;
+	u32 dram_sdodt1;
+	u32 res5;
+	u32 dram_sdqs0;
+	u32 dram_dqm0;
+	u32 dram_sdqs1;
+	u32 dram_dqm1;
+	u32 dram_sdqs6;
+	u32 dram_dqm6;
+	u32 dram_sdqs7;
+	u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE      0x020e0700
+struct mx6dq_iomux_grp_regs {
+	u32 res1[18];
+	u32 grp_b7ds;
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 res2;
+	u32 grp_ddrpke;
+	u32 res3[6];
+	u32 grp_ddrmode;
+	u32 res4[3];
+	u32 grp_b0ds;
+	u32 grp_b1ds;
+	u32 grp_ctlds;
+	u32 res5;
+	u32 grp_b2ds;
+	u32 grp_ddr_type;
+	u32 grp_b3ds;
+	u32 grp_b4ds;
+	u32 grp_b5ds;
+	u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE     0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+	u32 res1[25];
+	u32 dram_cas;
+	u32 res2[2];
+	u32 dram_dqm0;
+	u32 dram_dqm1;
+	u32 dram_dqm2;
+	u32 dram_dqm3;
+	u32 dram_dqm4;
+	u32 dram_dqm5;
+	u32 dram_dqm6;
+	u32 dram_dqm7;
+	u32 dram_ras;
+	u32 dram_reset;
+	u32 res3[2];
+	u32 dram_sdba2;
+	u32 dram_sdcke0;
+	u32 dram_sdcke1;
+	u32 dram_sdclk_0;
+	u32 dram_sdclk_1;
+	u32 dram_sdodt0;
+	u32 dram_sdodt1;
+	u32 dram_sdqs0;
+	u32 dram_sdqs1;
+	u32 dram_sdqs2;
+	u32 dram_sdqs3;
+	u32 dram_sdqs4;
+	u32 dram_sdqs5;
+	u32 dram_sdqs6;
+	u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE     0x020e0700
+struct mx6sdl_iomux_grp_regs {
+	u32 res1[18];
+	u32 grp_b7ds;
+	u32 grp_addds;
+	u32 grp_ddrmode_ctl;
+	u32 grp_ddrpke;
+	u32 res2[2];
+	u32 grp_ddrmode;
+	u32 grp_b0ds;
+	u32 res3;
+	u32 grp_ctlds;
+	u32 grp_b1ds;
+	u32 grp_ddr_type;
+	u32 grp_b2ds;
+	u32 grp_b3ds;
+	u32 grp_b4ds;
+	u32 grp_b5ds;
+	u32 res4;
+	u32 grp_b6ds;
+};
+
+/* Device Information: Varies per DDR3 part number and speed grade */
+struct mx6_ddr3_cfg {
+	u16 mem_speed;	/* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
+	u8 density;	/* chip density (Gb) (1,2,4,8) */
+	u8 width;	/* bus width (bits) (4,8,16) */
+	u8 banks;	/* number of banks */
+	u8 rowaddr;	/* row address bits (11-16)*/
+	u8 coladdr;	/* col address bits (9-12) */
+	u8 pagesz;	/* page size (K) (1-2) */
+	u16 trcd;	/* tRCD=tRP=CL (ns*100) */
+	u16 trcmin;	/* tRC min (ns*100) */
+	u16 trasmin;	/* tRAS min (ns*100) */
+	u8 SRT;		/* self-refresh temperature: 0=normal, 1=extended */
+};
+
+/* System Information: Varies per board design, layout, and term choices */
+struct mx6_ddr_sysinfo {
+	u8 dsize;	/* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
+	u8 cs_density;	/* density per chip select (Gb) */
+	u8 ncs;		/* number chip selects used (1|2) */
+	char cs1_mirror;/* enable address mirror (0|1) */
+	char bi_on;	/* Bank interleaving enable */
+	u8 rtt_nom;	/* Rtt_Nom (DDR3_RTT_*) */
+	u8 rtt_wr;	/* Rtt_Wr (DDR3_RTT_*) */
+	u8 ralat;	/* Read Additional Latency (0-7) */
+	u8 walat;	/* Write Additional Latency (0-3) */
+	u8 mif3_mode;	/* Command prediction working mode */
+	u8 rst_to_cke;	/* Time from SDE enable to CKE rise */
+	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
+};
+
+/*
+ * Board specific calibration:
+ *   This includes write leveling calibration values as well as DQS gating
+ *   and read/write delays. These values are board/layout/device specific.
+ *   Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
+ *   (DOC-96412) to determine these values over a range of boards and
+ *   temperatures.
+ */
+struct mx6_mmdc_calibration {
+	/* write leveling calibration */
+	u32 p0_mpwldectrl0;
+	u32 p0_mpwldectrl1;
+	u32 p1_mpwldectrl0;
+	u32 p1_mpwldectrl1;
+	/* read DQS gating */
+	u32 p0_mpdgctrl0;
+	u32 p0_mpdgctrl1;
+	u32 p1_mpdgctrl0;
+	u32 p1_mpdgctrl1;
+	/* read delay */
+	u32 p0_mprddlctl;
+	u32 p1_mprddlctl;
+	/* write delay */
+	u32 p0_mpwrdlctl;
+	u32 p1_mpwrdlctl;
+};
+
+/* configure iomux (pinctl/padctl) */
+void mx6dq_dram_iocfg(unsigned width,
+		      const struct mx6dq_iomux_ddr_regs *,
+		      const struct mx6dq_iomux_grp_regs *);
+void mx6sdl_dram_iocfg(unsigned width,
+		       const struct mx6sdl_iomux_ddr_regs *,
+		       const struct mx6sdl_iomux_grp_regs *);
+
+/* configure mx6 mmdc registers */
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
+		  const struct mx6_mmdc_calibration *,
+		  const struct mx6_ddr3_cfg *);
+
+#endif /* CONFIG_SPL_BUILD */
 
 #define MX6_MMDC_P0_MDCTL	0x021b0000
 #define MX6_MMDC_P0_MDPDC	0x021b0004

arch/arm/include/asm/arch-mx6/mx6dl_pins.h

@@ -158,7 +158,7 @@ MX6_PAD_DECL(DISP0_DAT1__IPU1_DISP0_DATA01,	0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CT
 MX6_PAD_DECL(DISP0_DAT1__LCD_DATA01,	0x03C8, 0x00B4, 1, 0x0000, 0, 0)
 MX6_PAD_DECL(DISP0_DAT1__ECSPI3_MOSI,	0x03C8, 0x00B4, 2, 0x0000, 0, 0)
 MX6_PAD_DECL(DISP0_DAT1__GPIO4_IO22,	0x03C8, 0x00B4, 5, 0x0000, 0, 0)
-MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x03CC, 0x00B8, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT10__IPU1_DISP0_DATA10,	0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
 MX6_PAD_DECL(DISP0_DAT10__LCD_DATA10,	0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm)
 MX6_PAD_DECL(DISP0_DAT10__GPIO4_IO31,	0x03CC, 0x00B8, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(DISP0_DAT11__IPU1_DISP0_DATA11,	0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
@@ -206,7 +206,7 @@ MX6_PAD_DECL(DISP0_DAT19__AUD5_RXD,	0x03F0, 0x00DC, 3, 0x07B0, 0, 0)
 MX6_PAD_DECL(DISP0_DAT19__AUD4_RXC,	0x03F0, 0x00DC, 4, 0x07A0, 0, 0)
 MX6_PAD_DECL(DISP0_DAT19__GPIO5_IO13,	0x03F0, 0x00DC, 5, 0x0000, 0, 0)
 MX6_PAD_DECL(DISP0_DAT19__EIM_CS3_B,	0x03F0, 0x00DC, 7, 0x0000, 0, 0)
-MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x03F4, 0x00E0, 0, 0x0000, 0, 0)
+MX6_PAD_DECL(DISP0_DAT2__IPU1_DISP0_DATA02,	0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm)
 MX6_PAD_DECL(DISP0_DAT2__LCD_DATA02,	0x03F4, 0x00E0, 1, 0x0000, 0, 0)
 MX6_PAD_DECL(DISP0_DAT2__ECSPI3_MISO,	0x03F4, 0x00E0, 2, 0x0000, 0, 0)
 MX6_PAD_DECL(DISP0_DAT2__GPIO4_IO23,	0x03F4, 0x00E0, 5, 0x0000, 0, 0)

arch/arm/include/asm/arch-mx6/sys_proto.h

@@ -11,7 +11,9 @@
 #include <asm/imx-common/regs-common.h>
 #include "../arch-imx/cpu.h"
 
-#define is_soc_rev(rev)	((get_cpu_rev() & 0xFF) - rev)
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev)        (soc_rev() - rev)
+
 u32 get_cpu_rev(void);
 
 /* returns MXC_CPU_ value */

arch/arm/include/asm/arch-socfpga/scan_manager.h

@@ -0,0 +1,90 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SCAN_MANAGER_H_
+#define	_SCAN_MANAGER_H_
+
+struct socfpga_scan_manager {
+	u32	stat;
+	u32	en;
+	u32	padding[2];
+	u32	fifo_single_byte;
+	u32	fifo_double_byte;
+	u32	fifo_quad_byte;
+};
+
+/*
+ * Shift count to get number of IO scan chain data in granularity
+ * of 128-bit ( N / 128 )
+ */
+#define IO_SCAN_CHAIN_128BIT_SHIFT		7
+
+/*
+ * Mask to get residual IO scan chain data in
+ * granularity of 128-bit ( N mod 128 )
+ */
+#define IO_SCAN_CHAIN_128BIT_MASK		0x7F
+
+/*
+ * Shift count to get number of IO scan chain
+ * data in granularity of 32-bit ( N / 32 )
+ */
+#define IO_SCAN_CHAIN_32BIT_SHIFT		5
+
+/*
+ * Mask to get residual IO scan chain data in
+ * granularity of 32-bit ( N mod 32 )
+ */
+#define IO_SCAN_CHAIN_32BIT_MASK		0x1F
+
+/* Byte mask */
+#define IO_SCAN_CHAIN_BYTE_MASK			0xFF
+
+/* 24-bits (3 bytes) IO scan chain payload definition */
+#define IO_SCAN_CHAIN_PAYLOAD_24BIT		24
+
+/*
+ * Maximum length of TDI_TDO packet payload is 128 bits,
+ * represented by (length - 1) in TDI_TDO header
+ */
+#define TDI_TDO_MAX_PAYLOAD			127
+
+/* TDI_TDO packet header for IO scan chain program */
+#define TDI_TDO_HEADER_FIRST_BYTE		0x80
+
+/* Position of second command byte for TDI_TDO packet */
+#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT	8
+
+/*
+ * Maximum polling loop to wait for IO scan chain engine
+ * becomes idle to prevent infinite loop
+ */
+#define SCAN_MAX_DELAY				100
+
+#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31)
+#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28)
+
+/*
+ * Program HPS IO Scan Chain
+ * io_scan_chain_id - IO scan chain ID
+ * io_scan_chain_len_in_bits - IO scan chain length in bits
+ * iocsr_scan_chain - IO scan chain table
+ */
+uint32_t scan_mgr_io_scan_chain_prg(
+	uint32_t io_scan_chain_id,
+	uint32_t io_scan_chain_len_in_bits,
+	const uint32_t *iocsr_scan_chain);
+
+extern const uint32_t iocsr_scan_chain0_table[
+	((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)];
+extern const uint32_t iocsr_scan_chain1_table[
+	((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)];
+extern const uint32_t iocsr_scan_chain2_table[
+	((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)];
+extern const uint32_t iocsr_scan_chain3_table[
+	((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
+
+#endif /* _SCAN_MANAGER_H_ */

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h

@@ -11,8 +11,10 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
+#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000
 
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */

arch/arm/include/asm/arch-sunxi/spl.h

@@ -7,7 +7,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_SPL_H_
+#define	_ASM_ARCH_SPL_H_
 
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1

arch/arm/include/asm/arch-tegra/tegra_i2c.h

@@ -124,6 +124,8 @@ struct i2c_ctlr {
 /* bit fields definitions for IO Packet Header 3 format */
 #define PKT_HDR3_READ_MODE_SHIFT	19
 #define PKT_HDR3_READ_MODE_MASK		(1 << PKT_HDR3_READ_MODE_SHIFT)
+#define PKT_HDR3_REPEAT_START_SHIFT	16
+#define PKT_HDR3_REPEAT_START_MASK	(1 << PKT_HDR3_REPEAT_START_SHIFT)
 #define PKT_HDR3_SLAVE_ADDR_SHIFT	0
 #define PKT_HDR3_SLAVE_ADDR_MASK	(0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
 

arch/arm/include/asm/arch-tegra114/spl.h

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM         1
-
-#endif

arch/arm/include/asm/arch-tegra124/spl.h

@@ -1,13 +0,0 @@
-/*
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif /* _ASM_ARCH_SPL_H_ */

arch/arm/include/asm/arch-tegra20/spl.h

@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM         1
-
-#endif

arch/arm/include/asm/arch-tegra30/spl.h

@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef	_ASM_ARCH_SPL_H_
-#define	_ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM         1
-
-#endif

arch/arm/include/asm/arch-tnetv107x/emif_defs.h

@@ -1 +0,0 @@
-#include <asm/arch-davinci/emif_defs.h>

arch/arm/include/asm/arch-tnetv107x/hardware.h

@@ -155,4 +155,6 @@ int wdt_kick(void);
 #define INTC_HINT_EN			(TNETV107X_INTC_BASE + 0x1500)
 #define INTC_EN_CLR0			(TNETV107X_INTC_BASE + 0x380)
 
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
+
 #endif /* __ASM_ARCH_HARDWARE_H */

arch/arm/include/asm/arch-tnetv107x/nand_defs.h

@@ -1,23 +0,0 @@
-/*
- * TNETV107X: NAND definitions
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef _NAND_DEFS_H_
-#define _NAND_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/emif_defs.h>
-
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE	TNETV107X_ASYNC_EMIF_CNTRL_BASE
-
-#define	MASK_CLE		0x4000
-#define	MASK_ALE		0x2000
-
-#define NAND_READ_START		0x00
-#define NAND_READ_END		0x30
-#define NAND_STATUS		0x70
-
-extern void davinci_nand_init(struct nand_chip *nand);
-
-#endif

arch/arm/include/asm/arch-vf610/crm_regs.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -150,6 +150,9 @@ struct anadig_reg {
 #define CCM_CACRR_ARM_CLK_DIV_MASK		0x7
 #define CCM_CACRR_ARM_CLK_DIV(v)		((v) & 0x7)
 
+#define CCM_CSCMR1_QSPI0_CLK_SEL_OFFSET		22
+#define CCM_CSCMR1_QSPI0_CLK_SEL_MASK		(0x3 << 22)
+#define CCM_CSCMR1_QSPI0_CLK_SEL(v)		(((v) & 0x3) << 22)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK		(0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)		(((v) & 0x3) << 18)
@@ -161,6 +164,11 @@ struct anadig_reg {
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK		(0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)		(((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_QSPI0_EN			(1 << 4)
+#define CCM_CSCDR3_QSPI0_DIV(v)			((v) << 3)
+#define CCM_CSCDR3_QSPI0_X2_DIV(v)		((v) << 2)
+#define CCM_CSCDR3_QSPI0_X4_DIV(v)		((v) & 0x3)
+
 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET		4
 #define CCM_CSCMR2_RMII_CLK_SEL_MASK		(0x3 << 4)
 #define CCM_CSCMR2_RMII_CLK_SEL(v)		(((v) & 0x3) << 4)
@@ -170,6 +178,7 @@ struct anadig_reg {
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
+#define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
 #define CCM_CCGR2_IOMUXC_CTRL_MASK		(0x3 << 16)
 #define CCM_CCGR2_PORTA_CTRL_MASK		(0x3 << 18)
 #define CCM_CCGR2_PORTB_CTRL_MASK		(0x3 << 20)

arch/arm/include/asm/arch-vf610/imx-regs.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -87,6 +87,8 @@
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
 
+#define QSPI0_AMBA_BASE		0x20000000
+
 /* MUX mode and PAD ctrl are in one register */
 #define CONFIG_IOMUX_SHARE_CONF_REG
 

arch/arm/include/asm/arch-vf610/iomux-vf610.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -20,6 +20,9 @@
 #define VF610_I2C_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
 				PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 
+#define VF610_QSPI_PAD_CTRL	(PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_150ohm | \
+				PAD_CTL_PUS_22K_UP | PAD_CTL_OBE_IBE_ENABLE)
+
 enum {
 	VF610_PAD_PTA6__RMII0_CLKIN		= IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
 	VF610_PAD_PTA6__RMII0_CLKOUT		= IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
@@ -53,6 +56,18 @@ enum {
 	VF610_PAD_PTA29__ESDHC1_DAT3		= IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
 	VF610_PAD_PTB14__I2C0_SCL		= IOMUX_PAD(0x0090, 0x0090, 2, 0x033c, 1, VF610_I2C_PAD_CTRL),
 	VF610_PAD_PTB15__I2C0_SDA		= IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, VF610_I2C_PAD_CTRL),
+	VF610_PAD_PTD0__QSPI0_A_QSCK		= IOMUX_PAD(0x013c, 0x013c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD1__QSPI0_A_CS0		= IOMUX_PAD(0x0140, 0x0140, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD2__QSPI0_A_DATA3		= IOMUX_PAD(0x0144, 0x0144, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD3__QSPI0_A_DATA2		= IOMUX_PAD(0x0148, 0x0148, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD4__QSPI0_A_DATA1		= IOMUX_PAD(0x014c, 0x014c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD5__QSPI0_A_DATA0		= IOMUX_PAD(0x0150, 0x0150, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD7__QSPI0_B_QSCK		= IOMUX_PAD(0x0158, 0x0158, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD8__QSPI0_B_CS0		= IOMUX_PAD(0x015c, 0x015c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD9__QSPI0_B_DATA3		= IOMUX_PAD(0x0160, 0x0160, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD10__QSPI0_B_DATA2		= IOMUX_PAD(0x0164, 0x0164, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD11__QSPI0_B_DATA1		= IOMUX_PAD(0x0168, 0x0168, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
+	VF610_PAD_PTD12__QSPI0_B_DATA0		= IOMUX_PAD(0x016c, 0x016c, 1, __NA_, 0, VF610_QSPI_PAD_CTRL),
 	VF610_PAD_DDR_A15__DDR_A_15		= IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A14__DDR_A_14		= IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_A13__DDR_A_13		= IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),

arch/arm/include/asm/armv8/mmu.h

@@ -108,4 +108,28 @@
 				TCR_IRGN_WBWA |		\
 				TCR_T0SZ(VA_BITS))
 
+#ifndef __ASSEMBLY__
+void set_pgtable_section(u64 *page_table, u64 index,
+			 u64 section, u64 memory_type);
+static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
+{
+	asm volatile("dsb sy");
+	if (el == 1) {
+		asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
+	} else if (el == 2) {
+		asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
+	} else if (el == 3) {
+		asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
+		asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
+		asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
+	} else {
+		hang();
+	}
+	asm volatile("isb");
+}
+#endif
 #endif /* _ASM_ARMV8_MMU_H_ */

arch/arm/include/asm/cache.h

@@ -29,6 +29,9 @@ void l2_cache_enable(void);
 void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
 
+void arm_init_before_mmu(void);
+void arm_init_domains(void);
+void cpu_cache_initialization(void);
 void dram_bank_mmu_setup(int bank);
 
 #endif

arch/arm/include/asm/config.h

@@ -17,4 +17,8 @@
 #define CONFIG_STATIC_RELA
 #endif
 
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch-fsl-lsch3/config.h>
+#endif
+
 #endif

arch/arm/include/asm/emif.h

@@ -642,11 +642,16 @@ struct emif_reg_struct {
 	u32 emif_ddr_phy_ctrl_1;
 	u32 emif_ddr_phy_ctrl_1_shdw;
 	u32 emif_ddr_phy_ctrl_2;
-	u32 padding7[12];
+	u32 padding7[4];
+	u32 emif_prio_class_serv_map;
+	u32 emif_connect_id_serv_1_map;
+	u32 emif_connect_id_serv_2_map;
+	u32 padding8[5];
 	u32 emif_rd_wr_exec_thresh;
-	u32 padding8[7];
+	u32 emif_cos_config;
+	u32 padding9[6];
 	u32 emif_ddr_phy_status[21];
-	u32 padding9[27];
+	u32 padding10[27];
 	u32 emif_ddr_ext_phy_ctrl_1;
 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
 	u32 emif_ddr_ext_phy_ctrl_2;
@@ -1137,6 +1142,10 @@ struct emif_regs {
 	u32 emif_rd_wr_lvl_rmp_ctl;
 	u32 emif_rd_wr_lvl_ctl;
 	u32 emif_rd_wr_exec_thresh;
+	u32 emif_prio_class_serv_map;
+	u32 emif_connect_id_serv_1_map;
+	u32 emif_connect_id_serv_2_map;
+	u32 emif_cos_config;
 };
 
 struct lpddr2_mr_regs {

arch/arm/include/asm/imx-common/iomux-v3.h

@@ -123,12 +123,14 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_SPEED_MED	(1 << 12)
 #define PAD_CTL_SPEED_HIGH	(3 << 12)
 
+#define PAD_CTL_DSE_150ohm	(1 << 6)
 #define PAD_CTL_DSE_50ohm	(3 << 6)
 #define PAD_CTL_DSE_25ohm	(6 << 6)
 #define PAD_CTL_DSE_20ohm	(7 << 6)
 
 #define PAD_CTL_PUS_47K_UP	(1 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_PUS_100K_UP	(2 << 4 | PAD_CTL_PUE)
+#define PAD_CTL_PUS_22K_UP	(3 << 4 | PAD_CTL_PUE)
 #define PAD_CTL_PKE		(1 << 3)
 #define PAD_CTL_PUE		(1 << 2 | PAD_CTL_PKE)
 
@@ -175,4 +177,29 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 				     unsigned count);
 
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def)					\
+if (is_cpu_type(MXC_CPU_MX6Q)) {				\
+	imx_iomux_v3_setup_pad(MX6Q_##def);			\
+} else {							\
+	imx_iomux_v3_setup_pad(MX6DL_##def);			\
+}
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def)					\
+	imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def)					\
+	imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x)					\
+	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
 #endif	/* __MACH_IOMUX_V3_H__*/

arch/arm/include/asm/io.h

@@ -70,10 +70,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
 #define __arch_getb(a)			(*(volatile unsigned char *)(a))
 #define __arch_getw(a)			(*(volatile unsigned short *)(a))
 #define __arch_getl(a)			(*(volatile unsigned int *)(a))
+#define __arch_getq(a)			(*(volatile unsigned long long *)(a))
 
 #define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
 #define __arch_putw(v,a)		(*(volatile unsigned short *)(a) = (v))
 #define __arch_putl(v,a)		(*(volatile unsigned int *)(a) = (v))
+#define __arch_putq(v,a)		(*(volatile unsigned long long *)(a) = (v))
 
 extern inline void __raw_writesb(unsigned long addr, const void *data,
 				 int bytelen)
@@ -123,10 +125,12 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define __raw_writeb(v,a)	__arch_putb(v,a)
 #define __raw_writew(v,a)	__arch_putw(v,a)
 #define __raw_writel(v,a)	__arch_putl(v,a)
+#define __raw_writeq(v,a)	__arch_putq(v,a)
 
 #define __raw_readb(a)		__arch_getb(a)
 #define __raw_readw(a)		__arch_getw(a)
 #define __raw_readl(a)		__arch_getl(a)
+#define __raw_readq(a)		__arch_getq(a)
 
 /*
  * TODO: The kernel offers some more advanced versions of barriers, it might
@@ -139,10 +143,12 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define writeb(v,c)	({ u8  __v = v; __iowmb(); __arch_putb(__v,c); __v; })
 #define writew(v,c)	({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
 #define writel(v,c)	({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
+#define writeq(v,c)	({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; })
 
 #define readb(c)	({ u8  __v = __arch_getb(c); __iormb(); __v; })
 #define readw(c)	({ u16 __v = __arch_getw(c); __iormb(); __v; })
 #define readl(c)	({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define readq(c)	({ u64 __v = __arch_getq(c); __iormb(); __v; })
 
 /*
  * The compiler seems to be incapable of optimising constants
@@ -168,9 +174,11 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
 #define out_arch(type,endian,a,v)	__raw_write##type(cpu_to_##endian(v),a)
 #define in_arch(type,endian,a)		endian##_to_cpu(__raw_read##type(a))
 
+#define out_le64(a,v)	out_arch(q,le64,a,v)
 #define out_le32(a,v)	out_arch(l,le32,a,v)
 #define out_le16(a,v)	out_arch(w,le16,a,v)
 
+#define in_le64(a)	in_arch(q,le64,a)
 #define in_le32(a)	in_arch(l,le32,a)
 #define in_le16(a)	in_arch(w,le16,a)
 

arch/arm/include/asm/proc-armv/system.h

@@ -22,7 +22,7 @@
 #define local_irq_save(flags)					\
 	({							\
 	asm volatile(						\
-	"mrs	%0, daif"					\
+	"mrs	%0, daif\n"					\
 	"msr	daifset, #3"					\
 	: "=r" (flags)						\
 	:							\

arch/arm/include/asm/semihosting.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright 2014 Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SEMIHOSTING_H__
+#define __SEMIHOSTING_H__
+
+/*
+ * ARM semihosting functions for loading images to memory. See the source
+ * code for more information.
+ */
+int smh_load(const char *fname, void *memp, int avail, int verbose);
+int smh_read(int fd, void *memp, int len);
+int smh_open(const char *fname, char *modestr);
+int smh_close(int fd);
+int smh_len_fd(int fd);
+int smh_len(const char *fname);
+
+#endif /* __SEMIHOSTING_H__ */

arch/arm/include/asm/spl.h

@@ -7,9 +7,29 @@
 #ifndef	_ASM_SPL_H_
 #define	_ASM_SPL_H_
 
+#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \
+	|| defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
+	|| defined(CONFIG_EXYNOS4210)
 /* Platform-specific defines */
 #include <asm/arch/spl.h>
 
+#else
+enum {
+	BOOT_DEVICE_RAM,
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+	BOOT_DEVICE_NAND,
+	BOOT_DEVICE_ONENAND,
+	BOOT_DEVICE_NOR,
+	BOOT_DEVICE_UART,
+	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_SATA,
+	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_NONE
+};
+#endif
+
 /* Linker symbols. */
 extern char __bss_start[], __bss_end[];
 

arch/arm/include/asm/system.h

@@ -78,6 +78,8 @@ void gic_send_sgi(unsigned long sgino);
 void wait_for_wakeup(void);
 void smp_kick_all_cpus(void);
 
+void flush_l3_cache(void);
+
 #endif	/* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */