Prepare v2017.07

Signed-off-by: Tom Rini <trini@konsulko.com>

.travis.yml

@@ -60,7 +60,6 @@ env:
 
 before_script:
   # install toolchains based on TOOLCHAIN} variable
-  - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
   - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi
@@ -138,10 +137,7 @@ matrix:
     - env:
         - BUILDMAN="arm946es"
     - env:
-        - BUILDMAN="atmel -x avr32"
-    - env:
-        - BUILDMAN="avr32"
-          TOOLCHAIN="avr32"
+        - BUILDMAN="atmel"
     - env:
         - BUILDMAN="aries"
     - env:
@@ -209,6 +205,8 @@ matrix:
         - BUILDMAN="corenet_ds b4860qds sbc8548 bsc91*"
     - env:
         - BUILDMAN="mpc86xx"
+    - env:
+        - BUILDMAN="mpc8xx"
     - env:
         - BUILDMAN="siemens"
     - env:

MAINTAINERS

@@ -78,8 +78,8 @@ T:	git git://git.denx.de/u-boot-atmel.git
 F:	arch/arm/mach-at91/
 
 ARM BROADCOM BCM283X
-M:	Stephen Warren <swarren@wwwdotorg.org>
-S:	Maintained
+#M:	Stephen Warren <swarren@wwwdotorg.org>
+S:	Orphaned (Since 2017-07)
 F:	arch/arm/mach-bcm283x/
 F:	drivers/gpio/bcm2835_gpio.c
 F:	drivers/mmc/bcm2835_sdhci.c
@@ -221,12 +221,6 @@ S:	Maintained
 F:	arch/arm/cpu/armv8/zynqmp/
 F:	arch/arm/include/asm/arch-zynqmp/
 
-AVR32
-M:	Andreas Bießmann <andreas@biessmann.org>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-avr32.git
-F:	arch/avr32/
-
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
@@ -264,6 +258,7 @@ F:	test/dm/
 EFI PAYLOAD
 M:	Alexander Graf <agraf@suse.de>
 S:	Maintained
+T:	git git://github.com/agraf/u-boot.git
 F:	include/efi_loader.h
 F:	lib/efi_loader/
 F:	cmd/bootefi.c
@@ -324,7 +319,7 @@ S:	Maintained
 F:	arch/powerpc/
 
 POWERPC MPC8XX
-M:	Wolfgang Denk <wd@denx.de>
+M:	Christophe Leroy <christophe.leroy@c-s.fr>
 S:	Maintained
 T:	git git://git.denx.de/u-boot-mpc8xx.git
 F:	arch/powerpc/cpu/mpc8xx/

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

README

@@ -136,7 +136,6 @@ Directory Hierarchy:
 /arch			Architecture specific files
   /arc			Files generic to ARC architecture
   /arm			Files generic to ARM architecture
-  /avr32		Files generic to AVR32 architecture
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
@@ -320,9 +319,6 @@ The following options need to be configured:
 
 - Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
 
-- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
-		Define exactly one, e.g. CONFIG_ATSTK1002
-
 - Marvell Family Member
 		CONFIG_SYS_MVFS		- define it if you want to enable
 					  multiple fs option at one time
@@ -860,7 +856,7 @@ The following options need to be configured:
 		(configuration option CONFIG_CMD_CACHE) unless you know
 		what you (and your U-Boot users) are doing. Data
 		cache cannot be enabled on systems like the
-		8260 (where accesses to the IMMR region must be
+		8xx (where accesses to the IMMR region must be
 		uncached), and it cannot be disabled on all other
 		systems where we (mis-) use the data cache to hold an
 		initial stack and some data.
@@ -923,9 +919,11 @@ The following options need to be configured:
 		CONFIG_WATCHDOG
 		If this variable is defined, it enables watchdog
 		support for the SoC. There must be support in the SoC
-		specific code for a watchdog. When supported for a
-		specific SoC is available, then no further board specific
-		code should be needed to use it.
+		specific code for a watchdog. For the 8xx
+		CPUs, the SIU Watchdog feature is enabled in the SYPCR
+		register.  When supported for a specific SoC is
+		available, then no further board specific code should
+		be needed to use it.
 
 		CONFIG_HW_WATCHDOG
 		When using a watchdog circuitry external to the used
@@ -3936,7 +3934,7 @@ Low Level (hardware related) configuration options:
 
 - CONFIG_SYS_IMMR:	Physical address of the Internal Memory.
 		DO NOT CHANGE unless you know exactly what you're
-		doing! (11-4) [82xx systems only]
+		doing! (11-4) [MPC8xx systems only]
 
 - CONFIG_SYS_INIT_RAM_ADDR:
 
@@ -3949,6 +3947,7 @@ Low Level (hardware related) configuration options:
 		sequences.
 
 		U-Boot uses the following memory types:
+		- MPC8xx: IMMR (internal memory of the CPU)
 
 - CONFIG_SYS_GBL_DATA_OFFSET:
 
@@ -4810,9 +4809,9 @@ details; basically, the header defines the following image properties:
   LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
   Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS,
   INTEGRITY).
-* Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86,
+* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
-  Currently supported: ARM, AVR32, Intel x86, MIPS, NDS32, Nios II, PowerPC).
+  Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).
 * Compression Type (uncompressed, gzip, bzip2)
 * Load Address
 * Entry Point

api/api_platform-powerpc.c

@@ -30,7 +30,7 @@ int platform_sys_info(struct sys_info *si)
 	si->clk_bus = gd->bus_clk;
 	si->clk_cpu = gd->cpu_clk;
 
-#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar	bi_immr_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar

arch/Kconfig

@@ -23,10 +23,6 @@ config ARM
 	select HAVE_PRIVATE_LIBGCC if !ARM64
 	select SUPPORT_OF_CONTROL
 
-config AVR32
-	bool "AVR32 architecture"
-	select CREATE_ARCH_SYMLINK
-
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -166,7 +162,6 @@ config SYS_CONFIG_NAME
 
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
-source "arch/avr32/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"

arch/arm/cpu/armv8/Kconfig

@@ -92,7 +92,7 @@ config PSCI_RESET
 		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
 		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
 		   !TARGET_LS2081ARDB && \
-		   !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
+		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
 	help
 	  Most armv8 systems have PSCI support enabled in EL3, either through
 	  ARM Trusted Firmware or other firmware.

arch/arm/mach-stm32/stm32f7/soc.c

@@ -17,6 +17,8 @@ u32 get_cpu_rev(void)
 
 int arch_cpu_init(void)
 {
+	int i;
+
 	struct mpu_region_config stm32_region_config[] = {
 		{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
 		O_I_WB_RD_WR_ALLOC, REGION_4GB },
@@ -35,7 +37,7 @@ int arch_cpu_init(void)
 	};
 
 	disable_mpu();
-	for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+	for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
 		mpu_config(&stm32_region_config[i]);
 	enable_mpu();
 

arch/avr32/Kconfig

@@ -1,30 +0,0 @@
-menu "AVR32 architecture"
-	depends on AVR32
-
-config SYS_ARCH
-	default "avr32"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_ATNGW100
-	bool "Support atngw100"
-
-config TARGET_ATNGW100MKII
-	bool "Support atngw100mkii"
-
-config TARGET_ATSTK1002
-	bool "Support atstk1002"
-
-config TARGET_GRASSHOPPER
-	bool "Support grasshopper"
-
-endchoice
-
-source "board/atmel/atngw100/Kconfig"
-source "board/atmel/atngw100mkii/Kconfig"
-source "board/atmel/atstk1000/Kconfig"
-source "board/in-circuit/grasshopper/Kconfig"
-
-endmenu

arch/avr32/Makefile

@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-head-y := arch/avr32/cpu/start.o
-
-libs-y += arch/avr32/cpu/
-libs-y += arch/avr32/lib/

arch/avr32/config.mk

@@ -1,17 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := avr32-linux-
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000
-
-PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
-PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
-
-LDFLAGS_u-boot		= --gc-sections --relax

arch/avr32/cpu/Makefile

@@ -1,21 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2005-2006 Atmel Corporation.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y			+= start.o
-
-obj-y			+= cpu.o
-obj-$(CONFIG_SYS_HSDRAMC) += hsdramc.o
-obj-y			+= exception.o
-obj-y			+= cache.o
-obj-y			+= interrupts.o
-obj-$(CONFIG_PORTMUX_PIO) += portmux-pio.o
-obj-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o
-obj-y += mmc.o
-
-obj-$(if $(filter at32ap700x,$(SOC)),y) += at32ap700x/

arch/avr32/cpu/at32ap700x/Makefile

@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= portmux.o clk.o mmu.o

arch/avr32/cpu/at32ap700x/clk.c

@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2005-2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/portmux.h>
-
-#include "sm.h"
-
-void clk_init(void)
-{
-	uint32_t cksel;
-
-	/* in case of soft resets, disable watchdog */
-	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
-	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
-
-#ifdef CONFIG_PLL
-	/* Initialize the PLL */
-	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
-			    | SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
-			    | SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
-			    | SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
-			    | SM_BF(PLLOSC, 0)
-			    | SM_BIT(PLLEN)));
-
-	/* Wait for lock */
-	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
-	/* Set up clocks for the CPU and all peripheral buses */
-	cksel = 0;
-	if (CONFIG_SYS_CLKDIV_CPU)
-		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
-	if (CONFIG_SYS_CLKDIV_HSB)
-		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
-	if (CONFIG_SYS_CLKDIV_PBA)
-		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
-	if (CONFIG_SYS_CLKDIV_PBB)
-		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
-	sm_writel(PM_CKSEL, cksel);
-
-#ifdef CONFIG_PLL
-	/* Use PLL0 as main clock */
-	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-
-#ifdef CONFIG_LCD
-	/* Set up pixel clock for the LCDC */
-	sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
-#endif
-#endif
-}
-
-unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
-		unsigned long rate, unsigned long parent_rate)
-{
-	unsigned long divider;
-
-	if (rate == 0 || parent_rate == 0) {
-		sm_writel(PM_GCCTRL(id), 0);
-		return 0;
-	}
-
-	divider = (parent_rate + rate / 2) / rate;
-	if (divider <= 1) {
-		sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
-		rate = parent_rate;
-	} else {
-		divider = min(255UL, divider / 2 - 1);
-		sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
-				| SM_BF(DIV, divider));
-		rate = parent_rate / (2 * (divider + 1));
-	}
-
-	return rate;
-}

arch/avr32/cpu/at32ap700x/mmu.c

@@ -1,78 +0,0 @@
-#include <common.h>
-#include <asm/arch/mmu.h>
-#include <asm/sysreg.h>
-
-void mmu_init_r(unsigned long dest_addr)
-{
-	uintptr_t	vmr_table_addr;
-
-	/* Round monitor address down to the nearest page boundary */
-	dest_addr &= MMU_PAGE_ADDR_MASK;
-
-	/* Initialize TLB entry 0 to cover the monitor, and lock it */
-	sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
-	sysreg_write(TLBELO, dest_addr | MMU_VMR_CACHE_WRBACK);
-	sysreg_write(MMUCR, SYSREG_BF(DRP, 0) | SYSREG_BF(DLA, 1)
-			| SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M));
-	__builtin_tlbw();
-
-	/*
-	 * Calculate the address of the VM range table in a PC-relative
-	 * manner to make sure we hit the SDRAM and not the flash.
-	 */
-	vmr_table_addr = (uintptr_t)&mmu_vmr_table;
-	sysreg_write(PTBR, vmr_table_addr);
-	printf("VMR table @ 0x%08lx\n", vmr_table_addr);
-
-	/* Enable paging */
-	sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1)
-			| SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E));
-}
-
-int mmu_handle_tlb_miss(void)
-{
-	const struct mmu_vm_range *vmr_table;
-	const struct mmu_vm_range *vmr;
-	unsigned int fault_pgno;
-	int first, last;
-
-	fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
-	vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
-
-	/* Do a binary search through the VM ranges */
-	first = 0;
-	last = CONFIG_SYS_NR_VM_REGIONS;
-	while (first < last) {
-		unsigned int start;
-		int middle;
-
-		/* Pick the entry in the middle of the remaining range */
-		middle = (first + last) >> 1;
-		vmr = &vmr_table[middle];
-		start = vmr->virt_pgno;
-
-		/* Do the bisection thing */
-		if (fault_pgno < start) {
-			last = middle;
-		} else if (fault_pgno >= (start + vmr->nr_pages)) {
-			first = middle + 1;
-		} else {
-			/* Got it; let's slam it into the TLB */
-			uint32_t tlbelo;
-
-			tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
-			tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
-			sysreg_write(TLBELO, tlbelo);
-			__builtin_tlbw();
-
-			/* Zero means success */
-			return 0;
-		}
-	}
-
-	/*
-	 * Didn't find any matching entries. Return a nonzero value to
-	 * indicate that this should be treated as a fatal exception.
-	 */
-	return -1;
-}

arch/avr32/cpu/at32ap700x/portmux.c

@@ -1,278 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-
-#include <asm/arch/chip-features.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/portmux.h>
-
-/*
- * Lots of small functions here. We depend on --gc-sections getting
- * rid of the ones we don't need.
- */
-void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
-		unsigned long flags, unsigned long drive_strength)
-{
-	unsigned long porte_mask = 0;
-
-	if (bus_width > 16)
-		portmux_select_peripheral(PORTMUX_PORT_E, 0xffff,
-				PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-	if (addr_width > 23)
-		porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16;
-	if (flags & PORTMUX_EBI_CS(2))
-		porte_mask |= 1 << 25;
-	if (flags & PORTMUX_EBI_CS(4))
-		porte_mask |= 1 << 21;
-	if (flags & PORTMUX_EBI_CS(5))
-		porte_mask |= 1 << 22;
-	if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1)))
-		porte_mask |= (1 << 19) | (1 << 20) | (1 << 23);
-
-	portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
-			PORTMUX_FUNC_A, 0);
-
-	if (flags & PORTMUX_EBI_NWAIT)
-		portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24,
-				PORTMUX_FUNC_A, PORTMUX_PULL_UP);
-}
-
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength)
-{
-	unsigned long portc_mask;
-
-	portc_mask = (1 << 3)	/* TXD0	*/
-		| (1 << 4)	/* TXD1	*/
-		| (1 << 7)	/* TXEN	*/
-		| (1 << 8)	/* TXCK */
-		| (1 << 9)	/* RXD0	*/
-		| (1 << 10)	/* RXD1	*/
-		| (1 << 13)	/* RXER	*/
-		| (1 << 15)	/* RXDV	*/
-		| (1 << 16)	/* MDC	*/
-		| (1 << 17);	/* MDIO	*/
-
-	if (flags & PORTMUX_MACB_MII)
-		portc_mask |= (1 << 0)	/* COL	*/
-			| (1 << 1)	/* CRS	*/
-			| (1 << 2)	/* TXER	*/
-			| (1 << 5)	/* TXD2	*/
-			| (1 << 6)	/* TXD3 */
-			| (1 << 11)	/* RXD2	*/
-			| (1 << 12)	/* RXD3	*/
-			| (1 << 14);	/* RXCK	*/
-
-	if (flags & PORTMUX_MACB_SPEED)
-		portc_mask |= (1 << 18);/* SPD	*/
-
-	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-}
-
-void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength)
-{
-	unsigned long portc_mask = 0;
-	unsigned long portd_mask;
-
-	portd_mask = (1 << 13)	/* TXD0	*/
-		| (1 << 14)	/* TXD1	*/
-		| (1 << 11)	/* TXEN	*/
-		| (1 << 12)	/* TXCK */
-		| (1 << 10)	/* RXD0	*/
-		| (1 << 6)	/* RXD1	*/
-		| (1 << 5)	/* RXER	*/
-		| (1 << 4)	/* RXDV	*/
-		| (1 << 3)	/* MDC	*/
-		| (1 << 2);	/* MDIO	*/
-
-	if (flags & PORTMUX_MACB_MII)
-		portc_mask = (1 << 19)	/* COL	*/
-			| (1 << 23)	/* CRS	*/
-			| (1 << 26)	/* TXER	*/
-			| (1 << 27)	/* TXD2	*/
-			| (1 << 28)	/* TXD3 */
-			| (1 << 29)	/* RXD2	*/
-			| (1 << 30)	/* RXD3	*/
-			| (1 << 24);	/* RXCK	*/
-
-	if (flags & PORTMUX_MACB_SPEED)
-		portd_mask |= (1 << 15);/* SPD	*/
-
-	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void portmux_enable_mmci(unsigned int slot, unsigned long flags,
-		unsigned long drive_strength)
-{
-	unsigned long mask;
-	unsigned long portmux_flags = PORTMUX_PULL_UP;
-
-	/* First, the common CLK signal. It doesn't need a pull-up */
-	portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10,
-			PORTMUX_FUNC_A, 0);
-
-	if (flags & PORTMUX_MMCI_EXT_PULLUP)
-		portmux_flags = 0;
-
-	/* Then, the per-slot signals */
-	switch (slot) {
-	case 0:
-		mask = (1 << 11) | (1 << 12);	/* CMD and DATA0 */
-		if (flags & PORTMUX_MMCI_4BIT)
-			/* DATA1..DATA3 */
-			mask |= (1 << 13) | (1 << 14) | (1 << 15);
-		portmux_select_peripheral(PORTMUX_PORT_A, mask,
-				PORTMUX_FUNC_A, portmux_flags);
-		break;
-	case 1:
-		mask = (1 << 6) | (1 << 7);	/* CMD and DATA0 */
-		if (flags & PORTMUX_MMCI_4BIT)
-			/* DATA1..DATA3 */
-			mask |= (1 << 8) | (1 << 9) | (1 << 10);
-		portmux_select_peripheral(PORTMUX_PORT_B, mask,
-				PORTMUX_FUNC_B, portmux_flags);
-		break;
-	}
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength)
-{
-	unsigned long pin_mask;
-
-	/* MOSI and SCK */
-	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2),
-			PORTMUX_FUNC_A, 0);
-	/* MISO may float */
-	portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-
-	/* Set up NPCSx as GPIO outputs, initially high */
-	pin_mask = (cs_mask & 7) << 3;
-	if (cs_mask & (1 << 3))
-		pin_mask |= 1 << 20;
-
-	portmux_select_gpio(PORTMUX_PORT_A, pin_mask,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-}
-
-void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength)
-{
-	/* MOSI and SCK */
-	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5),
-			PORTMUX_FUNC_B, 0);
-	/* MISO may float */
-	portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-
-	/* Set up NPCSx as GPIO outputs, initially high */
-	portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-	portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3),
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
-}
-#endif
-
-#ifdef AT32AP700x_CHIP_HAS_LCDC
-void portmux_enable_lcdc(int pin_config)
-{
-	unsigned long portc_mask = 0;
-	unsigned long portd_mask = 0;
-	unsigned long porte_mask = 0;
-
-	switch (pin_config) {
-	case 0:
-		portc_mask = (1 << 19)	/* CC     */
-			| (1 << 20)	/* HSYNC  */
-			| (1 << 21)	/* PCLK   */
-			| (1 << 22)	/* VSYNC  */
-			| (1 << 23)	/* DVAL   */
-			| (1 << 24)	/* MODE   */
-			| (1 << 25)	/* PWR    */
-			| (1 << 26)	/* DATA0  */
-			| (1 << 27)	/* DATA1  */
-			| (1 << 28)	/* DATA2  */
-			| (1 << 29)	/* DATA3  */
-			| (1 << 30)	/* DATA4  */
-			| (1 << 31);	/* DATA5  */
-
-		portd_mask = (1 << 0)	/* DATA6  */
-			| (1 << 1)	/* DATA7  */
-			| (1 << 2)	/* DATA8  */
-			| (1 << 3)	/* DATA9  */
-			| (1 << 4)	/* DATA10 */
-			| (1 << 5)	/* DATA11 */
-			| (1 << 6)	/* DATA12 */
-			| (1 << 7)	/* DATA13 */
-			| (1 << 8)	/* DATA14 */
-			| (1 << 9)	/* DATA15 */
-			| (1 << 10)	/* DATA16 */
-			| (1 << 11)	/* DATA17 */
-			| (1 << 12)	/* DATA18 */
-			| (1 << 13)	/* DATA19 */
-			| (1 << 14)	/* DATA20 */
-			| (1 << 15)	/* DATA21 */
-			| (1 << 16)	/* DATA22 */
-			| (1 << 17);	/* DATA23 */
-		break;
-
-	case 1:
-		portc_mask = (1 << 20)	/* HSYNC  */
-			| (1 << 21)	/* PCLK   */
-			| (1 << 22)	/* VSYNC  */
-			| (1 << 25)	/* PWR    */
-			| (1 << 31);	/* DATA5  */
-
-		portd_mask = (1 << 0)	/* DATA6  */
-			| (1 << 1)	/* DATA7  */
-			| (1 << 7)	/* DATA13 */
-			| (1 << 8)	/* DATA14 */
-			| (1 << 9)	/* DATA15 */
-			| (1 << 16)	/* DATA22 */
-			| (1 << 17);	/* DATA23 */
-
-		porte_mask = (1 << 0)	/* CC     */
-			| (1 << 1)	/* DVAL   */
-			| (1 << 2)	/* MODE   */
-			| (1 << 3)	/* DATA0  */
-			| (1 << 4)	/* DATA1  */
-			| (1 << 5)	/* DATA2  */
-			| (1 << 6)	/* DATA3  */
-			| (1 << 7)	/* DATA4  */
-			| (1 << 8)	/* DATA8  */
-			| (1 << 9)	/* DATA9  */
-			| (1 << 10)	/* DATA10 */
-			| (1 << 11)	/* DATA11 */
-			| (1 << 12)	/* DATA12 */
-			| (1 << 13)	/* DATA16 */
-			| (1 << 14)	/* DATA17 */
-			| (1 << 15)	/* DATA18 */
-			| (1 << 16)	/* DATA19 */
-			| (1 << 17)	/* DATA20 */
-			| (1 << 18);	/* DATA21 */
-		break;
-	}
-
-	/* REVISIT: Some pins are probably pure outputs */
-	portmux_select_peripheral(PORTMUX_PORT_C, portc_mask,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-	portmux_select_peripheral(PORTMUX_PORT_D, portd_mask,
-			PORTMUX_FUNC_A, PORTMUX_BUSKEEPER);
-	portmux_select_peripheral(PORTMUX_PORT_E, porte_mask,
-			PORTMUX_FUNC_B, PORTMUX_BUSKEEPER);
-}
-#endif

arch/avr32/cpu/at32ap700x/sm.h

@@ -1,204 +0,0 @@
-/*
- * Register definitions for System Manager
- */
-#ifndef __CPU_AT32AP_SM_H__
-#define __CPU_AT32AP_SM_H__
-
-/* SM register offsets */
-#define SM_PM_MCCTRL				0x0000
-#define SM_PM_CKSEL				0x0004
-#define SM_PM_CPU_MASK				0x0008
-#define SM_PM_HSB_MASK				0x000c
-#define SM_PM_PBA_MASK				0x0010
-#define SM_PM_PBB_MASK				0x0014
-#define SM_PM_PLL0				0x0020
-#define SM_PM_PLL1				0x0024
-#define SM_PM_VCTRL				0x0030
-#define SM_PM_VMREF				0x0034
-#define SM_PM_VMV				0x0038
-#define SM_PM_IER				0x0040
-#define SM_PM_IDR				0x0044
-#define SM_PM_IMR				0x0048
-#define SM_PM_ISR				0x004c
-#define SM_PM_ICR				0x0050
-#define SM_PM_GCCTRL(x)				(0x0060 + 4 * x)
-#define SM_RTC_CTRL				0x0080
-#define SM_RTC_VAL				0x0084
-#define SM_RTC_TOP				0x0088
-#define SM_RTC_IER				0x0090
-#define SM_RTC_IDR				0x0094
-#define SM_RTC_IMR				0x0098
-#define SM_RTC_ISR				0x009c
-#define SM_RTC_ICR				0x00a0
-#define SM_WDT_CTRL				0x00b0
-#define SM_WDT_CLR				0x00b4
-#define SM_WDT_EXT				0x00b8
-#define SM_RC_RCAUSE				0x00c0
-#define SM_EIM_IER				0x0100
-#define SM_EIM_IDR				0x0104
-#define SM_EIM_IMR				0x0108
-#define SM_EIM_ISR				0x010c
-#define SM_EIM_ICR				0x0110
-#define SM_EIM_MODE				0x0114
-#define SM_EIM_EDGE				0x0118
-#define SM_EIM_LEVEL				0x011c
-#define SM_EIM_TEST				0x0120
-#define SM_EIM_NMIC				0x0124
-
-/* Bitfields in PM_CKSEL */
-#define SM_CPUSEL_OFFSET			0
-#define SM_CPUSEL_SIZE				3
-#define SM_CPUDIV_OFFSET			7
-#define SM_CPUDIV_SIZE				1
-#define SM_HSBSEL_OFFSET			8
-#define SM_HSBSEL_SIZE				3
-#define SM_HSBDIV_OFFSET			15
-#define SM_HSBDIV_SIZE				1
-#define SM_PBASEL_OFFSET			16
-#define SM_PBASEL_SIZE				3
-#define SM_PBADIV_OFFSET			23
-#define SM_PBADIV_SIZE				1
-#define SM_PBBSEL_OFFSET			24
-#define SM_PBBSEL_SIZE				3
-#define SM_PBBDIV_OFFSET			31
-#define SM_PBBDIV_SIZE				1
-
-/* Bitfields in PM_PLL0 */
-#define SM_PLLEN_OFFSET				0
-#define SM_PLLEN_SIZE				1
-#define SM_PLLOSC_OFFSET			1
-#define SM_PLLOSC_SIZE				1
-#define SM_PLLOPT_OFFSET			2
-#define SM_PLLOPT_SIZE				3
-#define SM_PLLDIV_OFFSET			8
-#define SM_PLLDIV_SIZE				8
-#define SM_PLLMUL_OFFSET			16
-#define SM_PLLMUL_SIZE				8
-#define SM_PLLCOUNT_OFFSET			24
-#define SM_PLLCOUNT_SIZE			6
-#define SM_PLLTEST_OFFSET			31
-#define SM_PLLTEST_SIZE				1
-
-/* Bitfields in PM_VCTRL */
-#define SM_VAUTO_OFFSET				0
-#define SM_VAUTO_SIZE				1
-#define SM_PM_VCTRL_VAL_OFFSET			8
-#define SM_PM_VCTRL_VAL_SIZE			7
-
-/* Bitfields in PM_VMREF */
-#define SM_REFSEL_OFFSET			0
-#define SM_REFSEL_SIZE				4
-
-/* Bitfields in PM_VMV */
-#define SM_PM_VMV_VAL_OFFSET			0
-#define SM_PM_VMV_VAL_SIZE			8
-
-/* Bitfields in PM_ICR */
-#define SM_LOCK0_OFFSET				0
-#define SM_LOCK0_SIZE				1
-#define SM_LOCK1_OFFSET				1
-#define SM_LOCK1_SIZE				1
-#define SM_WAKE_OFFSET				2
-#define SM_WAKE_SIZE				1
-#define SM_VOK_OFFSET				3
-#define SM_VOK_SIZE				1
-#define SM_VMRDY_OFFSET				4
-#define SM_VMRDY_SIZE				1
-#define SM_CKRDY_OFFSET				5
-#define SM_CKRDY_SIZE				1
-
-/* Bitfields in PM_GCCTRL */
-#define SM_OSCSEL_OFFSET			0
-#define SM_OSCSEL_SIZE				1
-#define SM_PLLSEL_OFFSET			1
-#define SM_PLLSEL_SIZE				1
-#define SM_CEN_OFFSET				2
-#define SM_CEN_SIZE				1
-#define SM_CPC_OFFSET				3
-#define SM_CPC_SIZE				1
-#define SM_DIVEN_OFFSET				4
-#define SM_DIVEN_SIZE				1
-#define SM_DIV_OFFSET				8
-#define SM_DIV_SIZE				8
-
-/* Bitfields in RTC_CTRL */
-#define SM_PCLR_OFFSET				1
-#define SM_PCLR_SIZE				1
-#define SM_TOPEN_OFFSET				2
-#define SM_TOPEN_SIZE				1
-#define SM_CLKEN_OFFSET				3
-#define SM_CLKEN_SIZE				1
-#define SM_PSEL_OFFSET				8
-#define SM_PSEL_SIZE				16
-
-/* Bitfields in RTC_VAL */
-#define SM_RTC_VAL_VAL_OFFSET			0
-#define SM_RTC_VAL_VAL_SIZE			31
-
-/* Bitfields in RTC_TOP */
-#define SM_RTC_TOP_VAL_OFFSET			0
-#define SM_RTC_TOP_VAL_SIZE			32
-
-/* Bitfields in RTC_ICR */
-#define SM_TOPI_OFFSET				0
-#define SM_TOPI_SIZE				1
-
-/* Bitfields in WDT_CTRL */
-#define SM_KEY_OFFSET				24
-#define SM_KEY_SIZE				8
-
-/* Bitfields in RC_RCAUSE */
-#define SM_POR_OFFSET				0
-#define SM_POR_SIZE				1
-#define SM_BOD_OFFSET				1
-#define SM_BOD_SIZE				1
-#define SM_EXT_OFFSET				2
-#define SM_EXT_SIZE				1
-#define SM_WDT_OFFSET				3
-#define SM_WDT_SIZE				1
-#define SM_NTAE_OFFSET				4
-#define SM_NTAE_SIZE				1
-#define SM_SERP_OFFSET				5
-#define SM_SERP_SIZE				1
-
-/* Bitfields in EIM_EDGE */
-#define SM_INT0_OFFSET				0
-#define SM_INT0_SIZE				1
-#define SM_INT1_OFFSET				1
-#define SM_INT1_SIZE				1
-#define SM_INT2_OFFSET				2
-#define SM_INT2_SIZE				1
-#define SM_INT3_OFFSET				3
-#define SM_INT3_SIZE				1
-
-/* Bitfields in EIM_LEVEL */
-
-/* Bitfields in EIM_TEST */
-#define SM_TESTEN_OFFSET			31
-#define SM_TESTEN_SIZE				1
-
-/* Bitfields in EIM_NMIC */
-#define SM_EN_OFFSET				0
-#define SM_EN_SIZE				1
-
-/* Bit manipulation macros */
-#define SM_BIT(name)					\
-	(1 << SM_##name##_OFFSET)
-#define SM_BF(name,value)				\
-	(((value) & ((1 << SM_##name##_SIZE) - 1))	\
-	 << SM_##name##_OFFSET)
-#define SM_BFEXT(name,value)				\
-	(((value) >> SM_##name##_OFFSET)		\
-	 & ((1 << SM_##name##_SIZE) - 1))
-#define SM_BFINS(name,value,old)			\
-	(((old) & ~(((1 << SM_##name##_SIZE) - 1)	\
-		    << SM_##name##_OFFSET))		\
-	 | SM_BF(name,value))
-
-/* Register access macros */
-#define sm_readl(reg)					\
-	readl((void *)ATMEL_BASE_SM + SM_##reg)
-#define sm_writel(reg,value)				\
-	writel((value), (void *)ATMEL_BASE_SM + SM_##reg)
-
-#endif /* __CPU_AT32AP_SM_H__ */

arch/avr32/cpu/cache.c

@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-#include <asm/arch/cacheflush.h>
-
-void dcache_clean_range(volatile void *start, size_t size)
-{
-	unsigned long v, begin, end, linesz;
-
-	linesz = CONFIG_SYS_DCACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	begin = (unsigned long)start & ~(linesz - 1);
-	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
-
-	for (v = begin; v < end; v += linesz)
-		dcache_clean_line((void *)v);
-
-	sync_write_buffer();
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-	unsigned long v, linesz;
-
-	linesz = CONFIG_SYS_DCACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	start = start & ~(linesz - 1);
-	stop = (stop + linesz - 1) & ~(linesz - 1);
-
-	for (v = start; v < stop; v += linesz)
-		dcache_invalidate_line((void *)v);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-	unsigned long v, linesz;
-
-	linesz = CONFIG_SYS_DCACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	start = start & ~(linesz - 1);
-	stop = (stop + linesz - 1) & ~(linesz - 1);
-
-	for (v = start; v < stop; v += linesz)
-		dcache_flush_line((void *)v);
-
-	sync_write_buffer();
-}
-
-void icache_invalidate_range(volatile void *start, size_t size)
-{
-	unsigned long v, begin, end, linesz;
-
-	linesz = CONFIG_SYS_ICACHE_LINESZ;
-
-	/* You asked for it, you got it */
-	begin = (unsigned long)start & ~(linesz - 1);
-	end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
-
-	for (v = begin; v < end; v += linesz)
-		icache_invalidate_line((void *)v);
-}
-
-/*
- * This is called after loading something into memory.  We need to
- * make sure that everything that was loaded is actually written to
- * RAM, and that the icache will look for it. Cleaning the dcache and
- * invalidating the icache will do the trick.
- */
-void  flush_cache (unsigned long start_addr, unsigned long size)
-{
-	dcache_clean_range((void *)start_addr, size);
-	icache_invalidate_range((void *)start_addr, size);
-}

arch/avr32/cpu/config.mk

@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-PLATFORM_RELFLAGS       += -mcpu=ap7000

arch/avr32/cpu/cpu.c

@@ -1,73 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-
-#include <asm/io.h>
-#include <asm/sections.h>
-#include <asm/sysreg.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-
-#include "hsmc3.h"
-
-/* Sanity checks */
-#if (CONFIG_SYS_CLKDIV_CPU > CONFIG_SYS_CLKDIV_HSB)		\
-	|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBA)	\
-	|| (CONFIG_SYS_CLKDIV_HSB > CONFIG_SYS_CLKDIV_PBB)
-# error Constraint fCPU >= fHSB >= fPB{A,B} violated
-#endif
-#if defined(CONFIG_PLL) && ((CONFIG_SYS_PLL0_MUL < 1) || (CONFIG_SYS_PLL0_DIV < 1))
-# error Invalid PLL multiplier and/or divider
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int arch_cpu_init(void)
-{
-	extern void _evba(void);
-
-	gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
-
-	/* TODO: Move somewhere else, but needs to be run before we
-	 * increase the clock frequency. */
-	hsmc3_writel(MODE0, 0x00031103);
-	hsmc3_writel(CYCLE0, 0x000c000d);
-	hsmc3_writel(PULSE0, 0x0b0a0906);
-	hsmc3_writel(SETUP0, 0x00010002);
-
-	clk_init();
-
-	/* Update the CPU speed according to the PLL configuration */
-	gd->arch.cpu_hz = get_cpu_clk_rate();
-
-	/* Set up the exception handler table and enable exceptions */
-	sysreg_write(EVBA, (unsigned long)&_evba);
-	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
-
-	return 0;
-}
-
-void prepare_to_boot(void)
-{
-	/* Flush both caches and the write buffer */
-	asm volatile("cache  %0[4], 010\n\t"
-		     "cache  %0[0], 000\n\t"
-		     "sync   0" : : "r"(0) : "memory");
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	/* This will reset the CPU core, caches, MMU and all internal busses */
-	__builtin_mtdr(8, 1 << 13);	/* set DC:DBE */
-	__builtin_mtdr(8, 1 << 30);	/* set DC:RES */
-
-	/* Flush the pipeline before we declare it a failure */
-	asm volatile("sub   pc, pc, -4");
-
-	return -1;
-}

arch/avr32/cpu/exception.c

@@ -1,108 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/sysreg.h>
-#include <asm/ptrace.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define STACKSIZE	2048
-
-static const char * const cpu_modes[8] = {
-	"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
-	"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
-};
-
-static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
-{
-	unsigned long p;
-	int i;
-
-	printf("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
-
-	for (p = bottom & ~31; p < top; ) {
-		printf("%04lx: ", p & 0xffff);
-
-		for (i = 0; i < 8; i++, p += 4) {
-			unsigned int val;
-
-			if (p < bottom || p >= top)
-				printf("         ");
-			else {
-				val = *(unsigned long *)p;
-				printf("%08x ", val);
-			}
-		}
-		printf("\n");
-	}
-}
-
-void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
-{
-	unsigned int mode;
-
-	printf("\n *** Unhandled exception %u at PC=0x%08lx [%08lx]\n",
-			ecr, regs->pc, regs->pc - gd->reloc_off);
-
-	switch (ecr) {
-	case ECR_BUS_ERROR_WRITE:
-	case ECR_BUS_ERROR_READ:
-		printf("Bus error at address 0x%08lx\n",
-		       sysreg_read(BEAR));
-		break;
-	case ECR_TLB_MULTIPLE:
-	case ECR_ADDR_ALIGN_X:
-	case ECR_PROTECTION_X:
-	case ECR_ADDR_ALIGN_R:
-	case ECR_ADDR_ALIGN_W:
-	case ECR_PROTECTION_R:
-	case ECR_PROTECTION_W:
-	case ECR_DTLB_MODIFIED:
-	case ECR_TLB_MISS_X:
-	case ECR_TLB_MISS_R:
-	case ECR_TLB_MISS_W:
-		printf("MMU exception at address 0x%08lx\n",
-		       sysreg_read(TLBEAR));
-		break;
-	}
-
-	printf("   pc: %08lx    lr: %08lx    sp: %08lx   r12: %08lx\n",
-	       regs->pc, regs->lr, regs->sp, regs->r12);
-	printf("  r11: %08lx   r10: %08lx    r9: %08lx    r8: %08lx\n",
-	       regs->r11, regs->r10, regs->r9, regs->r8);
-	printf("   r7: %08lx    r6: %08lx    r5: %08lx    r4: %08lx\n",
-	       regs->r7, regs->r6, regs->r5, regs->r4);
-	printf("   r3: %08lx    r2: %08lx    r1: %08lx    r0: %08lx\n",
-	       regs->r3, regs->r2, regs->r1, regs->r0);
-	printf("Flags: %c%c%c%c%c\n",
-	       regs->sr & SR_Q ? 'Q' : 'q',
-	       regs->sr & SR_V ? 'V' : 'v',
-	       regs->sr & SR_N ? 'N' : 'n',
-	       regs->sr & SR_Z ? 'Z' : 'z',
-	       regs->sr & SR_C ? 'C' : 'c');
-	printf("Mode bits: %c%c%c%c%c%c%c%c%c\n",
-	       regs->sr & SR_H ? 'H' : 'h',
-	       regs->sr & SR_R ? 'R' : 'r',
-	       regs->sr & SR_J ? 'J' : 'j',
-	       regs->sr & SR_EM ? 'E' : 'e',
-	       regs->sr & SR_I3M ? '3' : '.',
-	       regs->sr & SR_I2M ? '2' : '.',
-	       regs->sr & SR_I1M ? '1' : '.',
-	       regs->sr & SR_I0M ? '0' : '.',
-	       regs->sr & SR_GM ? 'G' : 'g');
-	mode = (regs->sr >> SYSREG_M0_OFFSET) & 7;
-	printf("CPU Mode: %s\n", cpu_modes[mode]);
-
-	/* Avoid exception loops */
-	if (regs->sp < (gd->start_addr_sp - STACKSIZE) ||
-	    regs->sp >= gd->start_addr_sp)
-		printf("\nStack pointer seems bogus, won't do stack dump\n");
-	else
-		dump_mem("\nStack: ", regs->sp, gd->start_addr_sp);
-
-	panic("Unhandled exception\n");
-}

arch/avr32/cpu/hsdramc.c

@@ -1,101 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-
-#include "hsdramc1.h"
-
-unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
-{
-	unsigned long sdram_size;
-	uint32_t cfgreg;
-	unsigned int i;
-
-	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
-		       | HSDRAMC1_BF(NR, config->row_bits - 11)
-		       | HSDRAMC1_BF(NB, config->bank_bits - 1)
-		       | HSDRAMC1_BF(CAS, config->cas)
-		       | HSDRAMC1_BF(TWR, config->twr)
-		       | HSDRAMC1_BF(TRC, config->trc)
-		       | HSDRAMC1_BF(TRP, config->trp)
-		       | HSDRAMC1_BF(TRCD, config->trcd)
-		       | HSDRAMC1_BF(TRAS, config->tras)
-		       | HSDRAMC1_BF(TXSR, config->txsr));
-
-	if (config->data_bits == SDRAM_DATA_16BIT)
-		cfgreg |= HSDRAMC1_BIT(DBW);
-
-	hsdramc1_writel(CR, cfgreg);
-
-	/* Send a NOP to turn on the clock (necessary on some chips) */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * Initialization sequence for SDRAM, from the data sheet:
-	 *
-	 * 1. A minimum pause of 200 us is provided to precede any
-	 *    signal toggle.
-	 */
-	udelay(200);
-
-	/*
-	 * 2. A Precharge All command is issued to the SDRAM
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * 3. Eight auto-refresh (CBR) cycles are provided
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
-	hsdramc1_readl(MR);
-	for (i = 0; i < 8; i++)
-		writel(0, sdram_base);
-
-	/*
-	 * 4. A mode register set (MRS) cycle is issued to program
-	 *    SDRAM parameters, in particular CAS latency and burst
-	 *    length.
-	 *
-	 * The address will be chosen by the SDRAMC automatically; we
-	 * just have to make sure BA[1:0] are set to 0.
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * 5. The application must go into Normal Mode, setting Mode
-	 *    to 0 in the Mode Register and performing a write access
-	 *    at any location in the SDRAM.
-	 */
-	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
-	hsdramc1_readl(MR);
-	writel(0, sdram_base);
-
-	/*
-	 * 6. Write refresh rate into SDRAMC refresh timer count
-	 *    register (refresh rate = timing between refresh cycles).
-	 */
-	hsdramc1_writel(TR, config->refresh_period);
-
-	if (config->data_bits == SDRAM_DATA_16BIT)
-		sdram_size = 1 << (config->row_bits + config->col_bits
-				   + config->bank_bits + 1);
-	else
-		sdram_size = 1 << (config->row_bits + config->col_bits
-				   + config->bank_bits + 2);
-
-	return sdram_size;
-}

arch/avr32/cpu/hsdramc1.h

@@ -1,143 +0,0 @@
-/*
- * Register definitions for SDRAM Controller
- */
-#ifndef __ASM_AVR32_HSDRAMC1_H__
-#define __ASM_AVR32_HSDRAMC1_H__
-
-/* HSDRAMC1 register offsets */
-#define HSDRAMC1_MR				0x0000
-#define HSDRAMC1_TR				0x0004
-#define HSDRAMC1_CR				0x0008
-#define HSDRAMC1_HSR				0x000c
-#define HSDRAMC1_LPR				0x0010
-#define HSDRAMC1_IER				0x0014
-#define HSDRAMC1_IDR				0x0018
-#define HSDRAMC1_IMR				0x001c
-#define HSDRAMC1_ISR				0x0020
-#define HSDRAMC1_MDR				0x0024
-#define HSDRAMC1_VERSION			0x00fc
-
-/* Bitfields in MR */
-#define HSDRAMC1_MODE_OFFSET			0
-#define HSDRAMC1_MODE_SIZE			3
-
-/* Bitfields in TR */
-#define HSDRAMC1_COUNT_OFFSET			0
-#define HSDRAMC1_COUNT_SIZE			12
-
-/* Bitfields in CR */
-#define HSDRAMC1_NC_OFFSET			0
-#define HSDRAMC1_NC_SIZE			2
-#define HSDRAMC1_NR_OFFSET			2
-#define HSDRAMC1_NR_SIZE			2
-#define HSDRAMC1_NB_OFFSET			4
-#define HSDRAMC1_NB_SIZE			1
-#define HSDRAMC1_CAS_OFFSET			5
-#define HSDRAMC1_CAS_SIZE			2
-#define HSDRAMC1_DBW_OFFSET			7
-#define HSDRAMC1_DBW_SIZE			1
-#define HSDRAMC1_TWR_OFFSET			8
-#define HSDRAMC1_TWR_SIZE			4
-#define HSDRAMC1_TRC_OFFSET			12
-#define HSDRAMC1_TRC_SIZE			4
-#define HSDRAMC1_TRP_OFFSET			16
-#define HSDRAMC1_TRP_SIZE			4
-#define HSDRAMC1_TRCD_OFFSET			20
-#define HSDRAMC1_TRCD_SIZE			4
-#define HSDRAMC1_TRAS_OFFSET			24
-#define HSDRAMC1_TRAS_SIZE			4
-#define HSDRAMC1_TXSR_OFFSET			28
-#define HSDRAMC1_TXSR_SIZE			4
-
-/* Bitfields in HSR */
-#define HSDRAMC1_DA_OFFSET			0
-#define HSDRAMC1_DA_SIZE			1
-
-/* Bitfields in LPR */
-#define HSDRAMC1_LPCB_OFFSET			0
-#define HSDRAMC1_LPCB_SIZE			2
-#define HSDRAMC1_PASR_OFFSET			4
-#define HSDRAMC1_PASR_SIZE			3
-#define HSDRAMC1_TCSR_OFFSET			8
-#define HSDRAMC1_TCSR_SIZE			2
-#define HSDRAMC1_DS_OFFSET			10
-#define HSDRAMC1_DS_SIZE			2
-#define HSDRAMC1_TIMEOUT_OFFSET			12
-#define HSDRAMC1_TIMEOUT_SIZE			2
-
-/* Bitfields in IDR */
-#define HSDRAMC1_RES_OFFSET			0
-#define HSDRAMC1_RES_SIZE			1
-
-/* Bitfields in MDR */
-#define HSDRAMC1_MD_OFFSET			0
-#define HSDRAMC1_MD_SIZE			2
-
-/* Bitfields in VERSION */
-#define HSDRAMC1_VERSION_OFFSET			0
-#define HSDRAMC1_VERSION_SIZE			12
-#define HSDRAMC1_MFN_OFFSET			16
-#define HSDRAMC1_MFN_SIZE			3
-
-/* Constants for MODE */
-#define HSDRAMC1_MODE_NORMAL			0
-#define HSDRAMC1_MODE_NOP			1
-#define HSDRAMC1_MODE_BANKS_PRECHARGE		2
-#define HSDRAMC1_MODE_LOAD_MODE			3
-#define HSDRAMC1_MODE_AUTO_REFRESH		4
-#define HSDRAMC1_MODE_EXT_LOAD_MODE		5
-#define HSDRAMC1_MODE_POWER_DOWN		6
-
-/* Constants for NC */
-#define HSDRAMC1_NC_8_COLUMN_BITS		0
-#define HSDRAMC1_NC_9_COLUMN_BITS		1
-#define HSDRAMC1_NC_10_COLUMN_BITS		2
-#define HSDRAMC1_NC_11_COLUMN_BITS		3
-
-/* Constants for NR */
-#define HSDRAMC1_NR_11_ROW_BITS			0
-#define HSDRAMC1_NR_12_ROW_BITS			1
-#define HSDRAMC1_NR_13_ROW_BITS			2
-
-/* Constants for NB */
-#define HSDRAMC1_NB_TWO_BANKS			0
-#define HSDRAMC1_NB_FOUR_BANKS			1
-
-/* Constants for CAS */
-#define HSDRAMC1_CAS_ONE_CYCLE			1
-#define HSDRAMC1_CAS_TWO_CYCLES			2
-
-/* Constants for DBW */
-#define HSDRAMC1_DBW_32_BITS			0
-#define HSDRAMC1_DBW_16_BITS			1
-
-/* Constants for TIMEOUT */
-#define HSDRAMC1_TIMEOUT_AFTER_END		0
-#define HSDRAMC1_TIMEOUT_64_CYC_AFTER_END	1
-#define HSDRAMC1_TIMEOUT_128_CYC_AFTER_END	2
-
-/* Constants for MD */
-#define HSDRAMC1_MD_SDRAM			0
-#define HSDRAMC1_MD_LOW_POWER_SDRAM		1
-
-/* Bit manipulation macros */
-#define HSDRAMC1_BIT(name)					\
-	(1 << HSDRAMC1_##name##_OFFSET)
-#define HSDRAMC1_BF(name,value)					\
-	(((value) & ((1 << HSDRAMC1_##name##_SIZE) - 1))	\
-	 << HSDRAMC1_##name##_OFFSET)
-#define HSDRAMC1_BFEXT(name,value)				\
-	(((value) >> HSDRAMC1_##name##_OFFSET)			\
-	 & ((1 << HSDRAMC1_##name##_SIZE) - 1))
-#define HSDRAMC1_BFINS(name,value,old)				\
-	(((old) & ~(((1 << HSDRAMC1_##name##_SIZE) - 1)		\
-		    << HSDRAMC1_##name##_OFFSET))		\
-	 | HSDRAMC1_BF(name,value))
-
-/* Register access macros */
-#define hsdramc1_readl(reg)					\
-	readl((void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg)
-#define hsdramc1_writel(reg,value)				\
-	writel((value), (void *)ATMEL_BASE_HSDRAMC + HSDRAMC1_##reg)
-
-#endif /* __ASM_AVR32_HSDRAMC1_H__ */

arch/avr32/cpu/hsmc3.h

@@ -1,126 +0,0 @@
-/*
- * Register definitions for Static Memory Controller
- */
-#ifndef __CPU_AT32AP_HSMC3_H__
-#define __CPU_AT32AP_HSMC3_H__
-
-/* HSMC3 register offsets */
-#define HSMC3_SETUP0				0x0000
-#define HSMC3_PULSE0				0x0004
-#define HSMC3_CYCLE0				0x0008
-#define HSMC3_MODE0				0x000c
-#define HSMC3_SETUP1				0x0010
-#define HSMC3_PULSE1				0x0014
-#define HSMC3_CYCLE1				0x0018
-#define HSMC3_MODE1				0x001c
-#define HSMC3_SETUP2				0x0020
-#define HSMC3_PULSE2				0x0024
-#define HSMC3_CYCLE2				0x0028
-#define HSMC3_MODE2				0x002c
-#define HSMC3_SETUP3				0x0030
-#define HSMC3_PULSE3				0x0034
-#define HSMC3_CYCLE3				0x0038
-#define HSMC3_MODE3				0x003c
-#define HSMC3_SETUP4				0x0040
-#define HSMC3_PULSE4				0x0044
-#define HSMC3_CYCLE4				0x0048
-#define HSMC3_MODE4				0x004c
-#define HSMC3_SETUP5				0x0050
-#define HSMC3_PULSE5				0x0054
-#define HSMC3_CYCLE5				0x0058
-#define HSMC3_MODE5				0x005c
-
-/* Bitfields in SETUP0 */
-#define HSMC3_NWE_SETUP_OFFSET			0
-#define HSMC3_NWE_SETUP_SIZE			6
-#define HSMC3_NCS_WR_SETUP_OFFSET		8
-#define HSMC3_NCS_WR_SETUP_SIZE			6
-#define HSMC3_NRD_SETUP_OFFSET			16
-#define HSMC3_NRD_SETUP_SIZE			6
-#define HSMC3_NCS_RD_SETUP_OFFSET		24
-#define HSMC3_NCS_RD_SETUP_SIZE			6
-
-/* Bitfields in PULSE0 */
-#define HSMC3_NWE_PULSE_OFFSET			0
-#define HSMC3_NWE_PULSE_SIZE			7
-#define HSMC3_NCS_WR_PULSE_OFFSET		8
-#define HSMC3_NCS_WR_PULSE_SIZE			7
-#define HSMC3_NRD_PULSE_OFFSET			16
-#define HSMC3_NRD_PULSE_SIZE			7
-#define HSMC3_NCS_RD_PULSE_OFFSET		24
-#define HSMC3_NCS_RD_PULSE_SIZE			7
-
-/* Bitfields in CYCLE0 */
-#define HSMC3_NWE_CYCLE_OFFSET			0
-#define HSMC3_NWE_CYCLE_SIZE			9
-#define HSMC3_NRD_CYCLE_OFFSET			16
-#define HSMC3_NRD_CYCLE_SIZE			9
-
-/* Bitfields in MODE0 */
-#define HSMC3_READ_MODE_OFFSET			0
-#define HSMC3_READ_MODE_SIZE			1
-#define HSMC3_WRITE_MODE_OFFSET			1
-#define HSMC3_WRITE_MODE_SIZE			1
-#define HSMC3_EXNW_MODE_OFFSET			4
-#define HSMC3_EXNW_MODE_SIZE			2
-#define HSMC3_BAT_OFFSET			8
-#define HSMC3_BAT_SIZE				1
-#define HSMC3_DBW_OFFSET			12
-#define HSMC3_DBW_SIZE				2
-#define HSMC3_TDF_CYCLES_OFFSET			16
-#define HSMC3_TDF_CYCLES_SIZE			4
-#define HSMC3_TDF_MODE_OFFSET			20
-#define HSMC3_TDF_MODE_SIZE			1
-#define HSMC3_PMEN_OFFSET			24
-#define HSMC3_PMEN_SIZE				1
-#define HSMC3_PS_OFFSET				28
-#define HSMC3_PS_SIZE				2
-
-/* Bitfields in MODE1 */
-#define HSMC3_PD_OFFSET				28
-#define HSMC3_PD_SIZE				2
-
-/* Constants for READ_MODE */
-#define HSMC3_READ_MODE_NCS_CONTROLLED		0
-#define HSMC3_READ_MODE_NRD_CONTROLLED		1
-
-/* Constants for WRITE_MODE */
-#define HSMC3_WRITE_MODE_NCS_CONTROLLED		0
-#define HSMC3_WRITE_MODE_NWE_CONTROLLED		1
-
-/* Constants for EXNW_MODE */
-#define HSMC3_EXNW_MODE_DISABLED		0
-#define HSMC3_EXNW_MODE_RESERVED		1
-#define HSMC3_EXNW_MODE_FROZEN			2
-#define HSMC3_EXNW_MODE_READY			3
-
-/* Constants for BAT */
-#define HSMC3_BAT_BYTE_SELECT			0
-#define HSMC3_BAT_BYTE_WRITE			1
-
-/* Constants for DBW */
-#define HSMC3_DBW_8_BITS			0
-#define HSMC3_DBW_16_BITS			1
-#define HSMC3_DBW_32_BITS			2
-
-/* Bit manipulation macros */
-#define HSMC3_BIT(name)						\
-	(1 << HSMC3_##name##_OFFSET)
-#define HSMC3_BF(name,value)					\
-	(((value) & ((1 << HSMC3_##name##_SIZE) - 1))		\
-	 << HSMC3_##name##_OFFSET)
-#define HSMC3_BFEXT(name,value)					\
-	(((value) >> HSMC3_##name##_OFFSET)			\
-	 & ((1 << HSMC3_##name##_SIZE) - 1))
-#define HSMC3_BFINS(name,value,old)\
-	(((old) & ~(((1 << HSMC3_##name##_SIZE) - 1)		\
-		    << HSMC3_##name##_OFFSET))			\
-	 | HSMC3_BF(name,value))
-
-/* Register access macros */
-#define hsmc3_readl(reg)					\
-	readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg)
-#define hsmc3_writel(reg,value)					\
-	writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg)
-
-#endif /* __CPU_AT32AP_HSMC3_H__ */

arch/avr32/cpu/interrupts.c

@@ -1,112 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <div64.h>
-
-#include <linux/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/sysreg.h>
-
-#include <asm/arch/hardware.h>
-
-#define HANDLER_MASK	0x00ffffff
-#define INTLEV_SHIFT	30
-#define INTLEV_MASK	0x00000003
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Incremented whenever COUNT reaches 0xffffffff by timer_interrupt_handler */
-volatile unsigned long timer_overflow;
-
-/*
- * Instead of dividing by get_tbclk(), multiply by this constant and
- * right-shift the result by 32 bits.
- */
-static unsigned long tb_factor;
-
-unsigned long get_tbclk(void)
-{
-	return gd->arch.cpu_hz;
-}
-
-unsigned long long get_ticks(void)
-{
-	unsigned long lo, hi_now, hi_prev;
-
-	do {
-		hi_prev = timer_overflow;
-		lo = sysreg_read(COUNT);
-		hi_now = timer_overflow;
-	} while (hi_prev != hi_now);
-
-	return ((unsigned long long)hi_now << 32) | lo;
-}
-
-unsigned long get_timer(unsigned long base)
-{
-	u64 now = get_ticks();
-
-	now *= tb_factor;
-	return (unsigned long)(now >> 32) - base;
-}
-
-/*
- * For short delays only. It will overflow after a few seconds.
- */
-void __udelay(unsigned long usec)
-{
-	unsigned long cycles;
-	unsigned long base;
-	unsigned long now;
-
-	base = sysreg_read(COUNT);
-	cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
-
-	do {
-		now = sysreg_read(COUNT);
-	} while ((now - base) < cycles);
-}
-
-static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
-				 unsigned int priority)
-{
-	extern void _evba(void);
-	unsigned long intpr;
-	unsigned long handler_addr = (unsigned long)handler;
-
-	handler_addr -= (unsigned long)&_evba;
-
-	if ((handler_addr & HANDLER_MASK) != handler_addr
-	    || (priority & INTLEV_MASK) != priority)
-		return -EINVAL;
-
-	intpr = (handler_addr & HANDLER_MASK);
-	intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
-	writel(intpr, (void *)ATMEL_BASE_INTC + 4 * nr);
-
-	return 0;
-}
-
-int timer_init(void)
-{
-	extern void timer_interrupt_handler(void);
-	u64 tmp;
-
-	sysreg_write(COUNT, 0);
-
-	tmp = (u64)CONFIG_SYS_HZ << 32;
-	tmp += gd->arch.cpu_hz / 2;
-	do_div(tmp, gd->arch.cpu_hz);
-	tb_factor = (u32)tmp;
-
-	if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
-		return -EINVAL;
-
-	/* For all practical purposes, this gives us an overflow interrupt */
-	sysreg_write(COMPARE, 0xffffffff);
-	return 0;
-}

arch/avr32/cpu/mmc.c

@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <atmel_mci.h>
-#include <asm/arch/hardware.h>
-
-/* provide cpu_mmc_init, to overwrite provide board_mmc_init */
-int cpu_mmc_init(bd_t *bd)
-{
-	/* This calls the atmel_mci_init in gen_atmel_mci.c */
-	return atmel_mci_init((void *)ATMEL_BASE_MMCI);
-}

arch/avr32/cpu/portmux-gpio.c

@@ -1,91 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags)
-{
-	/* Both pull-up and pull-down set means buskeeper */
-	if (flags & PORTMUX_PULL_DOWN)
-		gpio_writel(port, PDERS, pin_mask);
-	else
-		gpio_writel(port, PDERC, pin_mask);
-	if (flags & PORTMUX_PULL_UP)
-		gpio_writel(port, PUERS, pin_mask);
-	else
-		gpio_writel(port, PUERC, pin_mask);
-
-	/* Select drive strength */
-	if (flags & PORTMUX_DRIVE_LOW)
-		gpio_writel(port, ODCR0S, pin_mask);
-	else
-		gpio_writel(port, ODCR0C, pin_mask);
-	if (flags & PORTMUX_DRIVE_HIGH)
-		gpio_writel(port, ODCR1S, pin_mask);
-	else
-		gpio_writel(port, ODCR1C, pin_mask);
-
-	/* Select function */
-	if (func & PORTMUX_FUNC_B)
-		gpio_writel(port, PMR0S, pin_mask);
-	else
-		gpio_writel(port, PMR0C, pin_mask);
-	if (func & PORTMUX_FUNC_C)
-		gpio_writel(port, PMR1S, pin_mask);
-	else
-		gpio_writel(port, PMR1C, pin_mask);
-
-	/* Disable GPIO (i.e. enable peripheral) */
-	gpio_writel(port, GPERC, pin_mask);
-}
-
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags)
-{
-	/* Both pull-up and pull-down set means buskeeper */
-	if (flags & PORTMUX_PULL_DOWN)
-		gpio_writel(port, PDERS, pin_mask);
-	else
-		gpio_writel(port, PDERC, pin_mask);
-	if (flags & PORTMUX_PULL_UP)
-		gpio_writel(port, PUERS, pin_mask);
-	else
-		gpio_writel(port, PUERC, pin_mask);
-
-	/* Enable open-drain mode if requested */
-	if (flags & PORTMUX_OPEN_DRAIN)
-		gpio_writel(port, ODMERS, pin_mask);
-	else
-		gpio_writel(port, ODMERC, pin_mask);
-
-	/* Select drive strength */
-	if (flags & PORTMUX_DRIVE_LOW)
-		gpio_writel(port, ODCR0S, pin_mask);
-	else
-		gpio_writel(port, ODCR0C, pin_mask);
-	if (flags & PORTMUX_DRIVE_HIGH)
-		gpio_writel(port, ODCR1S, pin_mask);
-	else
-		gpio_writel(port, ODCR1C, pin_mask);
-
-	/* Select direction and initial pin state */
-	if (flags & PORTMUX_DIR_OUTPUT) {
-		if (flags & PORTMUX_INIT_HIGH)
-			gpio_writel(port, OVRS, pin_mask);
-		else
-			gpio_writel(port, OVRC, pin_mask);
-		gpio_writel(port, ODERS, pin_mask);
-	} else {
-		gpio_writel(port, ODERC, pin_mask);
-	}
-
-	/* Enable GPIO */
-	gpio_writel(port, GPERS, pin_mask);
-}

arch/avr32/cpu/portmux-pio.c

@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags)
-{
-	if (flags & PORTMUX_PULL_UP)
-		pio_writel(port, PUER, pin_mask);
-	else
-		pio_writel(port, PUDR, pin_mask);
-
-	switch (func) {
-	case PORTMUX_FUNC_A:
-		pio_writel(port, ASR, pin_mask);
-		break;
-	case PORTMUX_FUNC_B:
-		pio_writel(port, BSR, pin_mask);
-		break;
-	}
-
-	pio_writel(port, PDR, pin_mask);
-}
-
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags)
-{
-	if (flags & PORTMUX_PULL_UP)
-		pio_writel(port, PUER, pin_mask);
-	else
-		pio_writel(port, PUDR, pin_mask);
-
-	if (flags & PORTMUX_OPEN_DRAIN)
-		pio_writel(port, MDER, pin_mask);
-	else
-		pio_writel(port, MDDR, pin_mask);
-
-	if (flags & PORTMUX_DIR_OUTPUT) {
-		if (flags & PORTMUX_INIT_HIGH)
-			pio_writel(port, SODR, pin_mask);
-		else
-			pio_writel(port, CODR, pin_mask);
-		pio_writel(port, OER, pin_mask);
-	} else {
-		pio_writel(port, ODR, pin_mask);
-	}
-
-	pio_writel(port, PER, pin_mask);
-}
-
-void pio_set_output_value(unsigned int pin, int value)
-{
-	void *port = pio_pin_to_port(pin);
-
-	if (!port)
-		panic("Invalid GPIO pin %u\n", pin);
-
-	__pio_set_output_value(port, pin & 0x1f, value);
-}
-
-int pio_get_input_value(unsigned int pin)
-{
-	void *port = pio_pin_to_port(pin);
-
-	if (!port)
-		panic("Invalid GPIO pin %u\n", pin);
-
-	return __pio_get_input_value(port, pin & 0x1f);
-}

arch/avr32/cpu/start.S

@@ -1,268 +0,0 @@
-/*
- * Copyright (C) 2005-2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <asm-offsets.h>
-#include <config.h>
-#include <asm/ptrace.h>
-#include <asm/sysreg.h>
-
-#define SYSREG_MMUCR_I_OFFSET	2
-#define SYSREG_MMUCR_S_OFFSET	4
-
-#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
-/* due to errata (unreliable branch folding) clear FE bit explicitly */
-#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE)	\
-		    | SYSREG_BIT(RE)   |  SYSREG_BIT(IBE)		\
-		    | SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
-
-	/*
-	 * To save some space, we use the same entry point for
-	 * exceptions and reset. This avoids lots of alignment padding
-	 * since the reset vector is always suitably aligned.
-	 */
-	.section .exception.text, "ax", @progbits
-	.global	_start
-	.global	_evba
-	.type	_start, @function
-	.type	_evba, @function
-_start:
-	.size	_start, 0
-_evba:
-	.org	0x00
-	rjmp	unknown_exception	/* Unrecoverable exception */
-	.org	0x04
-	rjmp	unknown_exception	/* TLB multiple hit */
-	.org	0x08
-	rjmp	unknown_exception	/* Bus error data fetch */
-	.org	0x0c
-	rjmp	unknown_exception	/* Bus error instruction fetch */
-	.org	0x10
-	rjmp	unknown_exception	/* NMI */
-	.org	0x14
-	rjmp	unknown_exception	/* Instruction address */
-	.org	0x18
-	rjmp	unknown_exception	/* ITLB protection */
-	.org	0x1c
-	rjmp	unknown_exception	/* Breakpoint */
-	.org	0x20
-	rjmp	unknown_exception	/* Illegal opcode */
-	.org	0x24
-	rjmp	unknown_exception	/* Unimplemented instruction */
-	.org	0x28
-	rjmp	unknown_exception	/* Privilege violation */
-	.org	0x2c
-	rjmp	unknown_exception	/* Floating-point */
-	.org	0x30
-	rjmp	unknown_exception	/* Coprocessor absent */
-	.org	0x34
-	rjmp	unknown_exception	/* Data Address (read) */
-	.org	0x38
-	rjmp	unknown_exception	/* Data Address (write) */
-	.org	0x3c
-	rjmp	unknown_exception	/* DTLB Protection (read) */
-	.org	0x40
-	rjmp	unknown_exception	/* DTLB Protection (write) */
-	.org	0x44
-	rjmp	unknown_exception	/* DTLB Modified */
-
-	.org	0x50			/* ITLB Miss */
-	pushm   r8-r12,lr
-	rjmp	1f
-	.org	0x60			/* DTLB Miss (read) */
-	pushm   r8-r12,lr
-	rjmp	1f
-	.org	0x70			/* DTLB Miss (write) */
-	pushm   r8-r12,lr
-1:	mov	r12, sp
-	rcall	mmu_handle_tlb_miss
-	popm	r8-r12,lr
-	brne	unknown_exception
-	rete
-
-	.size	_evba, . - _evba
-
-	.align	2
-	.type	unknown_exception, @function
-unknown_exception:
-	/* Figure out whether we're handling an exception (Exception
-	 * mode) or just booting (Supervisor mode). */
-	csrfcz	SYSREG_M1_OFFSET
-	brcc	at32ap_cpu_bootstrap
-
-	/* This is an exception. Complain. */
-	pushm	r0-r12
-	sub	r8, sp, REG_R12 - REG_R0 - 4
-	mov	r9, lr
-	mfsr	r10, SYSREG_RAR_EX
-	mfsr	r11, SYSREG_RSR_EX
-	pushm	r8-r11
-	mfsr	r12, SYSREG_ECR
-	mov	r11, sp
-	rcall	do_unknown_exception
-1:	rjmp	1b
-
-	/* The COUNT/COMPARE timer interrupt handler */
-	.global	timer_interrupt_handler
-	.type	timer_interrupt_handler,@function
-	.align	2
-timer_interrupt_handler:
-	/*
-	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
-	 *
-	 * We're running at interrupt level 3, so we don't need to save
-	 * r8-r12 or lr to the stack.
-	 */
-	lda.w	r8, timer_overflow
-	ld.w	r9, r8[0]
-	mov	r10, -1
-	mtsr	SYSREG_COMPARE, r10
-	sub	r9, -1
-	st.w	r8[0], r9
-	rete
-
-	/*
-	 * CPU bootstrap after reset is handled here. SoC code may
-	 * override this in case they need to initialize oscillators,
-	 * etc.
-	 */
-	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
-	.global	at32ap_cpu_bootstrap
-	.weak	at32ap_cpu_bootstrap
-	.type	at32ap_cpu_bootstrap, @function
-	.align	2
-at32ap_cpu_bootstrap:
-	/* Reset the Status Register */
-	mov	r0, lo(SR_INIT)
-	orh	r0, hi(SR_INIT)
-	mtsr	SYSREG_SR, r0
-
-	/* Reset CPUCR and invalidate the BTB */
-	mov	r2, CPUCR_INIT
-	mtsr	SYSREG_CPUCR, r2
-
-	/* Flush the caches */
-	mov	r1, 0
-	cache	r1[4], 8
-	cache	r1[0], 0
-	sync	0
-
-	/* Reset the MMU to default settings */
-	mov	r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
-	mtsr	SYSREG_MMUCR, r0
-
-	/* Internal RAM should not need any initialization.  We might
-	   have to initialize external RAM here if the part doesn't
-	   have internal RAM (or we may use the data cache) */
-
-	/* Jump to cacheable segment */
-	lddpc	pc, 1f
-
-	.align	2
-1:	.long	at32ap_low_level_init
-	.size	_start, . - _start
-
-	/* Common CPU bootstrap code after oscillator/cache/etc. init */
-	.section .text.avr32ap_low_level_init, "ax", @progbits
-	.global	at32ap_low_level_init
-	.type	at32ap_low_level_init, @function
-	.align	2
-at32ap_low_level_init:
-	lddpc	sp, sp_init
-
-	/* Initialize the GOT pointer */
-	lddpc	r6, got_init
-3:	rsub	r6, pc
-
-	/* Let's go */
-	rjmp	board_init_f
-
-	.align	2
-	.type	sp_init,@object
-sp_init:
-	.long	CONFIG_SYS_INIT_SP_ADDR
-got_init:
-	.long	3b - _GLOBAL_OFFSET_TABLE_
-
-	/*
-	 * void	relocate_code(new_sp, new_gd, monitor_addr)
-	 *
-	 * Relocate the u-boot image into RAM and continue from there.
-	 * Does not return.
-	 */
-	.section .text.relocate_code,"ax",@progbits
-	.global	relocate_code
-	.type	relocate_code,@function
-relocate_code:
-	mov	sp, r12		/* use new stack */
-	mov	r12, r11	/* save new_gd */
-	mov	r11, r10	/* save destination address */
-
-	/* copy .text section and flush the cache along the way */
-	lda.w	r8, _text
-	lda.w	r9, _etext
-	sub	lr, r10, r8	/* relocation offset */
-
-1:	ldm	r8++, r0-r3
-	stm	r10, r0-r3
-	sub	r10, -16
-	ldm	r8++, r0-r3
-	stm	r10, r0-r3
-	sub	r10, -16
-	cp.w	r8, r9
-	cache	r10[-4], 0x0d	/* dcache clean/invalidate */
-	cache	r10[-4], 0x01	/* icache invalidate */
-	brlt	1b
-
-	/* flush write buffer */
-	sync	0
-
-	/* copy data sections */
-	lda.w	r9, _edata
-1:	ld.d	r0, r8++
-	st.d	r10++, r0
-	cp.w	r8, r9
-	brlt	1b
-
-	/* zero out .bss */
-	mov	r0, 0
-	mov	r1, 0
-	lda.w	r9, __bss_end
-	sub	r9, r8
-1:	st.d	r10++, r0
-	sub	r9, 8
-	brgt	1b
-
-	/* jump to RAM */
-	sub	r0, pc, . - in_ram
-	add	pc, r0, lr
-
-	.align	2
-in_ram:
-	/* find the new GOT and relocate it */
-	lddpc	r6, got_init_reloc
-3:	rsub	r6, pc
-	mov	r8, r6
-	lda.w	r9, _egot
-	lda.w	r10, _got
-	sub	r9, r10
-1:	ld.w	r0, r8[0]
-	add	r0, lr
-	st.w	r8++, r0
-	sub	r9, 4
-	brgt	1b
-
-	/* Move the exception handlers */
-	mfsr	r2, SYSREG_EVBA
-	add	r2, lr
-	mtsr	SYSREG_EVBA, r2
-
-	/* Do the rest of the initialization sequence */
-	call	board_init_r
-
-	.align	2
-got_init_reloc:
-	.long	3b - _GLOBAL_OFFSET_TABLE_
-
-	.size	relocate_code, . - relocate_code

arch/avr32/cpu/u-boot.lds

@@ -1,58 +0,0 @@
-/* -*- Fundamental -*-
- *
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
-OUTPUT_ARCH(avr32)
-ENTRY(_start)
-
-SECTIONS
-{
-	. = 0;
-	_text = .;
-	.text : {
-		*(.exception.text)
-		*(.text)
-		*(.text.*)
-	}
-	_etext = .;
-
-	.rodata : {
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-	}
-
-	. = ALIGN(8);
-	_data = .;
-	.data : {
-		*(.data)
-		*(.data.*)
-	}
-
-	. = ALIGN(4);
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-	_got = .;
-	.got : {
-		*(.got)
-	}
-	_egot = .;
-
-	. = ALIGN(8);
-	_edata = .;
-
-	.bss (NOLOAD) : {
-		__bss_start = .;
-		*(.bss)
-		*(.bss.*)
-	}
-	. = ALIGN(8);
-	__bss_end = .;
-	__init_end = .;
-}

arch/avr32/include/asm/arch-at32ap700x/addrspace.h

@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_ADDRSPACE_H
-#define __ASM_AVR32_ADDRSPACE_H
-
-#include <asm/types.h>
-
-/* Memory segments when segmentation is enabled */
-#define P0SEG		0x00000000
-#define P1SEG		0x80000000
-#define P2SEG		0xa0000000
-#define P3SEG		0xc0000000
-#define P4SEG		0xe0000000
-
-/* Returns the privileged segment base of a given address */
-#define PXSEG(a)	(((unsigned long)(a)) & 0xe0000000)
-
-/* Returns the physical address of a PnSEG (n=1,2) address */
-#define PHYSADDR(a)	(((unsigned long)(a)) & 0x1fffffff)
-
-/*
- * Map an address to a certain privileged segment
- */
-#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
-#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
-#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
-#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
-
-/* virt_to_phys will only work when address is in P1 or P2 */
-static inline unsigned long virt_to_phys(volatile void *address)
-{
-	return PHYSADDR(address);
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-	return (void *)P1SEGADDR(address);
-}
-
-#define cached(addr) ((void *)P1SEGADDR(addr))
-#define uncached(addr) ((void *)P2SEGADDR(addr))
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- *
- * This implementation works for memory below 512MiB (flash, etc.) as
- * well as above 3.5GiB (internal peripherals.)
- */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(1 << 7)
-#define MAP_WRBACK	(MAP_WRCOMBINE | (1 << 9))
-#define MAP_WRTHROUGH	(MAP_WRBACK | (1 << 0))
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-#endif /* __ASM_AVR32_ADDRSPACE_H */

arch/avr32/include/asm/arch-at32ap700x/cacheflush.h

@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_CACHEFLUSH_H
-#define __ASM_AVR32_CACHEFLUSH_H
-
-/*
- * Invalidate any cacheline containing virtual address vaddr without
- * writing anything back to memory.
- *
- * Note that this function may corrupt unrelated data structures when
- * applied on buffers that are not cacheline aligned in both ends.
- */
-static inline void dcache_invalidate_line(volatile void *vaddr)
-{
-	asm volatile("cache %0[0], 0x0b" : : "r"(vaddr) : "memory");
-}
-
-/*
- * Make sure any cacheline containing virtual address vaddr is written
- * to memory.
- */
-static inline void dcache_clean_line(volatile void *vaddr)
-{
-	asm volatile("cache %0[0], 0x0c" : : "r"(vaddr) : "memory");
-}
-
-/*
- * Make sure any cacheline containing virtual address vaddr is written
- * to memory and then invalidate it.
- */
-static inline void dcache_flush_line(volatile void *vaddr)
-{
-	asm volatile("cache %0[0], 0x0d" : : "r"(vaddr) : "memory");
-}
-
-/*
- * Invalidate any instruction cacheline containing virtual address
- * vaddr.
- */
-static inline void icache_invalidate_line(volatile void *vaddr)
-{
-	asm volatile("cache %0[0], 0x01" : : "r"(vaddr) : "memory");
-}
-
-/*
- * Applies the above functions on all lines that are touched by the
- * specified virtual address range.
- */
-void dcache_clean_range(volatile void *start, size_t len);
-void icache_invalidate_range(volatile void *start, size_t len);
-
-static inline void dcache_flush_unlocked(void)
-{
-	asm volatile("cache %0[5], 0x08" : : "r"(0) : "memory");
-}
-
-/*
- * Make sure any pending writes are completed before continuing.
- */
-#define sync_write_buffer() asm volatile("sync 0" : : : "memory")
-
-#endif /* __ASM_AVR32_CACHEFLUSH_H */

arch/avr32/include/asm/arch-at32ap700x/chip-features.h

@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2007 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__
-#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__
-
-/* Currently, all the AP700x chips have these */
-#define AT32AP700x_CHIP_HAS_USART
-#define AT32AP700x_CHIP_HAS_MMCI
-#define AT32AP700x_CHIP_HAS_SPI
-
-/* Only AP7000 has ethernet interface */
-#ifdef CONFIG_AT32AP7000
-#define AT32AP700x_CHIP_HAS_MACB
-#endif
-
-/* AP7000 and AP7002 have LCD controller, but AP7001 does not */
-#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002)
-#define AT32AP700x_CHIP_HAS_LCDC
-#endif
-
-#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */

arch/avr32/include/asm/arch-at32ap700x/clk.h

@@ -1,175 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_ARCH_CLK_H__
-#define __ASM_AVR32_ARCH_CLK_H__
-
-#include <asm/arch/chip-features.h>
-#include <asm/arch/portmux.h>
-
-#ifdef CONFIG_PLL
-#define PLL0_RATE	((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV)	\
-				* CONFIG_SYS_PLL0_MUL)
-#define MAIN_CLK_RATE	PLL0_RATE
-#else
-#define MAIN_CLK_RATE	(CONFIG_SYS_OSC0_HZ)
-#endif
-
-static inline unsigned long get_cpu_clk_rate(void)
-{
-	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU;
-}
-static inline unsigned long get_hsb_clk_rate(void)
-{
-	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB;
-}
-static inline unsigned long get_pba_clk_rate(void)
-{
-	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA;
-}
-static inline unsigned long get_pbb_clk_rate(void)
-{
-	return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB;
-}
-
-/* Accessors for specific devices. More will be added as needed. */
-static inline unsigned long get_sdram_clk_rate(void)
-{
-	return get_hsb_clk_rate();
-}
-#ifdef AT32AP700x_CHIP_HAS_USART
-static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
-{
-	return get_pba_clk_rate();
-}
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MACB
-static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
-{
-	return get_pbb_clk_rate();
-}
-static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
-{
-	return get_hsb_clk_rate();
-}
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-static inline unsigned long get_mci_clk_rate(void)
-{
-	return get_pbb_clk_rate();
-}
-#endif
-#ifdef AT32AP700x_CHIP_HAS_SPI
-static inline unsigned long get_spi_clk_rate(unsigned int dev_id)
-{
-	return get_pba_clk_rate();
-}
-#endif
-#ifdef AT32AP700x_CHIP_HAS_LCDC
-static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
-{
-	return get_hsb_clk_rate();
-}
-#endif
-
-extern void clk_init(void);
-
-/* Board code may need the SDRAM base clock as a compile-time constant */
-#define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB)
-
-/* Generic clock control */
-enum gclk_parent {
-	GCLK_PARENT_OSC0 = 0,
-	GCLK_PARENT_OSC1 = 1,
-	GCLK_PARENT_PLL0 = 2,
-	GCLK_PARENT_PLL1 = 3,
-};
-
-/* Some generic clocks have specific roles */
-#define GCLK_DAC_SAMPLE_CLK	6
-#define GCLK_LCDC_PIXCLK	7
-
-extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
-		unsigned long rate, unsigned long parent_rate);
-
-/**
- * gclk_set_rate - configure and enable a generic clock
- * @id: Which GCLK[id] to enable
- * @parent: Parent clock feeding the GCLK
- * @rate: Target rate of the GCLK in Hz
- *
- * Returns the actual GCLK rate in Hz, after rounding to the nearest
- * supported rate.
- *
- * All three parameters are usually constant, hence the inline.
- */
-static inline unsigned long gclk_set_rate(unsigned int id,
-		enum gclk_parent parent, unsigned long rate)
-{
-	unsigned long parent_rate;
-
-	if (id > 7)
-		return 0;
-
-	switch (parent) {
-	case GCLK_PARENT_OSC0:
-		parent_rate = CONFIG_SYS_OSC0_HZ;
-		break;
-#ifdef CONFIG_SYS_OSC1_HZ
-	case GCLK_PARENT_OSC1:
-		parent_rate = CONFIG_SYS_OSC1_HZ;
-		break;
-#endif
-#ifdef PLL0_RATE
-	case GCLK_PARENT_PLL0:
-		parent_rate = PLL0_RATE;
-		break;
-#endif
-#ifdef PLL1_RATE
-	case GCLK_PARENT_PLL1:
-		parent_rate = PLL1_RATE;
-		break;
-#endif
-	default:
-		parent_rate = 0;
-		break;
-	}
-
-	return __gclk_set_rate(id, parent, rate, parent_rate);
-}
-
-/**
- * gclk_enable_output - enable output on a GCLK pin
- * @id: Which GCLK[id] pin to enable
- * @drive_strength: Drive strength of external GCLK pin, if applicable
- */
-static inline void gclk_enable_output(unsigned int id,
-		unsigned long drive_strength)
-{
-	switch (id) {
-	case 0:
-		portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30,
-				PORTMUX_FUNC_A, drive_strength);
-		break;
-	case 1:
-		portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31,
-				PORTMUX_FUNC_A, drive_strength);
-		break;
-	case 2:
-		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19,
-				PORTMUX_FUNC_A, drive_strength);
-		break;
-	case 3:
-		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29,
-				PORTMUX_FUNC_A, drive_strength);
-		break;
-	case 4:
-		portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30,
-				PORTMUX_FUNC_A, drive_strength);
-		break;
-	}
-}
-
-#endif /* __ASM_AVR32_ARCH_CLK_H__ */

arch/avr32/include/asm/arch-at32ap700x/gpio.h

@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_ARCH_GPIO_H__
-#define __ASM_AVR32_ARCH_GPIO_H__
-
-#include <asm/arch/chip-features.h>
-#include <asm/arch/hardware.h>
-
-#define NR_GPIO_CONTROLLERS	5
-
-/*
- * Pin numbers identifying specific GPIO pins on the chip.
- */
-#define GPIO_PIOA_BASE	(0)
-#define GPIO_PIOB_BASE	(GPIO_PIOA_BASE + 32)
-#define GPIO_PIOC_BASE	(GPIO_PIOB_BASE + 32)
-#define GPIO_PIOD_BASE	(GPIO_PIOC_BASE + 32)
-#define GPIO_PIOE_BASE	(GPIO_PIOD_BASE + 32)
-#define GPIO_PIN_PA(x)	(GPIO_PIOA_BASE + (x))
-#define GPIO_PIN_PB(x)	(GPIO_PIOB_BASE + (x))
-#define GPIO_PIN_PC(x)	(GPIO_PIOC_BASE + (x))
-#define GPIO_PIN_PD(x)	(GPIO_PIOD_BASE + (x))
-#define GPIO_PIN_PE(x)	(GPIO_PIOE_BASE + (x))
-
-static inline void *pio_pin_to_port(unsigned int pin)
-{
-	switch (pin >> 5) {
-	case 0:
-		return (void *)ATMEL_BASE_PIOA;
-	case 1:
-		return (void *)ATMEL_BASE_PIOB;
-	case 2:
-		return (void *)ATMEL_BASE_PIOC;
-	case 3:
-		return (void *)ATMEL_BASE_PIOD;
-	case 4:
-		return (void *)ATMEL_BASE_PIOE;
-	default:
-		return NULL;
-	}
-}
-
-#include <asm/arch-common/portmux-pio.h>
-
-#endif /* __ASM_AVR32_ARCH_GPIO_H__ */

arch/avr32/include/asm/arch-at32ap700x/hardware.h

@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __AT32AP7000_HARDWARE_H__
-#define __AT32AP7000_HARDWARE_H__
-
-/* Internal and external memories */
-#define EBI_SRAM_CS0_BASE			0x00000000
-#define EBI_SRAM_CS0_SIZE			0x04000000
-#define EBI_SRAM_CS4_BASE			0x04000000
-#define EBI_SRAM_CS4_SIZE			0x04000000
-#define EBI_SRAM_CS2_BASE			0x08000000
-#define EBI_SRAM_CS2_SIZE			0x04000000
-#define EBI_SRAM_CS3_BASE			0x0c000000
-#define EBI_SRAM_CS3_SIZE			0x04000000
-#define EBI_SRAM_CS1_BASE			0x10000000
-#define EBI_SRAM_CS1_SIZE			0x10000000
-#define EBI_SRAM_CS5_BASE			0x20000000
-#define EBI_SRAM_CS5_SIZE			0x04000000
-
-#define EBI_SDRAM_BASE				EBI_SRAM_CS1_BASE
-#define EBI_SDRAM_SIZE				EBI_SRAM_CS1_SIZE
-
-#define INTERNAL_SRAM_BASE			0x24000000
-#define INTERNAL_SRAM_SIZE			0x00008000
-
-/* Devices on the High Speed Bus (HSB) */
-#define LCDC_BASE					0xFF000000
-#define DMAC_BASE					0xFF200000
-#define USB_FIFO					0xFF300000
-
-/* Devices on Peripheral Bus A (PBA) */
-#define ATMEL_BASE_SPI0				0xFFE00000
-#define ATMEL_BASE_SPI1				0xFFE00400
-#define ATMEL_BASE_TWI0				0xFFE00800
-#define ATMEL_BASE_USART0			0xFFE00C00
-#define ATMEL_BASE_USART1			0xFFE01000
-#define ATMEL_BASE_USART2			0xFFE01400
-#define ATMEL_BASE_USART3			0xFFE01800
-#define ATMEL_BASE_SSC0				0xFFE01C00
-#define ATMEL_BASE_SSC1				0xFFE02000
-#define ATMEL_BASE_SSC2				0xFFE02400
-#define ATMEL_BASE_PIOA				0xFFE02800
-#define ATMEL_BASE_PIOB				0xFFE02C00
-#define ATMEL_BASE_PIOC				0xFFE03000
-#define ATMEL_BASE_PIOD				0xFFE03400
-#define ATMEL_BASE_PIOE				0xFFE03800
-#define ATMEL_BASE_PSIF				0xFFE03C00
-
-/* Devices on Peripheral Bus B (PBB) */
-#define ATMEL_BASE_SM				0xFFF00000
-#define ATMEL_BASE_INTC				0xFFF00400
-#define ATMEL_BASE_HMATRIX			0xFFF00800
-#define ATMEL_BASE_TIMER0			0xFFF00C00
-#define ATMEL_BASE_TIMER1			0xFFF01000
-#define ATMEL_BASE_PWM				0xFFF01400
-#define ATMEL_BASE_MACB0			0xFFF01800
-#define ATMEL_BASE_MACB1			0xFFF01C00
-#define ATMEL_BASE_DAC				0xFFF02000
-#define ATMEL_BASE_MMCI				0xFFF02400
-#define ATMEL_BASE_AUDIOC			0xFFF02800
-#define ATMEL_BASE_HISI				0xFFF02C00
-#define ATMEL_BASE_USB				0xFFF03000
-#define ATMEL_BASE_HSMC				0xFFF03400
-#define ATMEL_BASE_HSDRAMC			0xFFF03800
-#define ATMEL_BASE_ECC				0xFFF03C00
-
-#endif /* __AT32AP7000_HARDWARE_H__ */

arch/avr32/include/asm/arch-at32ap700x/hmatrix.h

@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_ARCH_HMATRIX_H__
-#define __ASM_AVR32_ARCH_HMATRIX_H__
-
-#include <asm/hmatrix-common.h>
-
-/* Bitfields in SFR4 (EBI) */
-#define HMATRIX_EBI_SDRAM_ENABLE_OFFSET		1
-#define HMATRIX_EBI_SDRAM_ENABLE_SIZE		1
-#define HMATRIX_EBI_NAND_ENABLE_OFFSET		3
-#define HMATRIX_EBI_NAND_ENABLE_SIZE		1
-#define HMATRIX_EBI_CF0_ENABLE_OFFSET		4
-#define HMATRIX_EBI_CF0_ENABLE_SIZE		1
-#define HMATRIX_EBI_CF1_ENABLE_OFFSET		5
-#define HMATRIX_EBI_CF1_ENABLE_SIZE		1
-#define HMATRIX_EBI_PULLUP_DISABLE_OFFSET	8
-#define HMATRIX_EBI_PULLUP_DISABLE_SIZE		1
-
-/* HSB masters */
-#define HMATRIX_MASTER_CPU_DCACHE		0
-#define HMATRIX_MASTER_CPU_ICACHE		1
-#define HMATRIX_MASTER_PDC			2
-#define HMATRIX_MASTER_ISI			3
-#define HMATRIX_MASTER_USBA			4
-#define HMATRIX_MASTER_LCDC			5
-#define HMATRIX_MASTER_MACB0			6
-#define HMATRIX_MASTER_MACB1			7
-#define HMATRIX_MASTER_DMACA_M0			8
-#define HMATRIX_MASTER_DMACA_M1			9
-
-/* HSB slaves */
-#define HMATRIX_SLAVE_SRAM0			0
-#define HMATRIX_SLAVE_SRAM1			1
-#define HMATRIX_SLAVE_PBA			2
-#define HMATRIX_SLAVE_PBB			3
-#define HMATRIX_SLAVE_EBI			4
-#define HMATRIX_SLAVE_USBA			5
-#define HMATRIX_SLAVE_LCDC			6
-#define HMATRIX_SLAVE_DMACA			7
-
-#endif /* __ASM_AVR32_ARCH_HMATRIX_H__ */

arch/avr32/include/asm/arch-at32ap700x/mmu.h

@@ -1,66 +0,0 @@
-/*
- * In order to deal with the hardcoded u-boot requirement that virtual
- * addresses are always mapped 1:1 with physical addresses, we implement
- * a small virtual memory manager so that we can use the MMU hardware in
- * order to get the caching properties right.
- *
- * A few pages (or possibly just one) are locked in the TLB permanently
- * in order to avoid recursive TLB misses, but most pages are faulted in
- * on demand.
- */
-#ifndef __ASM_ARCH_MMU_H
-#define __ASM_ARCH_MMU_H
-
-#include <asm/sysreg.h>
-
-#define MMU_PAGE_SHIFT	20
-#define MMU_PAGE_SIZE	(1UL << MMU_PAGE_SHIFT)
-#define MMU_PAGE_ADDR_MASK	(~(MMU_PAGE_SIZE - 1))
-
-#define MMU_VMR_CACHE_NONE						\
-	(SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))
-#define MMU_VMR_CACHE_WBUF						\
-	(MMU_VMR_CACHE_NONE | SYSREG_BIT(B))
-#define MMU_VMR_CACHE_WRTHRU						\
-	(MMU_VMR_CACHE_NONE | SYSREG_BIT(TLBELO_C) | SYSREG_BIT(W))
-#define MMU_VMR_CACHE_WRBACK						\
-	(MMU_VMR_CACHE_WBUF | SYSREG_BIT(TLBELO_C))
-
-/*
- * This structure is used in our "page table". Instead of the usual
- * x86-inspired radix tree, we let each entry cover an arbitrary-sized
- * virtual address range and store them in a binary search tree. This is
- * somewhat slower, but should use significantly less RAM, and we
- * shouldn't get many TLB misses when using 1 MB pages anyway.
- *
- * With 1 MB pages, we need 12 bits to store the page number. In
- * addition, we stick an Invalid bit in the high bit of virt_pgno (if
- * set, it cannot possibly match any faulting page), and all the bits
- * that need to be written to TLBELO in phys_pgno.
- */
-struct mmu_vm_range {
-	uint16_t	virt_pgno;
-	uint16_t	nr_pages;
-	uint32_t	phys;
-};
-
-/*
- * An array of mmu_vm_range objects describing all pageable addresses.
- * The array is sorted by virt_pgno so that the TLB miss exception
- * handler can do a binary search to find the correct entry.
- */
-extern struct mmu_vm_range mmu_vmr_table[];
-
-/*
- * Initialize the MMU. This will set up a fixed TLB entry for the static
- * u-boot image at dest_addr and enable paging.
- */
-void mmu_init_r(unsigned long dest_addr);
-
-/*
- * Handle a TLB miss exception. This function is called directly from
- * the exception vector table written in assembly.
- */
-int mmu_handle_tlb_miss(void);
-
-#endif /* __ASM_ARCH_MMU_H */

arch/avr32/include/asm/arch-at32ap700x/portmux.h

@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_ARCH_PORTMUX_H__
-#define __ASM_AVR32_ARCH_PORTMUX_H__
-
-#include <asm/arch/gpio.h>
-
-#define PORTMUX_PORT_A		((void *)ATMEL_BASE_PIOA)
-#define PORTMUX_PORT_B		((void *)ATMEL_BASE_PIOB)
-#define PORTMUX_PORT_C		((void *)ATMEL_BASE_PIOC)
-#define PORTMUX_PORT_D		((void *)ATMEL_BASE_PIOD)
-#define PORTMUX_PORT_E		((void *)ATMEL_BASE_PIOE)
-
-void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width,
-		unsigned long flags, unsigned long drive_strength);
-
-#define PORTMUX_EBI_CS(x)	(1 << (x))
-#define PORTMUX_EBI_NAND	(1 << 6)
-#define PORTMUX_EBI_CF(x)	(1 << ((x) + 7))
-#define PORTMUX_EBI_NWAIT	(1 << 9)
-
-#ifdef AT32AP700x_CHIP_HAS_USART
-static inline void portmux_enable_usart0(unsigned long drive_strength)
-{
-	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9),
-			PORTMUX_FUNC_B, 0);
-}
-
-static inline void portmux_enable_usart1(unsigned long drive_strength)
-{
-	portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18),
-			PORTMUX_FUNC_A, 0);
-}
-
-static inline void portmux_enable_usart2(unsigned long drive_strength)
-{
-	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27),
-			PORTMUX_FUNC_B, 0);
-}
-
-static inline void portmux_enable_usart3(unsigned long drive_strength)
-{
-	portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18),
-			PORTMUX_FUNC_B, 0);
-}
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MACB
-void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength);
-void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength);
-
-#define PORTMUX_MACB_RMII	(0)
-#define PORTMUX_MACB_MII	(1 << 0)
-#define PORTMUX_MACB_SPEED	(1 << 1)
-
-#endif
-#ifdef AT32AP700x_CHIP_HAS_MMCI
-void portmux_enable_mmci(unsigned int slot, unsigned long flags,
-		unsigned long drive_strength);
-
-#define PORTMUX_MMCI_4BIT	(1 << 0)
-#define PORTMUX_MMCI_8BIT	(PORTMUX_MMCI_4BIT | (1 << 1))
-#define PORTMUX_MMCI_EXT_PULLUP	(1 << 2)
-
-#endif
-#ifdef AT32AP700x_CHIP_HAS_SPI
-void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength);
-void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength);
-#endif
-#ifdef AT32AP700x_CHIP_HAS_LCDC
-void portmux_enable_lcdc(int pin_config);
-#endif
-
-#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */

arch/avr32/include/asm/arch-common/portmux-pio.h

@@ -1,122 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __AVR32_PORTMUX_PIO_H__
-#define __AVR32_PORTMUX_PIO_H__
-
-#include <asm/io.h>
-
-/* PIO register offsets */
-#define PIO_PER			0x0000
-#define PIO_PDR			0x0004
-#define PIO_PSR			0x0008
-#define PIO_OER			0x0010
-#define PIO_ODR			0x0014
-#define PIO_OSR			0x0018
-#define PIO_IFER		0x0020
-#define PIO_IFDR		0x0024
-#define PIO_ISFR		0x0028
-#define PIO_SODR		0x0030
-#define PIO_CODR		0x0034
-#define PIO_ODSR		0x0038
-#define PIO_PDSR		0x003c
-#define PIO_IER			0x0040
-#define PIO_IDR			0x0044
-#define PIO_IMR			0x0048
-#define PIO_ISR			0x004c
-#define PIO_MDER		0x0050
-#define PIO_MDDR		0x0054
-#define PIO_MDSR		0x0058
-#define PIO_PUDR		0x0060
-#define PIO_PUER		0x0064
-#define PIO_PUSR		0x0068
-#define PIO_ASR			0x0070
-#define PIO_BSR			0x0074
-#define PIO_ABSR		0x0078
-#define PIO_OWER		0x00a0
-#define PIO_OWDR		0x00a4
-#define PIO_OWSR		0x00a8
-
-/* Hardware register access */
-#define pio_readl(base, reg)				\
-	__raw_readl((void *)base + PIO_##reg)
-#define pio_writel(base, reg, value)			\
-	__raw_writel((value), (void *)base + PIO_##reg)
-
-/* Portmux API starts here. See doc/README.AVR32-port-muxing */
-
-enum portmux_function {
-	PORTMUX_FUNC_A,
-	PORTMUX_FUNC_B,
-};
-
-/* Pull-down, buskeeper and drive strength are not supported */
-#define PORTMUX_DIR_INPUT	(0 << 0)
-#define PORTMUX_DIR_OUTPUT	(1 << 0)
-#define PORTMUX_INIT_LOW	(0 << 1)
-#define PORTMUX_INIT_HIGH	(1 << 1)
-#define PORTMUX_PULL_UP		(1 << 2)
-#define PORTMUX_PULL_DOWN	(0)
-#define PORTMUX_BUSKEEPER	PORTMUX_PULL_UP
-#define PORTMUX_DRIVE_MIN	(0)
-#define PORTMUX_DRIVE_LOW	(0)
-#define PORTMUX_DRIVE_HIGH	(0)
-#define PORTMUX_DRIVE_MAX	(0)
-#define PORTMUX_OPEN_DRAIN	(1 << 3)
-
-void portmux_select_peripheral(void *port, unsigned long pin_mask,
-		enum portmux_function func, unsigned long flags);
-void portmux_select_gpio(void *port, unsigned long pin_mask,
-		unsigned long flags);
-
-/* Internal helper functions */
-
-static inline void __pio_set_output_value(void *port, unsigned int pin,
-		int value)
-{
-	/*
-	 * value will usually be constant, but it's pretty cheap
-	 * either way.
-	 */
-	if (value)
-		pio_writel(port, SODR, 1 << pin);
-	else
-		pio_writel(port, CODR, 1 << pin);
-}
-
-static inline int __pio_get_input_value(void *port, unsigned int pin)
-{
-	return (pio_readl(port, PDSR) >> pin) & 1;
-}
-
-void pio_set_output_value(unsigned int pin, int value);
-int pio_get_input_value(unsigned int pin);
-
-/* GPIO API starts here */
-
-/*
- * GCC doesn't realize that the constant case is extremely trivial,
- * so we need to help it make the right decision by using
- * always_inline.
- */
-__attribute__((always_inline))
-static inline void gpio_set_value(unsigned int pin, int value)
-{
-	if (__builtin_constant_p(pin))
-		__pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value);
-	else
-		pio_set_output_value(pin, value);
-}
-
-__attribute__((always_inline))
-static inline int gpio_get_value(unsigned int pin)
-{
-	if (__builtin_constant_p(pin))
-		return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f);
-	else
-		return pio_get_input_value(pin);
-}
-
-#endif /* __AVR32_PORTMUX_PIO_H__ */

arch/avr32/include/asm/bitops.h

@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_BITOPS_H
-#define __ASM_AVR32_BITOPS_H
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#endif /* __ASM_AVR32_BITOPS_H */

arch/avr32/include/asm/byteorder.h

@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_BYTEORDER_H
-#define __ASM_AVR32_BYTEORDER_H
-
-#include <asm/types.h>
-
-#define __arch__swab32(x) __builtin_bswap_32(x)
-#define __arch__swab16(x) __builtin_bswap_16(x)
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __BYTEORDER_HAS_U64__
-# define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* __ASM_AVR32_BYTEORDER_H */

arch/avr32/include/asm/cache.h

@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __AVR32_CACHE_H__
-#define __AVR32_CACHE_H__
-
-/*
- * Since the AVR32 architecture has a queryable cacheline size with a maximum
- * value of 256 we set the DMA buffer alignemnt requirement to this maximum
- * value.  The board config can override this if it knows that the cacheline
- * size is a smaller value.  AVR32 boards use the CONFIG_SYS_DCACHE_LINESZ
- * macro to specify cache line size, so if it is set we use it instead.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#elif defined(CONFIG_SYS_DCACHE_LINESZ)
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_DCACHE_LINESZ
-#else
-#define ARCH_DMA_MINALIGN	256
-#endif
-
-#endif /* __AVR32_CACHE_H__ */

arch/avr32/include/asm/config.h

@@ -1,13 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#define CONFIG_NEEDS_MANUAL_RELOC
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
-#endif

arch/avr32/include/asm/dma-mapping.h

@@ -1,55 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_DMA_MAPPING_H
-#define __ASM_AVR32_DMA_MAPPING_H
-
-#include <asm/io.h>
-#include <asm/arch/cacheflush.h>
-
-enum dma_data_direction {
-	DMA_BIDIRECTIONAL	= 0,
-	DMA_TO_DEVICE		= 1,
-	DMA_FROM_DEVICE		= 2,
-};
-
-static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
-{
-	*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
-	return (void *)*handle;
-}
-
-static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
-					   enum dma_data_direction dir)
-{
-	extern void __bad_dma_data_direction(void);
-
-	switch (dir) {
-	case DMA_BIDIRECTIONAL:
-		flush_dcache_range((unsigned long)vaddr,
-				   (unsigned long)vaddr + len);
-		break;
-	case DMA_TO_DEVICE:
-		dcache_clean_range(vaddr, len);
-		break;
-	case DMA_FROM_DEVICE:
-		invalidate_dcache_range((unsigned long)vaddr,
-					(unsigned long)vaddr + len);
-		break;
-	default:
-		/* This will cause a linker error */
-		__bad_dma_data_direction();
-	}
-
-	return virt_to_phys(vaddr);
-}
-
-static inline void dma_unmap_single(volatile void *vaddr, size_t len,
-				    unsigned long paddr)
-{
-
-}
-
-#endif /* __ASM_AVR32_DMA_MAPPING_H */

arch/avr32/include/asm/global_data.h

@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_GLOBAL_DATA_H__
-#define __ASM_GLOBAL_DATA_H__
-
-/* Architecture-specific global data */
-struct arch_global_data {
-	unsigned long cpu_hz;		/* cpu core clock frequency */
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
-
-#endif /* __ASM_GLOBAL_DATA_H__ */

arch/avr32/include/asm/hmatrix-common.h

@@ -1,115 +0,0 @@
-/*
- * Copyright (C) 2008 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_HMATRIX_COMMON_H__
-#define __ASM_AVR32_HMATRIX_COMMON_H__
-
-/* HMATRIX register offsets */
-struct hmatrix_regs {
-	u32	MCFG[16];
-	u32	SCFG[16];
-	struct {
-		u32	A;
-		u32	B;
-	} PRS[16];
-	u32	MRCR;
-	u32	__reserved[3];
-	u32	SFR[16];
-};
-
-/* Bitfields in MCFG */
-#define HMATRIX_ULBT_OFFSET			0
-#define HMATRIX_ULBT_SIZE			3
-
-/* Bitfields in SCFG */
-#define HMATRIX_SLOT_CYCLE_OFFSET		0
-#define HMATRIX_SLOT_CYCLE_SIZE			8
-#define HMATRIX_DEFMSTR_TYPE_OFFSET		16
-#define HMATRIX_DEFMSTR_TYPE_SIZE		2
-#define HMATRIX_FIXED_DEFMSTR_OFFSET		18
-#define HMATRIX_FIXED_DEFMSTR_SIZE		4
-#define HMATRIX_ARBT_OFFSET			24
-#define HMATRIX_ARBT_SIZE			1
-
-/* Bitfields in PRS.A */
-#define HMATRIX_M0PR_OFFSET			0
-#define HMATRIX_M0PR_SIZE			4
-#define HMATRIX_M1PR_OFFSET			4
-#define HMATRIX_M1PR_SIZE			4
-#define HMATRIX_M2PR_OFFSET			8
-#define HMATRIX_M2PR_SIZE			4
-#define HMATRIX_M3PR_OFFSET			12
-#define HMATRIX_M3PR_SIZE			4
-#define HMATRIX_M4PR_OFFSET			16
-#define HMATRIX_M4PR_SIZE			4
-#define HMATRIX_M5PR_OFFSET			20
-#define HMATRIX_M5PR_SIZE			4
-#define HMATRIX_M6PR_OFFSET			24
-#define HMATRIX_M6PR_SIZE			4
-#define HMATRIX_M7PR_OFFSET			28
-#define HMATRIX_M7PR_SIZE			4
-
-/* Bitfields in PRS.B */
-#define HMATRIX_M8PR_OFFSET			0
-#define HMATRIX_M8PR_SIZE			4
-#define HMATRIX_M9PR_OFFSET			4
-#define HMATRIX_M9PR_SIZE			4
-#define HMATRIX_M10PR_OFFSET			8
-#define HMATRIX_M10PR_SIZE			4
-#define HMATRIX_M11PR_OFFSET			12
-#define HMATRIX_M11PR_SIZE			4
-#define HMATRIX_M12PR_OFFSET			16
-#define HMATRIX_M12PR_SIZE			4
-#define HMATRIX_M13PR_OFFSET			20
-#define HMATRIX_M13PR_SIZE			4
-#define HMATRIX_M14PR_OFFSET			24
-#define HMATRIX_M14PR_SIZE			4
-#define HMATRIX_M15PR_OFFSET			28
-#define HMATRIX_M15PR_SIZE			4
-
-/* Constants for ULBT */
-#define HMATRIX_ULBT_INFINITE			0
-#define HMATRIX_ULBT_SINGLE			1
-#define HMATRIX_ULBT_FOUR_BEAT			2
-#define HMATRIX_ULBT_EIGHT_BEAT			3
-#define HMATRIX_ULBT_SIXTEEN_BEAT		4
-
-/* Constants for DEFMSTR_TYPE */
-#define HMATRIX_DEFMSTR_TYPE_NO_DEFAULT		0
-#define HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT	1
-#define HMATRIX_DEFMSTR_TYPE_FIXED_DEFAULT	2
-
-/* Constants for ARBT */
-#define HMATRIX_ARBT_ROUND_ROBIN		0
-#define HMATRIX_ARBT_FIXED_PRIORITY		1
-
-/* Bit manipulation macros */
-#define HMATRIX_BIT(name)					\
-	(1 << HMATRIX_##name##_OFFSET)
-#define HMATRIX_BF(name,value)					\
-	(((value) & ((1 << HMATRIX_##name##_SIZE) - 1))		\
-	 << HMATRIX_##name##_OFFSET)
-#define HMATRIX_BFEXT(name,value)				\
-	(((value) >> HMATRIX_##name##_OFFSET)			\
-	 & ((1 << HMATRIX_##name##_SIZE) - 1))
-#define HMATRIX_BFINS(name,value,old)				\
-	(((old) & ~(((1 << HMATRIX_##name##_SIZE) - 1)		\
-		    << HMATRIX_##name##_OFFSET))		\
-	 | HMATRIX_BF(name,value))
-
-/* Register access macros */
-#define __hmatrix_reg(reg)					\
-	(((volatile struct hmatrix_regs *)ATMEL_BASE_HMATRIX)->reg)
-#define hmatrix_read(reg)					\
-	(__hmatrix_reg(reg))
-#define hmatrix_write(reg, value)				\
-	do { __hmatrix_reg(reg) = (value); } while (0)
-
-#define hmatrix_slave_read(slave, reg)				\
-	hmatrix_read(reg[HMATRIX_SLAVE_##slave])
-#define hmatrix_slave_write(slave, reg, value)			\
-	hmatrix_write(reg[HMATRIX_SLAVE_##slave], value)
-
-#endif /* __ASM_AVR32_HMATRIX_COMMON_H__ */

arch/avr32/include/asm/io.h

@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_IO_H
-#define __ASM_AVR32_IO_H
-
-#include <asm/types.h>
-
-#ifdef __KERNEL__
-
-/*
- * Generic IO read/write.  These perform native-endian accesses.  Note
- * that some architectures will want to re-define __raw_{read,write}w.
- */
-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
-
-extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
-extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
-extern void __raw_readsl(unsigned int addr, void *data, int longlen);
-
-#define __raw_writeb(v,a)       (*(volatile unsigned char  *)(a) = (v))
-#define __raw_writew(v,a)       (*(volatile unsigned short *)(a) = (v))
-#define __raw_writel(v,a)       (*(volatile unsigned int   *)(a) = (v))
-
-#define __raw_readb(a)          (*(volatile unsigned char  *)(a))
-#define __raw_readw(a)          (*(volatile unsigned short *)(a))
-#define __raw_readl(a)          (*(volatile unsigned int   *)(a))
-
-/* As long as I/O is only performed in P4 (or possibly P3), we're safe */
-#define writeb(v,a)		__raw_writeb(v,a)
-#define writew(v,a)		__raw_writew(v,a)
-#define writel(v,a)		__raw_writel(v,a)
-
-#define readb(a)		__raw_readb(a)
-#define readw(a)		__raw_readw(a)
-#define readl(a)		__raw_readl(a)
-
-/*
- * Bad read/write accesses...
- */
-extern void __readwrite_bug(const char *fn);
-
-#define IO_SPACE_LIMIT	0xffffffff
-
-/*
- * All I/O is memory mapped, so these macros doesn't make very much sense
- */
-#define outb(v,p)		__raw_writeb(v, p)
-#define outw(v,p)		__raw_writew(cpu_to_le16(v),p)
-#define outl(v,p)		__raw_writel(cpu_to_le32(v),p)
-
-#define inb(p)	({ unsigned int __v = __raw_readb(p); __v; })
-#define inw(p)	({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
-#define inl(p)	({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
-
-#include <asm/arch/addrspace.h>
-/* Provides virt_to_phys, phys_to_virt, cached, uncached, map_physmem */
-
-#endif /* __KERNEL__ */
-
-static inline void sync(void)
-{
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long len)
-{
-
-}
-
-#endif /* __ASM_AVR32_IO_H */

arch/avr32/include/asm/posix_types.h

@@ -1,128 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_POSIX_TYPES_H
-#define __ASM_AVR32_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long	__kernel_dev_t;
-typedef unsigned long	__kernel_ino_t;
-typedef unsigned short	__kernel_mode_t;
-typedef unsigned short	__kernel_nlink_t;
-typedef long		__kernel_off_t;
-typedef int		__kernel_pid_t;
-typedef unsigned short	__kernel_ipc_pid_t;
-typedef unsigned int	__kernel_uid_t;
-typedef unsigned int	__kernel_gid_t;
-typedef unsigned long	__kernel_size_t;
-typedef int		__kernel_ssize_t;
-typedef int		__kernel_ptrdiff_t;
-typedef long		__kernel_time_t;
-typedef long		__kernel_suseconds_t;
-typedef long		__kernel_clock_t;
-typedef int		__kernel_timer_t;
-typedef int		__kernel_clockid_t;
-typedef int		__kernel_daddr_t;
-typedef char *		__kernel_caddr_t;
-typedef unsigned short	__kernel_uid16_t;
-typedef unsigned short	__kernel_gid16_t;
-typedef unsigned int	__kernel_uid32_t;
-typedef unsigned int	__kernel_gid32_t;
-
-typedef unsigned short	__kernel_old_uid_t;
-typedef unsigned short	__kernel_old_gid_t;
-typedef unsigned short	__kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long	__kernel_loff_t;
-#endif
-
-typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
-	int	val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-	int	__val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef  __FD_SET
-static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
-}
-
-#undef  __FD_CLR
-static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
-}
-
-
-#undef  __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
-{
-	unsigned long __tmp = __fd / __NFDBITS;
-	unsigned long __rem = __fd % __NFDBITS;
-	return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef  __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
-{
-	unsigned long *__tmp = __p->fds_bits;
-	int __i;
-
-	if (__builtin_constant_p(__FDSET_LONGS)) {
-		switch (__FDSET_LONGS) {
-		case 16:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			__tmp[ 4] = 0; __tmp[ 5] = 0;
-			__tmp[ 6] = 0; __tmp[ 7] = 0;
-			__tmp[ 8] = 0; __tmp[ 9] = 0;
-			__tmp[10] = 0; __tmp[11] = 0;
-			__tmp[12] = 0; __tmp[13] = 0;
-			__tmp[14] = 0; __tmp[15] = 0;
-			return;
-
-		case 8:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			__tmp[ 4] = 0; __tmp[ 5] = 0;
-			__tmp[ 6] = 0; __tmp[ 7] = 0;
-			return;
-
-		case 4:
-			__tmp[ 0] = 0; __tmp[ 1] = 0;
-			__tmp[ 2] = 0; __tmp[ 3] = 0;
-			return;
-		}
-	}
-	__i = __FDSET_LONGS;
-	while (__i) {
-		__i--;
-		*__tmp = 0;
-		__tmp++;
-	}
-}
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* __ASM_AVR32_POSIX_TYPES_H */

arch/avr32/include/asm/processor.h

@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_PROCESSOR_H
-#define __ASM_AVR32_PROCESSOR_H
-
-#ifndef __ASSEMBLY__
-
-#define current_text_addr() ({ void *pc; __asm__("mov %0,pc" : "=r"(pc)); pc; })
-
-struct avr32_cpuinfo {
-	unsigned long loops_per_jiffy;
-};
-
-extern struct avr32_cpuinfo boot_cpu_data;
-
-#ifdef CONFIG_SMP
-extern struct avr32_cpuinfo cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#else
-#define cpu_data (&boot_cpu_data)
-#define current_cpu_data boot_cpu_data
-#endif
-
-/* TODO: Make configurable (2GB will serve as a reasonable default) */
-#define TASK_SIZE	0x80000000
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's
- */
-#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
-
-#define cpu_relax()		barrier()
-#define cpu_sync_pipeline()	asm volatile("sub pc, -2" : : : "memory")
-
-/* This struct contains the CPU context as stored by switch_to() */
-struct thread_struct {
-	unsigned long pc;
-	unsigned long ksp;	/* Kernel stack pointer */
-	unsigned long r7;
-	unsigned long r6;
-	unsigned long r5;
-	unsigned long r4;
-	unsigned long r3;
-	unsigned long r2;
-	unsigned long r1;
-	unsigned long r0;
-};
-
-#define INIT_THREAD {						\
-	.ksp = sizeof(init_stack) + (long)&init_stack,		\
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- */
-#define start_thread(regs, new_pc, new_sp)	 \
-	set_fs(USER_DS);			 \
-	regs->sr = 0;		/* User mode. */ \
-	regs->gr[REG_PC] = new_pc;		 \
-	regs->gr[REG_SP] = new_sp
-
-struct task_struct;
-
-/* Free all resources held by a thread */
-extern void release_thread(struct task_struct *);
-
-/* Create a kernel thread without removing it from tasklists */
-extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk) do { } while(0)
-
-/* Return saved PC of a blocked thread */
-#define thread_saved_pc(tsk)    (tsk->thread.pc)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_AVR32_PROCESSOR_H */

arch/avr32/include/asm/ptrace.h

@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_PTRACE_H
-#define __ASM_AVR32_PTRACE_H
-
-/*
- * Status Register bits
- */
-#define SR_H		0x40000000
-#define SR_R		0x20000000
-#define SR_J		0x10000000
-#define SR_DM		0x08000000
-#define SR_D		0x04000000
-#define MODE_NMI	0x01c00000
-#define MODE_EXCEPTION	0x01800000
-#define MODE_INT3	0x01400000
-#define MODE_INT2	0x01000000
-#define MODE_INT1	0x00c00000
-#define MODE_INT0	0x00800000
-#define MODE_SUPERVISOR	0x00400000
-#define MODE_USER	0x00000000
-#define MODE_MASK	0x01c00000
-#define SR_EM		0x00200000
-#define SR_I3M		0x00100000
-#define SR_I2M		0x00080000
-#define SR_I1M		0x00040000
-#define SR_I0M		0x00020000
-#define SR_GM		0x00010000
-
-#define MODE_SHIFT	22
-#define SR_EM_BIT	21
-#define SR_I3M_BIT	20
-#define SR_I2M_BIT	19
-#define SR_I1M_BIT	18
-#define SR_I0M_BIT	17
-#define SR_GM_BIT	16
-
-/* The user-visible part */
-#define SR_Q		0x00000010
-#define SR_V		0x00000008
-#define SR_N		0x00000004
-#define SR_Z		0x00000002
-#define SR_C		0x00000001
-
-/*
- * The order is defined by the stdsp instruction. r0 is stored first, so it
- * gets the highest address.
- *
- * Registers 0-12 are general-purpose registers (r12 is normally used for
- * the function return value).
- * Register 13 is the stack pointer
- * Register 14 is the link register
- * Register 15 is the program counter
- */
-#define FRAME_SIZE_FULL 72
-#define REG_R12_ORIG	68
-#define REG_R0		64
-#define REG_R1		60
-#define REG_R2		56
-#define REG_R3		52
-#define REG_R4		48
-#define REG_R5		44
-#define REG_R6		40
-#define REG_R7		36
-#define REG_R8		32
-#define REG_R9		28
-#define REG_R10		34
-#define REG_R11		20
-#define REG_R12		16
-#define REG_SP		12
-#define REG_LR		 8
-
-#define FRAME_SIZE_MIN	 8
-#define REG_PC		 4
-#define REG_SR		 0
-
-#ifndef __ASSEMBLY__
-struct pt_regs {
-	/* These are always saved */
-	unsigned long sr;
-	unsigned long pc;
-
-	/* These are sometimes saved */
-	unsigned long lr;
-	unsigned long sp;
-	unsigned long r12;
-	unsigned long r11;
-	unsigned long r10;
-	unsigned long r9;
-	unsigned long r8;
-	unsigned long r7;
-	unsigned long r6;
-	unsigned long r5;
-	unsigned long r4;
-	unsigned long r3;
-	unsigned long r2;
-	unsigned long r1;
-	unsigned long r0;
-
-	/* Only saved on system call */
-	unsigned long r12_orig;
-};
-
-#ifdef __KERNEL__
-# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
-# define instruction_pointer(regs) ((regs)->pc)
-extern void show_regs (struct pt_regs *);
-
-static __inline__ int valid_user_regs(struct pt_regs *regs)
-{
-	/*
-	 * Some of the Java bits might be acceptable if/when we
-	 * implement some support for that stuff...
-	 */
-	if ((regs->sr & 0xffff0000) == 0)
-		return 1;
-
-	/*
-	 * Force status register flags to be sane and report this
-	 * illegal behaviour...
-	 */
-	regs->sr &= 0x0000ffff;
-	return 0;
-}
-#endif
-
-#endif /* ! __ASSEMBLY__ */
-
-#endif /* __ASM_AVR32_PTRACE_H */

arch/avr32/include/asm/sdram.h

@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_SDRAM_H
-#define __ASM_AVR32_SDRAM_H
-
-struct sdram_config {
-	/* Number of data bits. */
-	enum {
-		SDRAM_DATA_16BIT = 16,
-		SDRAM_DATA_32BIT = 32,
-	} data_bits;
-
-	/* Number of address bits */
-	uint8_t row_bits, col_bits, bank_bits;
-
-	/* SDRAM timings in cycles */
-	uint8_t cas, twr, trc, trp, trcd, tras, txsr;
-
-	/* SDRAM refresh period in cycles */
-	unsigned long refresh_period;
-};
-
-/*
- * Attempt to initialize the SDRAM controller using the specified
- * parameters. Return the expected size of the memory area based on
- * the number of address and data bits.
- *
- * The caller should verify that the configuration is correct by
- * running a memory test, e.g. get_ram_size().
- */
-extern unsigned long sdram_init(void *sdram_base,
-			const struct sdram_config *config);
-
-#endif /* __ASM_AVR32_SDRAM_H */

arch/avr32/include/asm/sections.h

@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_SECTIONS_H
-#define __ASM_AVR32_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-/* References to section boundaries */
-
-extern char __data_lma[], __edata_lma[];
-extern char __got_start[], __got_lma[], __got_end[];
-
-#endif /* __ASM_AVR32_SECTIONS_H */

arch/avr32/include/asm/setup.h

@@ -1,134 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * Based on linux/include/asm-arm/setup.h
- *   Copyright (C) 1997-1999 Russel King
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_SETUP_H__
-#define __ASM_AVR32_SETUP_H__
-
-#define COMMAND_LINE_SIZE 256
-
-/* Magic number indicating that a tag table is present */
-#define ATAG_MAGIC	0xa2a25441
-
-#ifndef __ASSEMBLY__
-
-/*
- * Generic memory range, used by several tags.
- *
- *   addr is always physical.
- *   size is measured in bytes.
- *   next is for use by the OS, e.g. for grouping regions into
- *	  linked lists.
- */
-struct tag_mem_range {
-	u32			addr;
-	u32			size;
-	struct tag_mem_range *	next;
-};
-
-/* The list ends with an ATAG_NONE node. */
-#define ATAG_NONE	0x00000000
-
-struct tag_header {
-	u32 size;
-	u32 tag;
-};
-
-/* The list must start with an ATAG_CORE node */
-#define ATAG_CORE	0x54410001
-
-struct tag_core {
-	u32 flags;
-	u32 pagesize;
-	u32 rootdev;
-};
-
-/* it is allowed to have multiple ATAG_MEM nodes */
-#define ATAG_MEM	0x54410002
-/* ATAG_MEM uses tag_mem_range */
-
-/* command line: \0 terminated string */
-#define ATAG_CMDLINE	0x54410003
-
-struct tag_cmdline {
-	char	cmdline[1];	/* this is the minimum size */
-};
-
-/* Ramdisk image (may be compressed) */
-#define ATAG_RDIMG	0x54410004
-/* ATAG_RDIMG uses tag_mem_range */
-
-/* Information about various clocks present in the system */
-#define ATAG_CLOCK	0x54410005
-
-struct tag_clock {
-	u32	clock_id;	/* Which clock are we talking about? */
-	u32	clock_flags;	/* Special features */
-	u64	clock_hz;	/* Clock speed in Hz */
-};
-
-/* The clock types we know about */
-#define ACLOCK_BOOTCPU	0	/* The CPU we're booting from */
-#define ACLOCK_HSB	1	/* Deprecated */
-
-/* Memory reserved for the system (e.g. the bootloader) */
-#define ATAG_RSVD_MEM	0x54410006
-/* ATAG_RSVD_MEM uses tag_mem_range */
-
-/* Ethernet information */
-
-#define ATAG_ETHERNET	0x54410007
-
-struct tag_ethernet {
-	u8	mac_index;
-	u8	mii_phy_addr;
-	u8	hw_address[6];
-};
-
-#define AETH_INVALID_PHY	0xff
-
-/* board information information */
-#define ATAG_BOARDINFO	0x54410008
-
-struct tag_boardinfo {
-	u32	board_number;
-};
-
-struct tag {
-	struct tag_header hdr;
-	union {
-		struct tag_core core;
-		struct tag_mem_range mem_range;
-		struct tag_cmdline cmdline;
-		struct tag_clock clock;
-		struct tag_ethernet ethernet;
-		struct tag_boardinfo boardinfo;
-	} u;
-};
-
-struct tagtable {
-	u32	tag;
-	int	(*parse)(struct tag *);
-};
-
-#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
-#define __tagtable(tag, fn)						\
-	static struct tagtable __tagtable_##fn __tag = { tag, fn }
-
-#define tag_member_present(tag,member)					\
-	((unsigned long)(&((struct tag *)0L)->member + 1)		\
-	 <= (tag)->hdr.size * 4)
-
-#define tag_next(t)	((struct tag *)((u32 *)(t) + (t)->hdr.size))
-#define tag_size(type)	((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
-
-#define for_each_tag(t,base)						\
-	for (t = base; t->hdr.size; t = tag_next(t))
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __ASM_AVR32_SETUP_H__ */

arch/avr32/include/asm/string.h

@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_STRING_H
-#define __ASM_AVR32_STRING_H
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, __kernel_size_t n);
-
-#endif /* __ASM_AVR32_STRING_H */

arch/avr32/include/asm/sysreg.h

@@ -1,281 +0,0 @@
-/*
- * System registers for AVR32
- */
-#ifndef __ASM_AVR32_SYSREG_H__
-#define __ASM_AVR32_SYSREG_H__
-
-/* system register offsets */
-#define SYSREG_SR			0x0000
-#define SYSREG_EVBA			0x0004
-#define SYSREG_ACBA			0x0008
-#define SYSREG_CPUCR			0x000c
-#define SYSREG_ECR			0x0010
-#define SYSREG_RSR_SUP			0x0014
-#define SYSREG_RSR_INT0			0x0018
-#define SYSREG_RSR_INT1			0x001c
-#define SYSREG_RSR_INT2			0x0020
-#define SYSREG_RSR_INT3			0x0024
-#define SYSREG_RSR_EX			0x0028
-#define SYSREG_RSR_NMI			0x002c
-#define SYSREG_RSR_DBG			0x0030
-#define SYSREG_RAR_SUP			0x0034
-#define SYSREG_RAR_INT0			0x0038
-#define SYSREG_RAR_INT1			0x003c
-#define SYSREG_RAR_INT2			0x0040
-#define SYSREG_RAR_INT3			0x0044
-#define SYSREG_RAR_EX			0x0048
-#define SYSREG_RAR_NMI			0x004c
-#define SYSREG_RAR_DBG			0x0050
-#define SYSREG_JECR			0x0054
-#define SYSREG_JOSP			0x0058
-#define SYSREG_JAVA_LV0			0x005c
-#define SYSREG_JAVA_LV1			0x0060
-#define SYSREG_JAVA_LV2			0x0064
-#define SYSREG_JAVA_LV3			0x0068
-#define SYSREG_JAVA_LV4			0x006c
-#define SYSREG_JAVA_LV5			0x0070
-#define SYSREG_JAVA_LV6			0x0074
-#define SYSREG_JAVA_LV7			0x0078
-#define SYSREG_JTBA			0x007c
-#define SYSREG_JBCR			0x0080
-#define SYSREG_CONFIG0			0x0100
-#define SYSREG_CONFIG1			0x0104
-#define SYSREG_COUNT			0x0108
-#define SYSREG_COMPARE			0x010c
-#define SYSREG_TLBEHI			0x0110
-#define SYSREG_TLBELO			0x0114
-#define SYSREG_PTBR			0x0118
-#define SYSREG_TLBEAR			0x011c
-#define SYSREG_MMUCR			0x0120
-#define SYSREG_TLBARLO			0x0124
-#define SYSREG_TLBARHI			0x0128
-#define SYSREG_PCCNT			0x012c
-#define SYSREG_PCNT0			0x0130
-#define SYSREG_PCNT1			0x0134
-#define SYSREG_PCCR			0x0138
-#define SYSREG_BEAR			0x013c
-#define SYSREG_SABAL			0x0300
-#define SYSREG_SABAH			0x0304
-#define SYSREG_SABD			0x0308
-
-/* Bitfields in SR */
-#define SYSREG_SR_C_OFFSET		0
-#define SYSREG_SR_C_SIZE		1
-#define SYSREG_Z_OFFSET			1
-#define SYSREG_Z_SIZE			1
-#define SYSREG_SR_N_OFFSET		2
-#define SYSREG_SR_N_SIZE		1
-#define SYSREG_SR_V_OFFSET		3
-#define SYSREG_SR_V_SIZE		1
-#define SYSREG_Q_OFFSET			4
-#define SYSREG_Q_SIZE			1
-#define SYSREG_L_OFFSET			5
-#define SYSREG_L_SIZE			1
-#define SYSREG_T_OFFSET			14
-#define SYSREG_T_SIZE			1
-#define SYSREG_SR_R_OFFSET		15
-#define SYSREG_SR_R_SIZE		1
-#define SYSREG_GM_OFFSET		16
-#define SYSREG_GM_SIZE			1
-#define SYSREG_I0M_OFFSET		17
-#define SYSREG_I0M_SIZE			1
-#define SYSREG_I1M_OFFSET		18
-#define SYSREG_I1M_SIZE			1
-#define SYSREG_I2M_OFFSET		19
-#define SYSREG_I2M_SIZE			1
-#define SYSREG_I3M_OFFSET		20
-#define SYSREG_I3M_SIZE			1
-#define SYSREG_EM_OFFSET		21
-#define SYSREG_EM_SIZE			1
-#define SYSREG_M0_OFFSET		22
-#define SYSREG_M0_SIZE			1
-#define SYSREG_M1_OFFSET		23
-#define SYSREG_M1_SIZE			1
-#define SYSREG_M2_OFFSET		24
-#define SYSREG_M2_SIZE			1
-#define SYSREG_SR_D_OFFSET		26
-#define SYSREG_SR_D_SIZE		1
-#define SYSREG_DM_OFFSET		27
-#define SYSREG_DM_SIZE			1
-#define SYSREG_SR_J_OFFSET		28
-#define SYSREG_SR_J_SIZE		1
-#define SYSREG_H_OFFSET			29
-#define SYSREG_H_SIZE			1
-
-/* Bitfields in CPUCR */
-#define SYSREG_BI_OFFSET		0
-#define SYSREG_BI_SIZE			1
-#define SYSREG_BE_OFFSET		1
-#define SYSREG_BE_SIZE			1
-#define SYSREG_FE_OFFSET		2
-#define SYSREG_FE_SIZE			1
-#define SYSREG_RE_OFFSET		3
-#define SYSREG_RE_SIZE			1
-#define SYSREG_IBE_OFFSET		4
-#define SYSREG_IBE_SIZE			1
-#define SYSREG_IEE_OFFSET		5
-#define SYSREG_IEE_SIZE			1
-
-/* Bitfields in ECR */
-#define SYSREG_ECR_OFFSET		0
-#define SYSREG_ECR_SIZE			32
-
-/* Bitfields in CONFIG0 */
-#define SYSREG_CONFIG0_R_OFFSET		0
-#define SYSREG_CONFIG0_R_SIZE		1
-#define SYSREG_CONFIG0_D_OFFSET		1
-#define SYSREG_CONFIG0_D_SIZE		1
-#define SYSREG_CONFIG0_S_OFFSET		2
-#define SYSREG_CONFIG0_S_SIZE		1
-#define SYSREG_O_OFFSET			3
-#define SYSREG_O_SIZE			1
-#define SYSREG_P_OFFSET			4
-#define SYSREG_P_SIZE			1
-#define SYSREG_CONFIG0_J_OFFSET		5
-#define SYSREG_CONFIG0_J_SIZE		1
-#define SYSREG_F_OFFSET			6
-#define SYSREG_F_SIZE			1
-#define SYSREG_MMUT_OFFSET		7
-#define SYSREG_MMUT_SIZE		3
-#define SYSREG_AR_OFFSET		10
-#define SYSREG_AR_SIZE			3
-#define SYSREG_AT_OFFSET		13
-#define SYSREG_AT_SIZE			3
-#define SYSREG_PROCESSORREVISION_OFFSET	16
-#define SYSREG_PROCESSORREVISION_SIZE	8
-#define SYSREG_PROCESSORID_OFFSET	24
-#define SYSREG_PROCESSORID_SIZE		8
-
-/* Bitfields in CONFIG1 */
-#define SYSREG_DASS_OFFSET		0
-#define SYSREG_DASS_SIZE		3
-#define SYSREG_DLSZ_OFFSET		3
-#define SYSREG_DLSZ_SIZE		3
-#define SYSREG_DSET_OFFSET		6
-#define SYSREG_DSET_SIZE		4
-#define SYSREG_IASS_OFFSET		10
-#define SYSREG_IASS_SIZE		3
-#define SYSREG_ILSZ_OFFSET		13
-#define SYSREG_ILSZ_SIZE		3
-#define SYSREG_ISET_OFFSET		16
-#define SYSREG_ISET_SIZE		4
-#define SYSREG_DMMUSZ_OFFSET		20
-#define SYSREG_DMMUSZ_SIZE		6
-#define SYSREG_IMMUSZ_OFFSET		26
-#define SYSREG_IMMUSZ_SIZE		6
-
-/* Bitfields in TLBEHI */
-#define SYSREG_ASID_OFFSET		0
-#define SYSREG_ASID_SIZE		8
-#define SYSREG_TLBEHI_I_OFFSET		8
-#define SYSREG_TLBEHI_I_SIZE		1
-#define SYSREG_TLBEHI_V_OFFSET		9
-#define SYSREG_TLBEHI_V_SIZE		1
-#define SYSREG_VPN_OFFSET		10
-#define SYSREG_VPN_SIZE			22
-
-/* Bitfields in TLBELO */
-#define SYSREG_W_OFFSET			0
-#define SYSREG_W_SIZE			1
-#define SYSREG_TLBELO_D_OFFSET		1
-#define SYSREG_TLBELO_D_SIZE		1
-#define SYSREG_SZ_OFFSET		2
-#define SYSREG_SZ_SIZE			2
-#define SYSREG_AP_OFFSET		4
-#define SYSREG_AP_SIZE			3
-#define SYSREG_B_OFFSET			7
-#define SYSREG_B_SIZE			1
-#define SYSREG_G_OFFSET			8
-#define SYSREG_G_SIZE			1
-#define SYSREG_TLBELO_C_OFFSET		9
-#define SYSREG_TLBELO_C_SIZE		1
-#define SYSREG_PFN_OFFSET		10
-#define SYSREG_PFN_SIZE			22
-
-/* Bitfields in MMUCR */
-#define SYSREG_E_OFFSET			0
-#define SYSREG_E_SIZE			1
-#define SYSREG_M_OFFSET			1
-#define SYSREG_M_SIZE			1
-#define SYSREG_MMUCR_I_OFFSET		2
-#define SYSREG_MMUCR_I_SIZE		1
-#define SYSREG_MMUCR_N_OFFSET		3
-#define SYSREG_MMUCR_N_SIZE		1
-#define SYSREG_MMUCR_S_OFFSET		4
-#define SYSREG_MMUCR_S_SIZE		1
-#define SYSREG_DLA_OFFSET		8
-#define SYSREG_DLA_SIZE			6
-#define SYSREG_DRP_OFFSET		14
-#define SYSREG_DRP_SIZE			6
-#define SYSREG_ILA_OFFSET		20
-#define SYSREG_ILA_SIZE			6
-#define SYSREG_IRP_OFFSET		26
-#define SYSREG_IRP_SIZE			6
-
-/* Bitfields in PCCR */
-#define SYSREG_PCCR_R_OFFSET		1
-#define SYSREG_PCCR_R_SIZE		1
-#define SYSREG_PCCR_C_OFFSET		2
-#define SYSREG_PCCR_C_SIZE		1
-#define SYSREG_PCCR_S_OFFSET		3
-#define SYSREG_PCCR_S_SIZE		1
-#define SYSREG_IEC_OFFSET		4
-#define SYSREG_IEC_SIZE			1
-#define SYSREG_IE0_OFFSET		5
-#define SYSREG_IE0_SIZE			1
-#define SYSREG_IE1_OFFSET		6
-#define SYSREG_IE1_SIZE			1
-#define SYSREG_FC_OFFSET		8
-#define SYSREG_FC_SIZE			1
-#define SYSREG_F0_OFFSET		9
-#define SYSREG_F0_SIZE			1
-#define SYSREG_F1_OFFSET		10
-#define SYSREG_F1_SIZE			1
-#define SYSREG_CONF0_OFFSET		12
-#define SYSREG_CONF0_SIZE		6
-#define SYSREG_CONF1_OFFSET		18
-#define SYSREG_CONF1_SIZE		6
-
-/* Constants for ECR */
-#define ECR_UNRECOVERABLE		0
-#define ECR_TLB_MULTIPLE		1
-#define ECR_BUS_ERROR_WRITE		2
-#define ECR_BUS_ERROR_READ		3
-#define ECR_NMI				4
-#define ECR_ADDR_ALIGN_X		5
-#define ECR_PROTECTION_X		6
-#define ECR_DEBUG			7
-#define ECR_ILLEGAL_OPCODE		8
-#define ECR_UNIMPL_INSTRUCTION		9
-#define ECR_PRIVILEGE_VIOLATION		10
-#define ECR_FPE				11
-#define ECR_COPROC_ABSENT		12
-#define ECR_ADDR_ALIGN_R		13
-#define ECR_ADDR_ALIGN_W		14
-#define ECR_PROTECTION_R		15
-#define ECR_PROTECTION_W		16
-#define ECR_DTLB_MODIFIED		17
-#define ECR_TLB_MISS_X			20
-#define ECR_TLB_MISS_R			24
-#define ECR_TLB_MISS_W			28
-
-/* Bit manipulation macros */
-#define SYSREG_BIT(name)		(1 << SYSREG_##name##_OFFSET)
-#define SYSREG_BF(name,value)				\
-	(((value) & ((1 << SYSREG_##name##_SIZE) - 1))	\
-	 << SYSREG_##name##_OFFSET)
-#define SYSREG_BFEXT(name,value)			\
-	(((value) >> SYSREG_##name##_OFFSET)		\
-	 & ((1 << SYSREG_##name##_SIZE) - 1))
-#define SYSREG_BFINS(name,value,old)			\
-	(((old) & ~(((1 << SYSREG_##name##_SIZE) - 1)	\
-		    << SYSREG_##name##_OFFSET))		\
-	 | SYSREG_BF(name,value))
-
-/* Register access macros */
-#define sysreg_read(reg)				\
-	((unsigned long)__builtin_mfsr(SYSREG_##reg))
-#define sysreg_write(reg, value)			\
-	__builtin_mtsr(SYSREG_##reg, value)
-
-#endif /* __ASM_AVR32_SYSREG_H__ */

arch/avr32/include/asm/types.h

@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_AVR32_TYPES_H
-#define __ASM_AVR32_TYPES_H
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-/*
- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
- * header files exported to user space
- */
-typedef __signed__ char __s8;
-typedef unsigned char __u8;
-
-typedef __signed__ short __s16;
-typedef unsigned short __u16;
-
-typedef __signed__ int __s32;
-typedef unsigned int __u32;
-
-#if defined(__GNUC__)
-__extension__ typedef __signed__ long long __s64;
-__extension__ typedef unsigned long long __u64;
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#ifndef __ASSEMBLY__
-
-typedef __signed__ char s8;
-typedef unsigned char u8;
-
-typedef __signed__ short s16;
-typedef unsigned short u16;
-
-typedef __signed__ int s32;
-typedef unsigned int u32;
-
-typedef __signed__ long long s64;
-typedef unsigned long long u64;
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#ifdef CONFIG_LBD
-typedef u64 sector_t;
-#define HAVE_SECTOR_T
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-
-#endif /* __ASM_AVR32_TYPES_H */

arch/avr32/include/asm/u-boot.h

@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __ASM_U_BOOT_H__
-#define __ASM_U_BOOT_H__ 1
-
-/* Use the generic board which requires a unified bd_info */
-#include <asm-generic/u-boot.h>
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_AVR32
-
-int arch_cpu_init(void);
-int dram_init(void);
-
-#endif /* __ASM_U_BOOT_H__ */

arch/avr32/include/asm/unaligned.h

@@ -1 +0,0 @@
-#include <asm-generic/unaligned.h>

arch/avr32/lib/Makefile

@@ -1,13 +0,0 @@
-#
-# (C) Copyright 2002-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	+= memset.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-y	+= interrupts.o
-obj-y	+= dram_init.o

arch/avr32/lib/bootm.c

@@ -1,213 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <image.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-#include <asm/arch/addrspace.h>
-#include <asm/io.h>
-#include <asm/setup.h>
-#include <asm/arch/clk.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* CPU-specific hook to allow flushing of caches, etc. */
-extern void prepare_to_boot(void);
-
-static struct tag *setup_start_tag(struct tag *params)
-{
-	params->hdr.tag = ATAG_CORE;
-	params->hdr.size = tag_size(tag_core);
-
-	params->u.core.flags = 0;
-	params->u.core.pagesize = 4096;
-	params->u.core.rootdev = 0;
-
-	return tag_next(params);
-}
-
-static struct tag *setup_memory_tags(struct tag *params)
-{
-	bd_t *bd = gd->bd;
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		params->hdr.tag = ATAG_MEM;
-		params->hdr.size = tag_size(tag_mem_range);
-
-		params->u.mem_range.addr = bd->bi_dram[i].start;
-		params->u.mem_range.size = bd->bi_dram[i].size;
-
-		params = tag_next(params);
-	}
-
-	return params;
-}
-
-static struct tag *setup_commandline_tag(struct tag *params, char *cmdline)
-{
-	if (!cmdline)
-		return params;
-
-	/* eat leading white space */
-	while (*cmdline == ' ') cmdline++;
-
-	/*
-	 * Don't include tags for empty command lines; let the kernel
-	 * use its default command line.
-	 */
-	if (*cmdline == '\0')
-		return params;
-
-	params->hdr.tag = ATAG_CMDLINE;
-	params->hdr.size =
-		(sizeof (struct tag_header) + strlen(cmdline) + 1 + 3) >> 2;
-	strcpy(params->u.cmdline.cmdline, cmdline);
-
-	return tag_next(params);
-}
-
-static struct tag *setup_ramdisk_tag(struct tag *params,
-				     unsigned long rd_start,
-				     unsigned long rd_end)
-{
-	if (rd_start == rd_end)
-		return params;
-
-	params->hdr.tag = ATAG_RDIMG;
-	params->hdr.size = tag_size(tag_mem_range);
-
-	params->u.mem_range.addr = rd_start;
-	params->u.mem_range.size = rd_end - rd_start;
-
-	return tag_next(params);
-}
-
-static struct tag *setup_clock_tags(struct tag *params)
-{
-	params->hdr.tag = ATAG_CLOCK;
-	params->hdr.size = tag_size(tag_clock);
-	params->u.clock.clock_id = ACLOCK_BOOTCPU;
-	params->u.clock.clock_flags = 0;
-	params->u.clock.clock_hz = gd->arch.cpu_hz;
-
-#ifdef CONFIG_AT32AP7000
-	/*
-	 * New kernels don't need this, but we should be backwards
-	 * compatible for a while...
-	 */
-	params = tag_next(params);
-
-	params->hdr.tag = ATAG_CLOCK;
-	params->hdr.size = tag_size(tag_clock);
-	params->u.clock.clock_id = ACLOCK_HSB;
-	params->u.clock.clock_flags = 0;
-	params->u.clock.clock_hz = get_hsb_clk_rate();
-#endif
-
-	return tag_next(params);
-}
-
-static struct tag *setup_ethernet_tag(struct tag *params,
-				      char *addr, int index)
-{
-	char *s, *e;
-	int i;
-
-	params->hdr.tag = ATAG_ETHERNET;
-	params->hdr.size = tag_size(tag_ethernet);
-
-	params->u.ethernet.mac_index = index;
-	params->u.ethernet.mii_phy_addr = gd->bd->bi_phy_id[index];
-
-	s = addr;
-	for (i = 0; i < 6; i++) {
-		params->u.ethernet.hw_address[i] = simple_strtoul(s, &e, 16);
-		s = e + 1;
-	}
-
-	return tag_next(params);
-}
-
-static struct tag *setup_ethernet_tags(struct tag *params)
-{
-	char name[16] = "ethaddr";
-	char *addr;
-	int i = 0;
-
-	do {
-		addr = getenv(name);
-		if (addr)
-			params = setup_ethernet_tag(params, addr, i);
-		sprintf(name, "eth%daddr", ++i);
-	} while (i < 4);
-
-	return params;
-}
-
-static struct tag *setup_boardinfo_tag(struct tag *params)
-{
-	params->hdr.tag = ATAG_BOARDINFO;
-	params->hdr.size = tag_size(tag_boardinfo);
-
-	params->u.boardinfo.board_number = gd->bd->bi_board_number;
-
-	return tag_next(params);
-}
-
-static void setup_end_tag(struct tag *params)
-{
-	params->hdr.tag = ATAG_NONE;
-	params->hdr.size = 0;
-}
-
-int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
-{
-	void	(*theKernel)(int magic, void *tagtable);
-	struct	tag *params, *params_start;
-	char	*commandline = getenv("bootargs");
-
-	/*
-	 * allow the PREP bootm subcommand, it is required for bootm to work
-	 *
-	 * TODO: Andreas Bießmann <andreas@biessmann.org> refactor the
-	 * do_bootm_linux() for avr32
-	 */
-	if (flag & BOOTM_STATE_OS_PREP)
-		return 0;
-
-	if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-		return 1;
-
-	theKernel = (void *)images->ep;
-
-	bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
-	params = params_start = (struct tag *)gd->bd->bi_boot_params;
-	params = setup_start_tag(params);
-	params = setup_memory_tags(params);
-	if (images->rd_start) {
-		params = setup_ramdisk_tag(params,
-					   PHYSADDR(images->rd_start),
-					   PHYSADDR(images->rd_end));
-	}
-	params = setup_commandline_tag(params, commandline);
-	params = setup_clock_tags(params);
-	params = setup_ethernet_tags(params);
-	params = setup_boardinfo_tag(params);
-	setup_end_tag(params);
-
-	printf("\nStarting kernel at %p (params at %p)...\n\n",
-	       theKernel, params_start);
-
-	prepare_to_boot();
-
-	theKernel(ATAG_MAGIC, params_start);
-	/* does not return */
-
-	return 1;
-}

arch/avr32/lib/dram_init.c

@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2015 Andreas Bießmann <andreas@biessmann.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-	/* check for the maximum amount of memory possible on AP7000 devices */
-	gd->ram_size = get_ram_size(
-		(void *)CONFIG_SYS_SDRAM_BASE,
-		(256<<20));
-	return 0;
-}

arch/avr32/lib/interrupts.c

@@ -1,35 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/sysreg.h>
-
-int interrupt_init(void)
-{
-	return 0;
-}
-
-void enable_interrupts(void)
-{
-	asm volatile("csrf	%0" : : "n"(SYSREG_GM_OFFSET));
-}
-
-int disable_interrupts(void)
-{
-	unsigned long sr;
-
-	sr = sysreg_read(SR);
-	asm volatile("ssrf	%0" : : "n"(SYSREG_GM_OFFSET));
-
-#ifdef CONFIG_AT32UC3A0xxx
-	/* Two NOPs are required after masking interrupts on the
-	 * AT32UC3A0512ES. See errata 41.4.5.5. */
-	asm("nop");
-	asm("nop");
-#endif
-
-	return !SYSREG_BFEXT(GM, sr);
-}

arch/avr32/lib/memset.S

@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-	/*
-	 * r12:	void *b
-	 * r11:	int c
-	 * r10:	size_t len
-	 *
-	 * Returns b in r12
-	 */
-	.section .text.memset, "ax", @progbits
-
-	.global	memset
-	.type	memset, @function
-	.align	2
-memset:
-	mov	r9, r12
-	mov	r8, r12
-	or	r11, r11, r11 << 8
-	andl	r9, 3, COH
-	brne	1f
-
-2:	or	r11, r11, r11 << 16
-	sub	r10, 4
-	brlt	5f
-
-	/* Let's do some real work */
-4:	st.w	r8++, r11
-	sub	r10, 4
-	brge	4b
-
-	/*
-	 * When we get here, we've got less than 4 bytes to set. r10
-	 * might be negative.
-	 */
-5:	sub	r10, -4
-	reteq	r12
-
-	/* Fastpath ends here, exactly 32 bytes from memset */
-
-	/* Handle unaligned count or pointer */
-	bld	r10, 1
-	brcc	6f
-	st.b	r8++, r11
-	st.b	r8++, r11
-	bld	r10, 0
-	retcc	r12
-6:	st.b	r8++, r11
-	mov	pc, lr
-
-	/* Handle unaligned pointer */
-1:	sub	r10, 4
-	brlt	5b
-	add	r10, r9
-	lsl	r9, 1
-	add	pc, r9
-	st.b	r8++, r11
-	st.b	r8++, r11
-	st.b	r8++, r11
-	rjmp	2b
-
-	.size	memset, . - memset

arch/powerpc/Kconfig

@@ -29,10 +29,14 @@ config MPC86xx
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
 
+config 8xx
+	bool "MPC8xx"
+
 endchoice
 
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc86xx/Kconfig"
+source "arch/powerpc/cpu/mpc8xx/Kconfig"
 
 endmenu

arch/powerpc/cpu/mpc8xx/Kconfig

@@ -0,0 +1,175 @@
+menu "mpc8xx CPU"
+	depends on 8xx
+
+config SYS_CPU
+	default "mpc8xx"
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_MCR3000
+	bool "Support MCR3000 board from CSSI"
+
+endchoice
+
+choice
+	prompt "CPU select"
+	default MPC866
+
+config MPC866
+	bool "MPC866"
+
+config MPC885
+	bool "MPC885"
+
+endchoice
+
+config 8xx_GCLK_FREQ
+	int "CPU GCLK Frequency"
+
+comment "Specific commands"
+
+config CMD_IMMAP
+	bool "Enable various commands to dump IMMR information"
+	help
+	  This enables various commands such as:
+
+	    siuinfo - print System Interface Unit (SIU) registers
+	    memcinfo - print Memory Controller registers
+
+comment "Configuration Registers"
+
+config SYS_SIUMCR
+	hex "SIUMCR register"
+	help
+	  SIU Module Configuration (11-6)
+
+config SYS_SYPCR
+	hex "SYPCR register"
+	help
+	  System Protection Control (11-9)
+
+config SYS_TBSCR
+	hex "TBSCR register"
+	help
+	  Time Base Status and Control (11-26)
+
+config SYS_PISCR
+	hex "PISCR register"
+	help
+	  Periodic Interrupt Status and Control (11-31)
+
+config SYS_PLPRCR_BOOL
+	bool "Customise PLPRCR"
+
+config SYS_PLPRCR
+	hex "PLPRCR register"
+	depends on SYS_PLPRCR_BOOL
+	help
+	  PLL, Low-Power, and Reset Control Register (15-30)
+
+config SYS_SCCR
+	hex "SCCR register"
+	help
+	  System Clock and reset Control Register (15-27)
+
+config SYS_SCCR_MASK
+	hex "MASK for setting SCCR register"
+
+config SYS_DER
+	hex "DER register"
+	help
+	  Debug Event Register (37-47)
+
+comment "Memory mapping"
+
+config SYS_BR0_PRELIM
+	hex "Preliminary value for BR0"
+
+config SYS_OR0_PRELIM
+	hex "Preliminary value for OR0"
+
+config SYS_BR1_PRELIM_BOOL
+	bool "Define Bank 1"
+
+config SYS_BR1_PRELIM
+	hex "Preliminary value for BR1"
+	depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_OR1_PRELIM
+	hex "Preliminary value for OR1"
+	depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_BR2_PRELIM_BOOL
+	bool "Define Bank 2"
+
+config SYS_BR2_PRELIM
+	hex "Preliminary value for BR2"
+	depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_OR2_PRELIM
+	hex "Preliminary value for OR2"
+	depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_BR3_PRELIM_BOOL
+	bool "Define Bank 3"
+
+config SYS_BR3_PRELIM
+	hex "Preliminary value for BR3"
+	depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_OR3_PRELIM
+	hex "Preliminary value for OR3"
+	depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_BR4_PRELIM_BOOL
+	bool "Define Bank 4"
+
+config SYS_BR4_PRELIM
+	hex "Preliminary value for BR4"
+	depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_OR4_PRELIM
+	hex "Preliminary value for OR4"
+	depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_BR5_PRELIM_BOOL
+	bool "Define Bank 5"
+
+config SYS_BR5_PRELIM
+	hex "Preliminary value for BR5"
+	depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_OR5_PRELIM
+	hex "Preliminary value for OR5"
+	depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_BR6_PRELIM_BOOL
+	bool "Define Bank 6"
+
+config SYS_BR6_PRELIM
+	hex "Preliminary value for BR6"
+	depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_OR6_PRELIM
+	hex "Preliminary value for OR6"
+	depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_BR7_PRELIM_BOOL
+	bool "Define Bank 7"
+
+config SYS_BR7_PRELIM
+	hex "Preliminary value for BR7"
+	depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_OR7_PRELIM
+	hex "Preliminary value for OR7"
+	depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_IMMR
+	hex "Value for IMMR"
+
+source "board/cssi/MCR3000/Kconfig"
+
+endmenu

arch/powerpc/cpu/mpc8xx/Makefile

@@ -0,0 +1,16 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y += start.o
+extra-y += traps.o
+obj-y	+= cpu.o
+obj-y	+= cpu_init.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_CMD_IMMAP) += immap.o
+obj-y	+= interrupts.o
+obj-$(CONFIG_CMD_REGINFO) += reginfo.o
+obj-y	+= speed.o

arch/powerpc/cpu/mpc8xx/config.mk

@@ -1,9 +1,8 @@
 #
-# (C) Copyright 2001-2006
+# (C) Copyright 2000-2010
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
-# Copyright (C) 2005-2006 Atmel Corporation
-#
 # SPDX-License-Identifier:	GPL-2.0+
+#
 
-obj-y			+= atstk1000.o
+PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float

arch/powerpc/cpu/mpc8xx/cpu.c

@@ -0,0 +1,334 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * m8xx.c
+ *
+ * CPU specific code
+ *
+ * written or collected and sometimes rewritten by
+ * Magnus Damm <damm@bitsmart.com>
+ *
+ * minor modifications by
+ * Wolfgang Denk <wd@denx.de>
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static char *cpu_warning = "\n         " \
+	"*** Warning: CPU Core has Silicon Bugs -- Check the Errata ***";
+
+static int check_CPU(long clock, uint pvr, uint immr)
+{
+	char *id_str =
+	NULL;
+	immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+	uint k, m;
+	char buf[32];
+	char pre = 'X';
+	char *mid = "xx";
+	char *suf;
+
+	/* the highest 16 bits should be 0x0050 for a 860 */
+
+	if ((pvr >> 16) != 0x0050)
+		return -1;
+
+	k = (immr << 16) |
+	    in_be16(&immap->im_cpm.cp_dparam16[PROFF_REVNUM / sizeof(u16)]);
+	m = 0;
+	suf = "";
+
+	/*
+	 * Some boards use sockets so different CPUs can be used.
+	 * We have to check chip version in run time.
+	 */
+	switch (k) {
+		/* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
+	case 0x08010004:		/* Rev. A.0 */
+		suf = "A";
+		/* fall through */
+	case 0x08000003:		/* Rev. 0.3 */
+		pre = 'M'; m = 1;
+		if (id_str == NULL)
+			id_str =
+		"PC866x"; /* Unknown chip from MPC866 family */
+		break;
+	case 0x09000000:
+		pre = 'M'; mid = suf = ""; m = 1;
+		if (id_str == NULL)
+			id_str = "PC885"; /* 870/875/880/885 */
+		break;
+
+	default:
+		suf = NULL;
+		break;
+	}
+
+	if (id_str == NULL)
+		id_str = "PC86x";	/* Unknown 86x chip */
+	if (suf)
+		printf("%c%s%sZPnn%s", pre, id_str, mid, suf);
+	else
+		printf("unknown M%s (0x%08x)", id_str, k);
+
+	printf(" at %s MHz: ", strmhz(buf, clock));
+
+	print_size(checkicache(), " I-Cache ");
+	print_size(checkdcache(), " D-Cache");
+
+	/* do we have a FEC (860T/P or 852/859/866/885)? */
+
+	out_be32(&immap->im_cpm.cp_fec.fec_addr_low, 0x12345678);
+	if (in_be32(&immap->im_cpm.cp_fec.fec_addr_low) == 0x12345678)
+		printf(" FEC present");
+
+	if (!m)
+		puts(cpu_warning);
+
+	putc('\n');
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int checkcpu(void)
+{
+	ulong clock = gd->cpu_clk;
+	uint immr = get_immr(0);	/* Return full IMMR contents */
+	uint pvr = get_pvr();
+
+	puts("CPU:   ");
+
+	return check_CPU(clock, pvr, immr);
+}
+
+/* ------------------------------------------------------------------------- */
+/* L1 i-cache                                                                */
+
+int checkicache(void)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+	u32 cacheon = rd_ic_cst() & IDC_ENABLED;
+	/* probe in flash memoryarea */
+	u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
+	u32 m;
+	u32 lines = -1;
+
+	wr_ic_cst(IDC_UNALL);
+	wr_ic_cst(IDC_INVALL);
+	wr_ic_cst(IDC_DISABLE);
+	__asm__ volatile ("isync");
+
+	while (!((m = rd_ic_cst()) & IDC_CERR2)) {
+		wr_ic_adr(k);
+		wr_ic_cst(IDC_LDLCK);
+		__asm__ volatile ("isync");
+
+		lines++;
+		k += 0x10;	/* the number of bytes in a cacheline */
+	}
+
+	wr_ic_cst(IDC_UNALL);
+	wr_ic_cst(IDC_INVALL);
+
+	if (cacheon)
+		wr_ic_cst(IDC_ENABLE);
+	else
+		wr_ic_cst(IDC_DISABLE);
+
+	__asm__ volatile ("isync");
+
+	return lines << 4;
+};
+
+/* ------------------------------------------------------------------------- */
+/* L1 d-cache                                                                */
+/* call with cache disabled                                                  */
+
+int checkdcache(void)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+	u32 cacheon = rd_dc_cst() & IDC_ENABLED;
+	/* probe in flash memoryarea */
+	u32 k = in_be32(&memctl->memc_br0) & ~0x00007fff;
+	u32 m;
+	u32 lines = -1;
+
+	wr_dc_cst(IDC_UNALL);
+	wr_dc_cst(IDC_INVALL);
+	wr_dc_cst(IDC_DISABLE);
+
+	while (!((m = rd_dc_cst()) & IDC_CERR2)) {
+		wr_dc_adr(k);
+		wr_dc_cst(IDC_LDLCK);
+		lines++;
+		k += 0x10;	/* the number of bytes in a cacheline */
+	}
+
+	wr_dc_cst(IDC_UNALL);
+	wr_dc_cst(IDC_INVALL);
+
+	if (cacheon)
+		wr_dc_cst(IDC_ENABLE);
+	else
+		wr_dc_cst(IDC_DISABLE);
+
+	return lines << 4;
+};
+
+/* ------------------------------------------------------------------------- */
+
+void upmconfig(uint upm, uint *table, uint size)
+{
+	uint i;
+	uint addr = 0;
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+
+	for (i = 0; i < size; i++) {
+		out_be32(&memctl->memc_mdr, table[i]);		/* (16-15) */
+		out_be32(&memctl->memc_mcr, addr | upm);	/* (16-16) */
+		addr++;
+	}
+}
+
+/* ------------------------------------------------------------------------- */
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong msr, addr;
+
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/* Checkstop Reset enable */
+	setbits_be32(&immap->im_clkrst.car_plprcr, PLPRCR_CSR);
+
+	/* Interrupts and MMU off */
+	__asm__ volatile ("mtspr    81, 0");
+	__asm__ volatile ("mfmsr    %0" : "=r" (msr));
+
+	msr &= ~0x1030;
+	__asm__ volatile ("mtmsr    %0" : : "r" (msr));
+
+	/*
+	 * Trying to execute the next instruction at a non-existing address
+	 * should cause a machine check, resulting in reset
+	 */
+#ifdef CONFIG_SYS_RESET_ADDRESS
+	addr = CONFIG_SYS_RESET_ADDRESS;
+#else
+	/*
+	 * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address,
+	 * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid address.
+	 * Better pick an address known to be invalid on your system and assign
+	 * it to CONFIG_SYS_RESET_ADDRESS.
+	 * "(ulong)-1" used to be a good choice for many systems...
+	 */
+	addr = CONFIG_SYS_MONITOR_BASE - sizeof(ulong);
+#endif
+	((void (*)(void)) addr)();
+	return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ *
+ * See sections 14.2 and 14.6 of the User's Manual
+ */
+unsigned long get_tbclk(void)
+{
+	uint immr = get_immr(0);	/* Return full IMMR contents */
+	immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+	ulong oscclk, factor, pll;
+
+	if (in_be32(&immap->im_clkrst.car_sccr) & SCCR_TBS)
+		return gd->cpu_clk / 16;
+
+	pll = in_be32(&immap->im_clkrst.car_plprcr);
+
+#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
+
+	/*
+	 * For newer PQ1 chips (MPC866/87x/88x families), PLL multiplication
+	 * factor is calculated as follows:
+	 *
+	 *		     MFN
+	 *	     MFI + -------
+	 *		   MFD + 1
+	 * factor =  -----------------
+	 *	     (PDF + 1) * 2^S
+	 *
+	 */
+	factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD) + 1)) /
+		 (PLPRCR_val(PDF) + 1) / (1 << PLPRCR_val(S));
+
+	oscclk = gd->cpu_clk / factor;
+
+	if ((in_be32(&immap->im_clkrst.car_sccr) & SCCR_RTSEL) == 0 ||
+	    factor > 2)
+		return oscclk / 4;
+
+	return oscclk / 16;
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset(void)
+{
+	int re_enable = disable_interrupts();
+
+	reset_8xx_watchdog((immap_t __iomem *)CONFIG_SYS_IMMR);
+	if (re_enable)
+		enable_interrupts();
+}
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_WATCHDOG)
+
+void reset_8xx_watchdog(immap_t __iomem *immr)
+{
+	/*
+	 * All other boards use the MPC8xx Internal Watchdog
+	 */
+	out_be16(&immr->im_siu_conf.sc_swsr, 0x556c);	/* write magic1 */
+	out_be16(&immr->im_siu_conf.sc_swsr, 0xaa39);	/* write magic2 */
+}
+#endif /* CONFIG_WATCHDOG */
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_MPC8XX_FEC)
+	fec_initialize(bis);
+#endif
+	return 0;
+}

arch/powerpc/cpu/mpc8xx/cpu_init.c

@@ -0,0 +1,188 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <watchdog.h>
+
+#include <mpc8xx.h>
+#include <commproc.h>
+#include <asm/io.h>
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(immap_t __iomem *immr)
+{
+	memctl8xx_t __iomem *memctl = &immr->im_memctl;
+	ulong reg;
+
+	/* SYPCR - contains watchdog control (11-9) */
+
+	out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR);
+
+#if defined(CONFIG_WATCHDOG)
+	reset_8xx_watchdog(immr);
+#endif /* CONFIG_WATCHDOG */
+
+	/* SIUMCR - contains debug pin configuration (11-6) */
+	setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
+	/* initialize timebase status and control register (11-26) */
+	/* unlock TBSCRK */
+
+	out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
+	out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR);
+
+	/* initialize the PIT (11-31) */
+
+	out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
+	out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
+
+	/* System integration timers. Don't change EBDF! (15-27) */
+
+	out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
+	clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
+			CONFIG_SYS_SCCR);
+
+	/*
+	 * MPC866/885 ERRATA GLL2
+	 * Description:
+	 *   In 1:2:1 mode, when HRESET is detected at the positive edge of
+	 *   EXTCLK, then there will be a loss of phase between
+	 *   EXTCLK and CLKOUT.
+	 *
+	 * Workaround:
+	 *   Reprogram the SCCR:
+	 *   1.   Write 1'b00 to SCCR[EBDF].
+	 *   2.   Write 1'b01 to SCCR[EBDF].
+	 *   3.   Rewrite the desired value to the PLPRCR register.
+	 */
+	reg = in_be32(&immr->im_clkrst.car_sccr);
+	/* Are we in mode 1:2:1 ? */
+	if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
+		clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
+		setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
+	}
+
+	/* PLL (CPU clock) settings (15-30) */
+
+	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
+
+	/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
+	 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
+	 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
+	 * field value.
+	 *
+	 * For newer (starting MPC866) chips PLPRCR layout is different.
+	 */
+#ifdef CONFIG_SYS_PLPRCR
+	if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
+		out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
+	else /* isolate MF-related fields and reset control bits */
+		clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
+				CONFIG_SYS_PLPRCR);
+#endif
+
+	/*
+	 * Memory Controller:
+	 */
+
+	/* Clear everything except Port Size bits & add the "Bank Valid" bit */
+	clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
+
+	/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
+	 * preliminary addresses - these have to be modified later
+	 * when FLASH size has been determined
+	 *
+	 * Depending on the size of the memory region defined by
+	 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
+	 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
+	 * map CONFIG_SYS_MONITOR_BASE.
+	 *
+	 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
+	 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
+	 *
+	 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
+	 * base address remains as 0x00000000. However, the address mask
+	 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
+	 * into the Bank0.
+	 *
+	 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
+	 * CONFIG_SYS_BR0_PRELIM in advance.
+	 *
+	 * [Thanks to Michael Liao for this explanation.
+	 *  I owe him a free beer. - wd]
+	 */
+
+#if defined(CONFIG_SYS_OR0_REMAP)
+	out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
+#endif
+#if defined(CONFIG_SYS_OR1_REMAP)
+	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
+#endif
+#if defined(CONFIG_SYS_OR5_REMAP)
+	out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
+#endif
+
+	/* now restrict to preliminary range */
+	out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
+	out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
+
+#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
+	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
+	out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
+	out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+	out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
+	out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
+	out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
+	out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
+	out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
+	out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
+	out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
+	out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
+#endif
+
+#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
+	out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
+	out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
+#endif
+
+	/*
+	 * Reset CPM
+	 */
+	out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
+	/* Spin until command processed */
+	while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
+		;
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return 0;
+}

arch/powerpc/cpu/mpc8xx/fdt.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2008 (C) Bryan O'Donoghue
+ *
+ * Code copied & edited from Freescale mpc85xx stuff.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+			     "timebase-frequency", get_tbclk(), 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+			     "bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+			     "clock-frequency", bd->bi_intfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency",
+			       bd->bi_intfreq, 1);
+	do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
+			       gd->arch.brg_clk, 1);
+
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}

arch/powerpc/cpu/mpc8xx/immap.c

@@ -0,0 +1,380 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * MPC8xx Internal Memory Map Functions
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/8xx_immap.h>
+#include <commproc.h>
+#include <asm/iopin_8xx.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_siuinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	sysconf8xx_t __iomem *sc = &immap->im_siu_conf;
+
+	printf("SIUMCR= %08x SYPCR = %08x\n",
+	       in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr));
+	printf("SWT   = %08x\n", in_be32(&sc->sc_swt));
+	printf("SIPEND= %08x SIMASK= %08x\n",
+	       in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask));
+	printf("SIEL  = %08x SIVEC = %08x\n",
+	       in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec));
+	printf("TESR  = %08x SDCR  = %08x\n",
+	       in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr));
+	return 0;
+}
+
+int do_memcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+	int nbanks = 8;
+	uint __iomem *p = &memctl->memc_br0;
+	int i;
+
+	for (i = 0; i < nbanks; i++, p += 2)
+		printf("BR%-2d  = %08x OR%-2d  = %08x\n",
+		       i, in_be32(p), i, in_be32(p + 1));
+
+	printf("MAR   = %08x", in_be32(&memctl->memc_mar));
+	printf(" MCR   = %08x\n", in_be32(&memctl->memc_mcr));
+	printf("MAMR  = %08x MBMR  = %08x",
+	       in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr));
+	printf("\nMSTAT =     %04x\n", in_be16(&memctl->memc_mstat));
+	printf("MPTPR =     %04x MDR   = %08x\n",
+	       in_be16(&memctl->memc_mptpr), in_be32(&memctl->memc_mdr));
+	return 0;
+}
+
+int do_carinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	car8xx_t __iomem *car = &immap->im_clkrst;
+
+	printf("SCCR  = %08x\n", in_be32(&car->car_sccr));
+	printf("PLPRCR= %08x\n", in_be32(&car->car_plprcr));
+	printf("RSR   = %08x\n", in_be32(&car->car_rsr));
+	return 0;
+}
+
+static int counter;
+
+static void header(void)
+{
+	char *data = "\
+       --------------------------------        --------------------------------\
+       00000000001111111111222222222233        00000000001111111111222222222233\
+       01234567890123456789012345678901        01234567890123456789012345678901\
+       --------------------------------        --------------------------------\
+    ";
+	int i;
+
+	if (counter % 2)
+		putc('\n');
+	counter = 0;
+
+	for (i = 0; i < 4; i++, data += 79)
+		printf("%.79s\n", data);
+}
+
+static void binary(char *label, uint value, int nbits)
+{
+	uint mask = 1 << (nbits - 1);
+	int i, second = (counter++ % 2);
+
+	if (second)
+		putc(' ');
+	puts(label);
+	for (i = 32 + 1; i != nbits; i--)
+		putc(' ');
+
+	while (mask != 0) {
+		if (value & mask)
+			putc('1');
+		else
+			putc('0');
+		mask >>= 1;
+	}
+
+	if (second)
+		putc('\n');
+}
+
+#define PA_NBITS	16
+#define PA_NB_ODR	 8
+#define PB_NBITS	18
+#define PB_NB_ODR	16
+#define PC_NBITS	12
+#define PD_NBITS	13
+
+int do_iopinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	iop8xx_t __iomem *iop = &immap->im_ioport;
+	ushort __iomem *l, *r;
+	uint __iomem *R;
+
+	counter = 0;
+	header();
+
+	/*
+	 * Ports A & B
+	 */
+
+	l = &iop->iop_padir;
+	R = &immap->im_cpm.cp_pbdir;
+	binary("PA_DIR", in_be16(l++), PA_NBITS);
+	binary("PB_DIR", in_be32(R++), PB_NBITS);
+	binary("PA_PAR", in_be16(l++), PA_NBITS);
+	binary("PB_PAR", in_be32(R++), PB_NBITS);
+	binary("PA_ODR", in_be16(l++), PA_NB_ODR);
+	binary("PB_ODR", in_be32(R++), PB_NB_ODR);
+	binary("PA_DAT", in_be16(l++), PA_NBITS);
+	binary("PB_DAT", in_be32(R++), PB_NBITS);
+
+	header();
+
+	/*
+	 * Ports C & D
+	 */
+
+	l = &iop->iop_pcdir;
+	r = &iop->iop_pddir;
+	binary("PC_DIR", in_be16(l++), PC_NBITS);
+	binary("PD_DIR", in_be16(r++), PD_NBITS);
+	binary("PC_PAR", in_be16(l++), PC_NBITS);
+	binary("PD_PAR", in_be16(r++), PD_NBITS);
+	binary("PC_SO ", in_be16(l++), PC_NBITS);
+	binary("      ", 0, 0);
+	r++;
+	binary("PC_DAT", in_be16(l++), PC_NBITS);
+	binary("PD_DAT", in_be16(r++), PD_NBITS);
+	binary("PC_INT", in_be16(l++), PC_NBITS);
+
+	header();
+	return 0;
+}
+
+/*
+ * set the io pins
+ * this needs a clean up for smaller tighter code
+ * use *uint and set the address based on cmd + port
+ */
+int do_iopset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	uint rcode = 0;
+	iopin_t iopin;
+	static uint port;
+	static uint pin;
+	static uint value;
+	static enum {
+		DIR,
+		PAR,
+		SOR,
+		ODR,
+		DAT,
+		INT
+	} cmd = DAT;
+
+	if (argc != 5) {
+		puts("iopset PORT PIN CMD VALUE\n");
+		return 1;
+	}
+	port = argv[1][0] - 'A';
+	if (port > 3)
+		port -= 0x20;
+	if (port > 3)
+		rcode = 1;
+	pin = simple_strtol(argv[2], NULL, 10);
+	if (pin > 31)
+		rcode = 1;
+
+
+	switch (argv[3][0]) {
+	case 'd':
+		if (argv[3][1] == 'a')
+			cmd = DAT;
+		else if (argv[3][1] == 'i')
+			cmd = DIR;
+		else
+			rcode = 1;
+		break;
+	case 'p':
+		cmd = PAR;
+		break;
+	case 'o':
+		cmd = ODR;
+		break;
+	case 's':
+		cmd = SOR;
+		break;
+	case 'i':
+		cmd = INT;
+		break;
+	default:
+		printf("iopset: unknown command %s\n", argv[3]);
+		rcode = 1;
+	}
+	if (argv[4][0] == '1')
+		value = 1;
+	else if (argv[4][0] == '0')
+		value = 0;
+	else
+		rcode = 1;
+	if (rcode == 0) {
+		iopin.port = port;
+		iopin.pin = pin;
+		iopin.flag = 0;
+		switch (cmd) {
+		case DIR:
+			if (value)
+				iopin_set_out(&iopin);
+			else
+				iopin_set_in(&iopin);
+			break;
+		case PAR:
+			if (value)
+				iopin_set_ded(&iopin);
+			else
+				iopin_set_gen(&iopin);
+			break;
+		case SOR:
+			if (value)
+				iopin_set_opt2(&iopin);
+			else
+				iopin_set_opt1(&iopin);
+			break;
+		case ODR:
+			if (value)
+				iopin_set_odr(&iopin);
+			else
+				iopin_set_act(&iopin);
+			break;
+		case DAT:
+			if (value)
+				iopin_set_high(&iopin);
+			else
+				iopin_set_low(&iopin);
+			break;
+		case INT:
+			if (value)
+				iopin_set_falledge(&iopin);
+			else
+				iopin_set_anyedge(&iopin);
+			break;
+		}
+	}
+	return rcode;
+}
+
+static void prbrg(int n, uint val)
+{
+	uint extc = (val >> 14) & 3;
+	uint cd = (val & CPM_BRG_CD_MASK) >> 1;
+	uint div16 = (val & CPM_BRG_DIV16) != 0;
+
+	ulong clock = gd->cpu_clk;
+
+	printf("BRG%d:", n);
+
+	if (val & CPM_BRG_RST)
+		puts(" RESET");
+	else
+		puts("      ");
+
+	if (val & CPM_BRG_EN)
+		puts("  ENABLED");
+	else
+		puts(" DISABLED");
+
+	printf(" EXTC=%d", extc);
+
+	if (val & CPM_BRG_ATB)
+		puts(" ATB");
+	else
+		puts("    ");
+
+	printf(" DIVIDER=%4d", cd);
+	if (extc == 0 && cd != 0) {
+		uint baudrate;
+
+		if (div16)
+			baudrate = (clock / 16) / (cd + 1);
+		else
+			baudrate = clock / (cd + 1);
+
+		printf("=%6d bps", baudrate);
+	} else {
+		puts("           ");
+	}
+
+	if (val & CPM_BRG_DIV16)
+		puts(" DIV16");
+	else
+		puts("      ");
+
+	putc('\n');
+}
+
+int do_brginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	cpm8xx_t __iomem *cp = &immap->im_cpm;
+	uint __iomem *p = &cp->cp_brgc1;
+	int i = 1;
+
+	while (i <= 4)
+		prbrg(i++, in_be32(p++));
+
+	return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+	siuinfo,	1,	1,	do_siuinfo,
+	"print System Interface Unit (SIU) registers",
+	""
+);
+
+U_BOOT_CMD(
+	memcinfo,	1,	1,	do_memcinfo,
+	"print Memory Controller registers",
+	""
+);
+
+U_BOOT_CMD(
+	carinfo,	1,	1,	do_carinfo,
+	"print Clocks and Reset registers",
+	""
+);
+
+U_BOOT_CMD(
+	iopinfo,	1,	1,	do_iopinfo,
+	"print I/O Port registers",
+	""
+);
+
+U_BOOT_CMD(
+	iopset,	5,	0,	do_iopset,
+	"set I/O Port registers",
+	"PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1"
+);
+
+U_BOOT_CMD(
+	brginfo,	1,	1,	do_brginfo,
+	"print Baud Rate Generator (BRG) registers",
+	""
+);

arch/powerpc/cpu/mpc8xx/interrupts.c

@@ -0,0 +1,252 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <mpc8xx_irq.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <commproc.h>
+
+/************************************************************************/
+
+/*
+ * CPM interrupt vector functions.
+ */
+struct interrupt_action {
+	interrupt_handler_t *handler;
+	void *arg;
+};
+
+static struct interrupt_action cpm_vecs[CPMVEC_NR];
+static struct interrupt_action irq_vecs[NR_IRQS];
+
+static void cpm_interrupt_init(void);
+static void cpm_interrupt(void *regs);
+
+/************************************************************************/
+
+int interrupt_init_cpu(unsigned *decrementer_count)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
+
+	/* disable all interrupts */
+	out_be32(&immr->im_siu_conf.sc_simask, 0);
+
+	/* Configure CPM interrupts */
+	cpm_interrupt_init();
+
+	return 0;
+}
+
+/************************************************************************/
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	int irq;
+	ulong simask;
+	ulong vec, v_bit;
+
+	/*
+	 * read the SIVEC register and shift the bits down
+	 * to get the irq number
+	 */
+	vec = in_be32(&immr->im_siu_conf.sc_sivec);
+	irq = vec >> 26;
+	v_bit = 0x80000000UL >> irq;
+
+	/*
+	 * Read Interrupt Mask Register and Mask Interrupts
+	 */
+	simask = in_be32(&immr->im_siu_conf.sc_simask);
+	clrbits_be32(&immr->im_siu_conf.sc_simask, 0xFFFF0000 >> irq);
+
+	if (!(irq & 0x1)) {		/* External Interrupt ?     */
+		ulong siel;
+
+		/*
+		 * Read Interrupt Edge/Level Register
+		 */
+		siel = in_be32(&immr->im_siu_conf.sc_siel);
+
+		if (siel & v_bit) {	/* edge triggered interrupt ?   */
+			/*
+			 * Rewrite SIPEND Register to clear interrupt
+			 */
+			out_be32(&immr->im_siu_conf.sc_sipend, v_bit);
+		}
+	}
+
+	if (irq_vecs[irq].handler != NULL) {
+		irq_vecs[irq].handler(irq_vecs[irq].arg);
+	} else {
+		printf("\nBogus External Interrupt IRQ %d Vector %ld\n",
+		       irq, vec);
+		/* turn off the bogus interrupt to avoid it from now */
+		simask &= ~v_bit;
+	}
+	/*
+	 * Re-Enable old Interrupt Mask
+	 */
+	out_be32(&immr->im_siu_conf.sc_simask, simask);
+}
+
+/************************************************************************/
+
+/*
+ * CPM interrupt handler
+ */
+static void cpm_interrupt(void *regs)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	uint vec;
+
+	/*
+	 * Get the vector by setting the ACK bit
+	 * and then reading the register.
+	 */
+	out_be16(&immr->im_cpic.cpic_civr, 1);
+	vec = in_be16(&immr->im_cpic.cpic_civr);
+	vec >>= 11;
+
+	if (cpm_vecs[vec].handler != NULL) {
+		(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
+	} else {
+		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
+		printf("Masking bogus CPM interrupt vector 0x%x\n", vec);
+	}
+	/*
+	 * After servicing the interrupt,
+	 * we have to remove the status indicator.
+	 */
+	setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec);
+}
+
+/*
+ * The CPM can generate the error interrupt when there is a race
+ * condition between generating and masking interrupts. All we have
+ * to do is ACK it and return. This is a no-op function so we don't
+ * need any special tests in the interrupt handler.
+ */
+static void cpm_error_interrupt(void *dummy)
+{
+}
+
+/************************************************************************/
+/*
+ * Install and free an interrupt handler
+ */
+void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if ((vec & CPMVEC_OFFSET) != 0) {
+		/* CPM interrupt */
+		vec &= 0xffff;
+		if (cpm_vecs[vec].handler != NULL)
+			printf("CPM interrupt 0x%x replacing 0x%x\n",
+			       (uint)handler, (uint)cpm_vecs[vec].handler);
+		cpm_vecs[vec].handler = handler;
+		cpm_vecs[vec].arg = arg;
+		setbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
+	} else {
+		/* SIU interrupt */
+		if (irq_vecs[vec].handler != NULL)
+			printf("SIU interrupt %d 0x%x replacing 0x%x\n",
+			       vec, (uint)handler, (uint)cpm_vecs[vec].handler);
+		irq_vecs[vec].handler = handler;
+		irq_vecs[vec].arg = arg;
+		setbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
+	}
+}
+
+void irq_free_handler(int vec)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if ((vec & CPMVEC_OFFSET) != 0) {
+		/* CPM interrupt */
+		vec &= 0xffff;
+		clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec);
+		cpm_vecs[vec].handler = NULL;
+		cpm_vecs[vec].arg = NULL;
+	} else {
+		/* SIU interrupt */
+		clrbits_be32(&immr->im_siu_conf.sc_simask, 1 << (31 - vec));
+		irq_vecs[vec].handler = NULL;
+		irq_vecs[vec].arg = NULL;
+	}
+}
+
+/************************************************************************/
+
+static void cpm_interrupt_init(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	uint cicr;
+
+	/*
+	 * Initialize the CPM interrupt controller.
+	 */
+
+	cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
+	       ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
+
+	out_be32(&immr->im_cpic.cpic_cicr, cicr);
+	out_be32(&immr->im_cpic.cpic_cimr, 0);
+
+	/*
+	 * Install the error handler.
+	 */
+	irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
+
+	setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
+
+	/*
+	 * Install the cpm interrupt handler
+	 */
+	irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
+}
+
+/************************************************************************/
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void timer_interrupt_cpu(struct pt_regs *regs)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/* Reset Timer Expired and Timers Interrupt Status */
+	out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
+	__asm__ ("nop");
+	/*
+	  Clear TEXPS (and TMIST on older chips). SPLSS (on older
+	  chips) is cleared too.
+
+	  Bitwise OR is a read-modify-write operation so ALL bits
+	  which are cleared by writing `1' would be cleared by
+	  operations like
+
+	  immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
+
+	  The same can be achieved by simple writing of the PLPRCR
+	  to itself. If a bit value should be preserved, read the
+	  register, ZERO the bit and write, not OR, the result back.
+	*/
+	setbits_be32(&immr->im_clkrst.car_plprcr, 0);
+}
+
+/************************************************************************/

arch/powerpc/cpu/mpc8xx/reginfo.c

@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2000
+ * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/io.h>
+
+void mpc8xx_reginfo(void)
+{
+	immap_t __iomem     *immap  = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+	sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf;
+	sit8xx_t __iomem *timers = &immap->im_sit;
+
+	/* Hopefully more PowerPC  knowledgable people will add code to display
+	 * other useful registers
+	 */
+
+	printf("\nSystem Configuration registers\n"
+		"\tIMMR\t0x%08X\n", get_immr(0));
+
+	printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr));
+	printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr));
+
+	printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt));
+	printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr));
+
+	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
+	       in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask));
+	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
+	       in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec));
+	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
+	       in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr));
+
+	printf("Memory Controller Registers\n");
+	printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0),
+	       in_be32(&memctl->memc_or0));
+	printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1),
+	       in_be32(&memctl->memc_or1));
+	printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2),
+	       in_be32(&memctl->memc_or2));
+	printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3),
+	       in_be32(&memctl->memc_or3));
+	printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4),
+	       in_be32(&memctl->memc_or4));
+	printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5),
+	       in_be32(&memctl->memc_or5));
+	printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6),
+	       in_be32(&memctl->memc_or6));
+	printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7),
+	       in_be32(&memctl->memc_or7));
+	printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr),
+	       in_be32(&memctl->memc_mbmr));
+	printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat),
+	       in_be16(&memctl->memc_mptpr));
+	printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr));
+
+	printf("\nSystem Integration Timers\n");
+	printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n",
+	       in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc));
+	printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr));
+
+	/*
+	 * May be some CPM info here?
+	 */
+}

arch/powerpc/cpu/mpc8xx/speed.c

@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void get_brgclk(uint sccr)
+{
+	uint divider = 0;
+
+	switch ((sccr & SCCR_DFBRG11) >> 11) {
+	case 0:
+		divider = 1;
+		break;
+	case 1:
+		divider = 4;
+		break;
+	case 2:
+		divider = 16;
+		break;
+	case 3:
+		divider = 64;
+		break;
+	}
+	gd->arch.brg_clk = gd->cpu_clk / divider;
+}
+
+/*
+ * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
+ */
+int get_clocks(void)
+{
+	uint immr = get_immr(0);	/* Return full IMMR contents */
+	immap_t __iomem *immap = (immap_t __iomem *)(immr & 0xFFFF0000);
+	uint sccr = in_be32(&immap->im_clkrst.car_sccr);
+	/*
+	 * If for some reason measuring the gclk frequency won't
+	 * work, we return the hardwired value.
+	 * (For example, the cogent CMA286-60 CPU module has no
+	 * separate oscillator for PITRTCLK)
+	 */
+	gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
+
+	if ((sccr & SCCR_EBDF11) == 0) {
+		/* No Bus Divider active */
+		gd->bus_clk = gd->cpu_clk;
+	} else {
+		/* The MPC8xx has only one BDF: half clock speed */
+		gd->bus_clk = gd->cpu_clk / 2;
+	}
+
+	get_brgclk(sccr);
+
+	return 0;
+}

arch/powerpc/cpu/mpc8xx/start.S

@@ -0,0 +1,636 @@
+/*
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*  U-Boot - Startup Code for PowerPC based Embedded Boards
+ *
+ *
+ *  The processor starts at 0x00000100 and the code is executed
+ *  from flash. The code is organized to be at an other address
+ *  in memory, but as long we don't jump around before relocating,
+ *  board_init lies at a quite high address and when the cpu has
+ *  jumped there, everything is ok.
+ *  This works because the cpu gives the FLASH (CS0) the whole
+ *  address space at startup, and board_init lies as a echo of
+ *  the flash somewhere up there in the memory map.
+ *
+ *  board_init will change CS0 to be positioned at the correct
+ *  address and (s)dram will be positioned at address 0
+ */
+#include <asm-offsets.h>
+#include <config.h>
+#include <mpc8xx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+/* We don't want the  MMU yet.
+*/
+#undef	MSR_KERNEL
+#define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r12 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(_FIXUP_TABLE_)
+
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+
+	GOT_ENTRY(__init_end)
+	GOT_ENTRY(__bss_end)
+	GOT_ENTRY(__bss_start)
+	END_GOT
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+	.text
+	.long	0x27051956		/* U-Boot Magic Number			*/
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION_STRING, "\0"
+
+	. = EXC_OFF_SYS_RESET
+	.globl	_start
+_start:
+	lis	r3, CONFIG_SYS_IMMR@h		/* position IMMR */
+	mtspr	638, r3
+
+	/* Initialize machine status; enable machine check interrupt		*/
+	/*----------------------------------------------------------------------*/
+	li	r3, MSR_KERNEL		/* Set ME, RI flags */
+	mtmsr	r3
+	mtspr	SRR1, r3		/* Make SRR1 match MSR */
+
+	mfspr	r3, ICR			/* clear Interrupt Cause Register */
+
+	/* Initialize debug port registers					*/
+	/*----------------------------------------------------------------------*/
+	xor	r0, r0, r0		/* Clear R0 */
+	mtspr	LCTRL1, r0		/* Initialize debug port regs */
+	mtspr	LCTRL2, r0
+	mtspr	COUNTA, r0
+	mtspr	COUNTB, r0
+
+	/* Reset the caches							*/
+	/*----------------------------------------------------------------------*/
+
+	mfspr	r3, IC_CST		/* Clear error bits */
+	mfspr	r3, DC_CST
+
+	lis	r3, IDC_UNALL@h		/* Unlock all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_INVALL@h	/* Invalidate all */
+	mtspr	IC_CST, r3
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_DISABLE@h	/* Disable data cache */
+	mtspr	DC_CST, r3
+
+	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
+	mtspr	IC_CST, r3
+
+	/* invalidate all tlb's							*/
+	/*----------------------------------------------------------------------*/
+
+	tlbia
+	isync
+
+	/*
+	 * Calculate absolute address in FLASH and jump there
+	 *----------------------------------------------------------------------*/
+
+	lis	r3, CONFIG_SYS_MONITOR_BASE@h
+	ori	r3, r3, CONFIG_SYS_MONITOR_BASE@l
+	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr	r3
+	blr
+
+in_flash:
+
+	/* initialize some SPRs that are hard to access from C			*/
+	/*----------------------------------------------------------------------*/
+
+	lis	r3, CONFIG_SYS_IMMR@h		/* pass IMMR as arg1 to C routine */
+	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
+	/* Note: R0 is still 0 here */
+	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
+	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
+
+	/*
+	 * Disable serialized ifetch and show cycles
+	 * (i.e. set processor to normal mode).
+	 * This is also a silicon bug workaround, see errata
+	 */
+
+	li	r2, 0x0007
+	mtspr	ICTRL, r2
+
+	/* Set up debug mode entry */
+
+	lis	r2, CONFIG_SYS_DER@h
+	ori	r2, r2, CONFIG_SYS_DER@l
+	mtspr	DER, r2
+
+	/* let the C-code set up the rest					*/
+	/*									*/
+	/* Be careful to keep code relocatable !				*/
+	/*----------------------------------------------------------------------*/
+
+	GET_GOT			/* initialize GOT access			*/
+
+	/* r3: IMMR */
+	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
+
+	bl	board_init_f	/* run 1st part of board init code (from Flash) */
+
+	/* NOTREACHED - board_init_f() does not return */
+
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception.  "Never" generated on the 860. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception.  "Never" generated on the 860. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+		MSR_KERNEL, COPY_EE)
+
+	/* No FPU on MPC8xx.  This exception is not supposed to happen.
+	*/
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+	/* I guess we could implement decrementer, and may have
+	 * to someday for timekeeping.
+	 */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
+	 * for all unimplemented and illegal instructions.
+	 */
+	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
+
+	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+
+	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+
+	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
+	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+
+	. = 0x2000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	mtspr	SPRG2,r22		/* r1 is now kernel sp */
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28			/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)		/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+
+/* Cache functions.
+*/
+	.globl	icache_enable
+icache_enable:
+	SYNC
+	lis	r3, IDC_INVALL@h
+	mtspr	IC_CST, r3
+	lis	r3, IDC_ENABLE@h
+	mtspr	IC_CST, r3
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	SYNC
+	lis	r3, IDC_DISABLE@h
+	mtspr	IC_CST, r3
+	blr
+
+	.globl	icache_status
+icache_status:
+	mfspr	r3, IC_CST
+	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	blr
+
+	.globl	dcache_enable
+dcache_enable:
+	lis	r3, 0x0400		/* Set cache mode with MMU off */
+	mtspr	MD_CTR, r3
+
+	lis	r3, IDC_INVALL@h
+	mtspr	DC_CST, r3
+	lis	r3, IDC_ENABLE@h
+	mtspr	DC_CST, r3
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	SYNC
+	lis	r3, IDC_DISABLE@h
+	mtspr	DC_CST, r3
+	lis	r3, IDC_INVALL@h
+	mtspr	DC_CST, r3
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfspr	r3, DC_CST
+	srwi	r3, r3, 31	/* >>31 => select bit 0 */
+	blr
+
+	.globl	dc_read
+dc_read:
+	mtspr	DC_ADR, r3
+	mfspr	r3, DC_DAT
+	blr
+
+/*
+ * unsigned int get_immr (unsigned int mask)
+ *
+ * return (mask ? (IMMR & mask) : IMMR);
+ */
+	.globl	get_immr
+get_immr:
+	mr	r4,r3		/* save mask */
+	mfspr	r3, IMMR	/* IMMR */
+	cmpwi	0,r4,0		/* mask != 0 ? */
+	beq	4f
+	and	r3,r3,r4	/* IMMR & mask */
+4:
+	blr
+
+	.globl get_pvr
+get_pvr:
+	mfspr	r3, PVR
+	blr
+
+
+	.globl wr_ic_cst
+wr_ic_cst:
+	mtspr	IC_CST, r3
+	blr
+
+	.globl rd_ic_cst
+rd_ic_cst:
+	mfspr	r3, IC_CST
+	blr
+
+	.globl wr_ic_adr
+wr_ic_adr:
+	mtspr	IC_ADR, r3
+	blr
+
+
+	.globl wr_dc_cst
+wr_dc_cst:
+	mtspr	DC_CST, r3
+	blr
+
+	.globl rd_dc_cst
+rd_dc_cst:
+	mfspr	r3, DC_CST
+	blr
+
+	.globl wr_dc_adr
+wr_dc_adr:
+	mtspr	DC_ADR, r3
+	blr
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	mr	r1,  r3		/* Set new stack pointer		*/
+	mr	r9,  r4		/* Save copy of Global Data pointer	*/
+	mr	r10, r5		/* Save copy of Destination Address	*/
+
+	GET_GOT
+	mr	r3,  r5				/* Destination Address	*/
+	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
+	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r12, r12, r15
+	/* then the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary	*/
+	beq	7f		/* Protect against 0 count		*/
+	mtctr	r0
+	bge	cr1,2f
+
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+	b	4f
+
+2:	slwi	r0,r0,2
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+
+	/*
+	 * Relocation Function, r12 point to got2+0x8000
+	 *
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	cmpwi	r0,0
+	beq-	2f
+	add	r0,r0,r11
+	stw	r0,0(r3)
+2:	bdnz	1b
+
+	/*
+	 * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	cmpwi	r0,0
+	add	r0,r0,r11
+	stw	r4,0(r3)
+	beq-	5f
+	stw	r0,0(r4)
+5:	bdnz	3b
+4:
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(__bss_start)
+	lwz	r4,GOT(__bss_end)
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+
+	mr	r3, r9		/* Global Data pointer		*/
+	mr	r4, r10		/* Destination Address		*/
+	bl	board_init_r
+
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	li	r9, 0x100		/* reset vector always at 0x100 */
+
+	cmplw	0, r7, r8
+	bgelr				/* return if r7>=r8 - just in case */
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	4b
+
+	mtlr	r4			/* restore link register	*/
+	blr

arch/powerpc/cpu/mpc8xx/traps.c

@@ -0,0 +1,165 @@
+/*
+ * linux/arch/powerpc/kernel/traps.c
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+/* THIS NEEDS CHANGING to use the board info structure.
+*/
+#define END_OF_MEM	0x02000000
+
+/*
+ * Trap & Exception support
+ */
+
+static void print_backtrace(unsigned long *sp)
+{
+	int cnt = 0;
+	unsigned long i;
+
+	printf("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
+
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			printf("\n");
+		printf("%08lX ", i);
+		if (cnt > 32)
+			break;
+		sp = (unsigned long *)*sp;
+	}
+	printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	       regs->msr, regs->msr & MSR_EE ? 1 : 0,
+	       regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0,
+	       regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0,
+	       regs->msr & MSR_DR ? 1 : 0);
+
+	printf("\n");
+	for (i = 0;  i < 32;  i++) {
+		if ((i % 8) == 0)
+			printf("GPR%02d: ", i);
+
+		printf("%08lX ", regs->gpr[i]);
+		if ((i % 8) == 7)
+			printf("\n");
+	}
+}
+
+
+static void _exception(int signr, struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
+}
+
+void MachineCheckException(struct pt_regs *regs)
+{
+	unsigned long fixup = search_exception_table(regs->nip);
+
+	/* Probing PCI using config cycles cause this exception
+	 * when a device is not present.  Catch it and return to
+	 * the PCI exception handler.
+	 */
+	if (fixup != 0) {
+		regs->nip = fixup;
+		return;
+	}
+
+	printf("Machine check in kernel mode.\n");
+	printf("Caused by (from msr): ");
+	printf("regs %p ", regs);
+	switch (regs->msr & 0x000F0000) {
+	case (0x80000000 >> 12):
+		printf("Machine check signal - probably due to mm fault\n"
+			"with mmu off\n");
+		break;
+	case (0x80000000 >> 13):
+		printf("Transfer error ack signal\n");
+		break;
+	case (0x80000000 >> 14):
+		printf("Data parity signal\n");
+		break;
+	case (0x80000000 >> 15):
+		printf("Address parity signal\n");
+		break;
+	default:
+		printf("Unknown values in msr\n");
+	}
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("machine check");
+}
+
+void AlignmentException(struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
+}
+
+void ProgramCheckException(struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
+}
+
+void SoftEmuException(struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
+}
+
+
+void UnknownException(struct pt_regs *regs)
+{
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	       regs->nip, regs->msr, regs->trap);
+	_exception(0, regs);
+}
+
+void DebugException(struct pt_regs *regs)
+{
+	printf("Debugger trap at @ %lx\n", regs->nip);
+	show_regs(regs);
+}
+
+/* Probe an address by reading.  If not present, return -1, otherwise
+ * return 0.
+ */
+int addr_probe(uint *addr)
+{
+	return 0;
+}

arch/powerpc/include/asm/8xx_immap.h

@@ -0,0 +1,468 @@
+/*
+ * MPC8xx Internal Memory Map
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * The I/O on the MPC860 is comprised of blocks of special registers
+ * and the dual port ram for the Communication Processor Module.
+ * Within this space are functional units such as the SIU, memory
+ * controller, system timers, and other control functions.  It is
+ * a combination that I found difficult to separate into logical
+ * functional files.....but anyone else is welcome to try.  -- Dan
+ */
+#ifndef __IMMAP_8XX__
+#define __IMMAP_8XX__
+
+/* System configuration registers.
+*/
+typedef	struct sys_conf {
+	uint	sc_siumcr;
+	uint	sc_sypcr;
+	uint	sc_swt;
+	char	res1[2];
+	ushort	sc_swsr;
+	uint	sc_sipend;
+	uint	sc_simask;
+	uint	sc_siel;
+	uint	sc_sivec;
+	uint	sc_tesr;
+	char	res2[0xc];
+	uint	sc_sdcr;
+	char	res3[0x4c];
+} sysconf8xx_t;
+
+/* PCMCIA configuration registers.
+*/
+typedef struct pcmcia_conf {
+	uint	pcmc_pbr0;
+	uint	pcmc_por0;
+	uint	pcmc_pbr1;
+	uint	pcmc_por1;
+	uint	pcmc_pbr2;
+	uint	pcmc_por2;
+	uint	pcmc_pbr3;
+	uint	pcmc_por3;
+	uint	pcmc_pbr4;
+	uint	pcmc_por4;
+	uint	pcmc_pbr5;
+	uint	pcmc_por5;
+	uint	pcmc_pbr6;
+	uint	pcmc_por6;
+	uint	pcmc_pbr7;
+	uint	pcmc_por7;
+	char	res1[0x20];
+	uint	pcmc_pgcra;
+	uint	pcmc_pgcrb;
+	uint	pcmc_pscr;
+	char	res2[4];
+	uint	pcmc_pipr;
+	char	res3[4];
+	uint	pcmc_per;
+	char	res4[4];
+} pcmconf8xx_t;
+
+/* Memory controller registers.
+*/
+typedef struct	mem_ctlr {
+	uint	memc_br0;
+	uint	memc_or0;
+	uint	memc_br1;
+	uint	memc_or1;
+	uint	memc_br2;
+	uint	memc_or2;
+	uint	memc_br3;
+	uint	memc_or3;
+	uint	memc_br4;
+	uint	memc_or4;
+	uint	memc_br5;
+	uint	memc_or5;
+	uint	memc_br6;
+	uint	memc_or6;
+	uint	memc_br7;
+	uint	memc_or7;
+	char	res1[0x24];
+	uint	memc_mar;
+	uint	memc_mcr;
+	char	res2[4];
+	uint	memc_mamr;
+	uint	memc_mbmr;
+	ushort	memc_mstat;
+	ushort	memc_mptpr;
+	uint	memc_mdr;
+	char	res3[0x80];
+} memctl8xx_t;
+
+/* System Integration Timers.
+*/
+typedef struct	sys_int_timers {
+	ushort	sit_tbscr;
+	char	res0[0x02];
+	uint	sit_tbreff0;
+	uint	sit_tbreff1;
+	char	res1[0x14];
+	ushort	sit_rtcsc;
+	char	res2[0x02];
+	uint	sit_rtc;
+	uint	sit_rtsec;
+	uint	sit_rtcal;
+	char	res3[0x10];
+	ushort	sit_piscr;
+	char	res4[2];
+	uint	sit_pitc;
+	uint	sit_pitr;
+	char	res5[0x34];
+} sit8xx_t;
+
+#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
+#define TBSCR_REFA		((ushort)0x0080)
+#define TBSCR_REFB		((ushort)0x0040)
+#define TBSCR_REFAE		((ushort)0x0008)
+#define TBSCR_REFBE		((ushort)0x0004)
+#define TBSCR_TBF		((ushort)0x0002)
+#define TBSCR_TBE		((ushort)0x0001)
+
+#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
+#define RTCSC_SEC		((ushort)0x0080)
+#define RTCSC_ALR		((ushort)0x0040)
+#define RTCSC_38K		((ushort)0x0010)
+#define RTCSC_SIE		((ushort)0x0008)
+#define RTCSC_ALE		((ushort)0x0004)
+#define RTCSC_RTF		((ushort)0x0002)
+#define RTCSC_RTE		((ushort)0x0001)
+
+#define PISCR_PIRQ_MASK		((ushort)0xff00)
+#define PISCR_PS		((ushort)0x0080)
+#define PISCR_PIE		((ushort)0x0004)
+#define PISCR_PTF		((ushort)0x0002)
+#define PISCR_PTE		((ushort)0x0001)
+
+/* Clocks and Reset.
+*/
+typedef struct clk_and_reset {
+	uint	car_sccr;
+	uint	car_plprcr;
+	uint	car_rsr;
+	char	res[0x74];        /* Reserved area                  */
+} car8xx_t;
+
+/* System Integration Timers keys.
+*/
+typedef struct sitk {
+	uint	sitk_tbscrk;
+	uint	sitk_tbreff0k;
+	uint	sitk_tbreff1k;
+	uint	sitk_tbk;
+	char	res1[0x10];
+	uint	sitk_rtcsck;
+	uint	sitk_rtck;
+	uint	sitk_rtseck;
+	uint	sitk_rtcalk;
+	char	res2[0x10];
+	uint	sitk_piscrk;
+	uint	sitk_pitck;
+	char	res3[0x38];
+} sitk8xx_t;
+
+/* Clocks and reset keys.
+*/
+typedef struct cark {
+	uint	cark_sccrk;
+	uint	cark_plprcrk;
+	uint	cark_rsrk;
+	char	res[0x474];
+} cark8xx_t;
+
+/* The key to unlock registers maintained by keep-alive power.
+*/
+#define KAPWR_KEY	((unsigned int)0x55ccaa33)
+
+/* I2C
+*/
+typedef struct i2c {
+	u_char	i2c_i2mod;
+	char	res1[3];
+	u_char	i2c_i2add;
+	char	res2[3];
+	u_char	i2c_i2brg;
+	char	res3[3];
+	u_char	i2c_i2com;
+	char	res4[3];
+	u_char	i2c_i2cer;
+	char	res5[3];
+	u_char	i2c_i2cmr;
+	char	res6[0x8b];
+} i2c8xx_t;
+
+/* DMA control/status registers.
+*/
+typedef struct sdma_csr {
+	char	res1[4];
+	uint	sdma_sdar;
+	u_char	sdma_sdsr;
+	char	res3[3];
+	u_char	sdma_sdmr;
+	char	res4[3];
+	u_char	sdma_idsr1;
+	char	res5[3];
+	u_char	sdma_idmr1;
+	char	res6[3];
+	u_char	sdma_idsr2;
+	char	res7[3];
+	u_char	sdma_idmr2;
+	char	res8[0x13];
+} sdma8xx_t;
+
+/* Communication Processor Module Interrupt Controller.
+*/
+typedef struct cpm_ic {
+	ushort	cpic_civr;
+	char	res[0xe];
+	uint	cpic_cicr;
+	uint	cpic_cipr;
+	uint	cpic_cimr;
+	uint	cpic_cisr;
+} cpic8xx_t;
+
+/* Input/Output Port control/status registers.
+*/
+typedef struct io_port {
+	ushort	iop_padir;
+	ushort	iop_papar;
+	ushort	iop_paodr;
+	ushort	iop_padat;
+	char	res1[8];
+	ushort	iop_pcdir;
+	ushort	iop_pcpar;
+	ushort	iop_pcso;
+	ushort	iop_pcdat;
+	ushort	iop_pcint;
+	char	res2[6];
+	ushort	iop_pddir;
+	ushort	iop_pdpar;
+	char	res3[2];
+	ushort	iop_pddat;
+	uint	utmode;
+	char	res4[4];
+} iop8xx_t;
+
+/* Communication Processor Module Timers
+*/
+typedef struct cpm_timers {
+	ushort	cpmt_tgcr;
+	char	res1[0xe];
+	ushort	cpmt_tmr1;
+	ushort	cpmt_tmr2;
+	ushort	cpmt_trr1;
+	ushort	cpmt_trr2;
+	ushort	cpmt_tcr1;
+	ushort	cpmt_tcr2;
+	ushort	cpmt_tcn1;
+	ushort	cpmt_tcn2;
+	ushort	cpmt_tmr3;
+	ushort	cpmt_tmr4;
+	ushort	cpmt_trr3;
+	ushort	cpmt_trr4;
+	ushort	cpmt_tcr3;
+	ushort	cpmt_tcr4;
+	ushort	cpmt_tcn3;
+	ushort	cpmt_tcn4;
+	ushort	cpmt_ter1;
+	ushort	cpmt_ter2;
+	ushort	cpmt_ter3;
+	ushort	cpmt_ter4;
+	char	res2[8];
+} cpmtimer8xx_t;
+
+/* Finally, the Communication Processor stuff.....
+*/
+typedef struct scc {		/* Serial communication channels */
+	uint	scc_gsmrl;
+	uint	scc_gsmrh;
+	ushort	scc_psmr;
+	char	res1[2];
+	ushort	scc_todr;
+	ushort	scc_dsr;
+	ushort	scc_scce;
+	char	res2[2];
+	ushort	scc_sccm;
+	char	res3;
+	u_char	scc_sccs;
+	char	res4[8];
+} scc_t;
+
+typedef struct smc {		/* Serial management channels */
+	char	res1[2];
+	ushort	smc_smcmr;
+	char	res2[2];
+	u_char	smc_smce;
+	char	res3[3];
+	u_char	smc_smcm;
+	char	res4[5];
+} smc_t;
+
+/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
+ * it fits within the address space.
+ */
+
+typedef struct fec {
+	uint	fec_addr_low;		/* lower 32 bits of station address	*/
+	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
+	ushort	res1;			/* reserved				*/
+	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
+	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
+	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
+	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
+	uint	fec_r_buff_size;	/* Rx buffer size			*/
+	uint	res2[9];		/* reserved				*/
+	uint	fec_ecntrl;		/* ethernet control register		*/
+	uint	fec_ievent;		/* interrupt event register		*/
+	uint	fec_imask;		/* interrupt mask register		*/
+	uint	fec_ivec;		/* interrupt level and vector status	*/
+	uint	fec_r_des_active;	/* Rx ring updated flag			*/
+	uint	fec_x_des_active;	/* Tx ring updated flag			*/
+	uint	res3[10];		/* reserved				*/
+	uint	fec_mii_data;		/* MII data register			*/
+	uint	fec_mii_speed;		/* MII speed control register		*/
+	uint	res4[17];		/* reserved				*/
+	uint	fec_r_bound;		/* end of RAM (read-only)		*/
+	uint	fec_r_fstart;		/* Rx FIFO start address		*/
+	uint	res5[6];		/* reserved				*/
+	uint	fec_x_fstart;		/* Tx FIFO start address		*/
+	uint	res6[17];		/* reserved				*/
+	uint	fec_fun_code;		/* fec SDMA function code		*/
+	uint	res7[3];		/* reserved				*/
+	uint	fec_r_cntrl;		/* Rx control register			*/
+	uint	fec_r_hash;		/* Rx hash register			*/
+	uint	res8[14];		/* reserved				*/
+	uint	fec_x_cntrl;		/* Tx control register			*/
+	uint	res9[0x1e];		/* reserved				*/
+} fec_t;
+
+typedef struct comm_proc {
+	/* General control and status registers.
+	*/
+	ushort	cp_cpcr;
+	u_char	res1[2];
+	ushort	cp_rccr;
+	u_char	res2;
+	u_char	cp_rmds;
+	u_char	res3[4];
+	ushort	cp_cpmcr1;
+	ushort	cp_cpmcr2;
+	ushort	cp_cpmcr3;
+	ushort	cp_cpmcr4;
+	u_char	res4[2];
+	ushort	cp_rter;
+	u_char	res5[2];
+	ushort	cp_rtmr;
+	u_char	res6[0x14];
+
+	/* Baud rate generators.
+	*/
+	uint	cp_brgc1;
+	uint	cp_brgc2;
+	uint	cp_brgc3;
+	uint	cp_brgc4;
+
+	/* Serial Communication Channels.
+	*/
+	scc_t	cp_scc[4];
+
+	/* Serial Management Channels.
+	*/
+	smc_t	cp_smc[2];
+
+	/* Serial Peripheral Interface.
+	*/
+	ushort	cp_spmode;
+	u_char	res7[4];
+	u_char	cp_spie;
+	u_char	res8[3];
+	u_char	cp_spim;
+	u_char	res9[2];
+	u_char	cp_spcom;
+	u_char	res10[2];
+
+	/* Parallel Interface Port.
+	*/
+	u_char	res11[2];
+	ushort	cp_pipc;
+	u_char	res12[2];
+	ushort	cp_ptpr;
+	uint	cp_pbdir;
+	uint	cp_pbpar;
+	u_char	res13[2];
+	ushort	cp_pbodr;
+	uint	cp_pbdat;
+
+	/* Port E - MPC87x/88x only.
+	 */
+	uint	cp_pedir;
+	uint	cp_pepar;
+	uint	cp_peso;
+	uint	cp_peodr;
+	uint	cp_pedat;
+
+	/* Communications Processor Timing Register -
+	   Contains RMII Timing for the FECs on MPC87x/88x only.
+	*/
+	uint	cp_cptr;
+
+	/* Serial Interface and Time Slot Assignment.
+	*/
+	uint	cp_simode;
+	u_char	cp_sigmr;
+	u_char	res15;
+	u_char	cp_sistr;
+	u_char	cp_sicmr;
+	u_char	res16[4];
+	uint	cp_sicr;
+	uint	cp_sirp;
+	u_char	res17[0xc];
+
+	u_char	res19[0x100];
+	u_char	cp_siram[0x200];
+
+	/* The fast ethernet controller is not really part of the CPM,
+	 * but it resides in the address space.
+	 */
+	fec_t	cp_fec;
+	char	res18[0xE00];
+
+	/* The MPC885 family has a second FEC here */
+	fec_t	cp_fec2;
+#define cp_fec1	cp_fec	/* consistency macro */
+
+	/* Dual Ported RAM follows.
+	 * There are many different formats for this memory area
+	 * depending upon the devices used and options chosen.
+	 * Some processors don't have all of it populated.
+	 */
+	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
+
+	/* Parameter RAM */
+	union {
+		u_char	cp_dparam[0x400];
+		u16	cp_dparam16[0x200];
+	};
+} cpm8xx_t;
+
+/* Internal memory map.
+*/
+typedef struct immap {
+	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
+	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
+	memctl8xx_t	im_memctl;	/* Memory Controller */
+	sit8xx_t	im_sit;		/* System integration timers */
+	car8xx_t	im_clkrst;	/* Clocks and reset */
+	sitk8xx_t	im_sitk;	/* Sys int timer keys */
+	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
+	char		res[96];
+	i2c8xx_t	im_i2c;		/* I2C control/status */
+	sdma8xx_t	im_sdma;	/* SDMA control/status */
+	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
+	iop8xx_t	im_ioport;	/* IO Port control/status */
+	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
+	cpm8xx_t	im_cpm;		/* Communication processor */
+} immap_t;
+
+#endif /* __IMMAP_8XX__ */

arch/powerpc/include/asm/cache.h

@@ -7,7 +7,9 @@
 #include <asm/processor.h>
 
 /* bytes per L1 cache line */
-#if defined(CONFIG_PPC64BRIDGE)
+#if defined(CONFIG_8xx)
+#define	L1_CACHE_SHIFT	4
+#elif defined(CONFIG_PPC64BRIDGE)
 #define L1_CACHE_SHIFT	7
 #elif defined(CONFIG_E500MC)
 #define L1_CACHE_SHIFT	6
@@ -70,4 +72,41 @@ void disable_cpc_sram(void);
 #define L2CACHE_NONE	0x03	/* NONE */
 #define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
 
+#ifdef CONFIG_8xx
+/* Cache control on the MPC8xx is provided through some additional
+ * special purpose registers.
+ */
+#define IC_CST		560	/* Instruction cache control/status */
+#define IC_ADR		561	/* Address needed for some commands */
+#define IC_DAT		562	/* Read-only data register */
+#define DC_CST		568	/* Data cache control/status */
+#define DC_ADR		569	/* Address needed for some commands */
+#define DC_DAT		570	/* Read-only data register */
+
+/* Commands.  Only the first few are available to the instruction cache.
+*/
+#define	IDC_ENABLE	0x02000000	/* Cache enable */
+#define IDC_DISABLE	0x04000000	/* Cache disable */
+#define IDC_LDLCK	0x06000000	/* Load and lock */
+#define IDC_UNLINE	0x08000000	/* Unlock line */
+#define IDC_UNALL	0x0a000000	/* Unlock all */
+#define IDC_INVALL	0x0c000000	/* Invalidate all */
+
+#define DC_FLINE	0x0e000000	/* Flush data cache line */
+#define DC_SFWT		0x01000000	/* Set forced writethrough mode */
+#define DC_CFWT		0x03000000	/* Clear forced writethrough mode */
+#define DC_SLES		0x05000000	/* Set little endian swap mode */
+#define DC_CLES		0x07000000	/* Clear little endian swap mode */
+
+/* Status.
+*/
+#define IDC_ENABLED	0x80000000	/* Cache is enabled */
+#define IDC_CERR1	0x00200000	/* Cache error 1 */
+#define IDC_CERR2	0x00100000	/* Cache error 2 */
+#define IDC_CERR3	0x00080000	/* Cache error 3 */
+
+#define DC_DFWT		0x40000000	/* Data cache is forced write through */
+#define DC_LES		0x20000000	/* Caches are little endian mode */
+#endif /* CONFIG_8xx */
+
 #endif

arch/powerpc/include/asm/global_data.h

@@ -19,6 +19,9 @@ struct arch_global_data {
 	u8 sdhc_adapter;
 #endif
 #endif
+#if defined(CONFIG_8xx)
+	unsigned long brg_clk;
+#endif
 #if defined(CONFIG_CPM2)
 	/* There are many clocks on the MPC8260 - see page 9-5 */
 	unsigned long vco_out;

arch/powerpc/include/asm/iopin_8xx.h

@@ -0,0 +1,468 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * MPC8xx I/O port pin manipulation functions
+ * Roughly based on iopin_8260.h
+ */
+
+#ifndef _ASM_IOPIN_8XX_H_
+#define _ASM_IOPIN_8XX_H_
+
+#include <linux/types.h>
+#include <asm/8xx_immap.h>
+#include <asm/io.h>
+
+#ifdef __KERNEL__
+
+typedef struct {
+	u_char port:2;	/* port number (A=0, B=1, C=2, D=3) */
+	u_char pin:5;	/* port pin (0-31) */
+	u_char flag:1;	/* for whatever */
+} iopin_t;
+
+#define IOPIN_PORTA	0
+#define IOPIN_PORTB	1
+#define IOPIN_PORTC	2
+#define IOPIN_PORTD	3
+
+static inline void iopin_set_high(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		setbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		setbits_be32(datp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		setbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		setbits_be16(datp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_low(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		clrbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		clrbits_be32(datp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		clrbits_be16(datp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		clrbits_be16(datp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_high(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		return (in_be32(datp) >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		return (in_be16(datp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_low(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *datp = &immap->im_ioport.iop_padat;
+
+		return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *datp = &immap->im_cpm.cp_pbdat;
+
+		return ((in_be32(datp) >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pcdat;
+
+		return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *datp = &immap->im_ioport.iop_pddat;
+
+		return ((in_be16(datp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_out(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		setbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		setbits_be32(dirp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		setbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		setbits_be16(dirp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_in(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		clrbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		clrbits_be32(dirp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		clrbits_be16(dirp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		clrbits_be16(dirp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_out(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		return (in_be32(dirp) >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		return (in_be16(dirp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_in(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_padir;
+
+		return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *dirp = &immap->im_cpm.cp_pbdir;
+
+		return ((in_be32(dirp) >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pcdir;
+
+		return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *dirp = &immap->im_ioport.iop_pddir;
+
+		return ((in_be16(dirp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_odr(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		setbits_be16(odrp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		setbits_be16(odrp, 1 << (31 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_act(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		clrbits_be16(odrp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		clrbits_be16(odrp, 1 << (31 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_odr(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		return (in_be16(odrp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		return (in_be16(odrp) >> (31 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_act(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *odrp = &immap->im_ioport.iop_paodr;
+
+		return ((in_be16(odrp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		ushort __iomem *odrp = &immap->im_cpm.cp_pbodr;
+
+		return ((in_be16(odrp) >> (31 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_ded(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		setbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		setbits_be32(parp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		setbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		setbits_be16(parp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_gen(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		clrbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		clrbits_be32(parp, 1 << (31 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		clrbits_be16(parp, 1 << (15 - iopin->pin));
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		clrbits_be16(parp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_ded(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		return (in_be32(parp) >> (31 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		return (in_be16(parp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_gen(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTA) {
+		ushort __iomem *parp = &immap->im_ioport.iop_papar;
+
+		return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTB) {
+		uint __iomem *parp = &immap->im_cpm.cp_pbpar;
+
+		return ((in_be32(parp) >> (31 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pcpar;
+
+		return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+	} else if (iopin->port == IOPIN_PORTD) {
+		ushort __iomem *parp = &immap->im_ioport.iop_pdpar;
+
+		return ((in_be16(parp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_opt2(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		setbits_be16(sorp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_opt1(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		clrbits_be16(sorp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_opt2(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		return (in_be16(sorp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_opt1(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *sorp = &immap->im_ioport.iop_pcso;
+
+		return ((in_be16(sorp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+static inline void iopin_set_falledge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		setbits_be16(intp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline void iopin_set_anyedge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		clrbits_be16(intp, 1 << (15 - iopin->pin));
+	}
+}
+
+static inline uint iopin_is_falledge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		return (in_be16(intp) >> (15 - iopin->pin)) & 1;
+	}
+	return 0;
+}
+
+static inline uint iopin_is_anyedge(iopin_t *iopin)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	if (iopin->port == IOPIN_PORTC) {
+		ushort __iomem *intp = &immap->im_ioport.iop_pcint;
+
+		return ((in_be16(intp) >> (15 - iopin->pin)) & 1) ^ 1;
+	}
+	return 0;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IOPIN_8XX_H_ */

arch/powerpc/include/asm/ppc.h

@@ -13,6 +13,9 @@
 
 #ifndef __ASSEMBLY__
 
+#if defined(CONFIG_8xx)
+#include <asm/8xx_immap.h>
+#endif
 #ifdef CONFIG_MPC86xx
 #include <mpc86xx.h>
 #include <asm/immap_86xx.h>
@@ -35,6 +38,9 @@
 #include <asm/arch/immap_lsch2.h>
 #endif
 
+#if defined(CONFIG_8xx)
+uint get_immr(uint);
+#endif
 uint get_pvr(void);
 uint get_svr(void);
 uint rd_ic_cst(void);

arch/powerpc/lib/time.c

@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 
 /* ------------------------------------------------------------------------- */
 
@@ -64,10 +65,21 @@ int timer_init(void)
 {
 	unsigned long temp;
 
+#if defined(CONFIG_8xx)
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/* unlock */
+	out_be32(&immap->im_sitk.sitk_tbk, KAPWR_KEY);
+#endif
+
 	/* reset */
 	asm volatile("li %0,0 ; mttbu %0 ; mttbl %0;"
 	     : "=&r"(temp) );
 
+#if defined(CONFIG_8xx)
+	/* enable */
+	setbits_be16(&immap->im_sit.sit_tbscr, TBSCR_TBE);
+#endif
 	return (0);
 }
 /* ------------------------------------------------------------------------- */

board/amlogic/odroid-c2/odroid-c2.c

@@ -24,6 +24,7 @@ int board_init(void)
 int misc_init_r(void)
 {
 	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
 	ssize_t len;
 
 	/* Set RGMII mode */
@@ -50,5 +51,12 @@ int misc_init_r(void)
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
 
+	if (!getenv("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+			EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE) 
+			setenv("serial#", serial);
+	}
+
 	return 0;
 }

board/atmel/atngw100/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_ATNGW100
-
-config SYS_BOARD
-	default "atngw100"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atngw100"
-
-endif

board/atmel/atngw100/MAINTAINERS

@@ -1,6 +0,0 @@
-ATNGW100 BOARD
-#M:	Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-S:	Orphan (since 2014-06)
-F:	board/atmel/atngw100/
-F:	include/configs/atngw100.h
-F:	configs/atngw100_defconfig

board/atmel/atngw100/Makefile

@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= atngw100.o

board/atmel/atngw100/atngw100.c

@@ -1,109 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_16BIT,
-	.row_bits	= 13,
-	.col_bits	= 9,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-#if defined(CONFIG_ATMEL_SPI)
-	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	gd->bd->bi_phy_id[1] = 0x03;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-	return 0;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#include <spi.h>
-
-#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
-}
-#endif /* CONFIG_ATMEL_SPI */

board/atmel/atngw100mkii/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_ATNGW100MKII
-
-config SYS_BOARD
-	default "atngw100mkii"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atngw100mkii"
-
-endif

board/atmel/atngw100mkii/MAINTAINERS

@@ -1,6 +0,0 @@
-ATNGW100MKII BOARD
-M:	Andreas Bießmann <andreas@biessmann.org>
-S:	Maintained
-F:	board/atmel/atngw100mkii/
-F:	include/configs/atngw100mkii.h
-F:	configs/atngw100mkii_defconfig

board/atmel/atngw100mkii/Makefile

@@ -1,6 +0,0 @@
-#
-# Copyright (C) 2005-2006 Atmel Corporation
-#
-# SPDX-License-Identifier:	GPL-2.0+
-
-obj-y	:= atngw100mkii.o

board/atmel/atngw100mkii/atngw100mkii.c

@@ -1,125 +0,0 @@
-/*
- * Copyright (C) 2010 Atmel Corporation
- *
- * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <spi.h>
-#include <netdev.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		/* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		/* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
-		.virt_pgno	= EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		/* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_32BIT,
-	.row_bits	= 13,
-	.col_bits	= 10,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 6,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
-			| HMATRIX_BIT(EBI_NAND_ENABLE));
-
-	portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
-			PORTMUX_DRIVE_HIGH);
-	portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
-			PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
-			| PORTMUX_DRIVE_MIN);
-
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-#if defined(CONFIG_ATMEL_SPI)
-	portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x01;
-	gd->bd->bi_phy_id[1] = 0x03;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-	return 0;
-}
-#endif
-
-/* SPI chip select control */
-#ifdef CONFIG_ATMEL_SPI
-#define ATNGW100_DATAFLASH_CS_PIN	GPIO_PIN_PA(3)
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs == 0;
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
-}
-#endif /* CONFIG_ATMEL_SPI */

board/atmel/atstk1000/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_ATSTK1002
-
-config SYS_BOARD
-	default "atstk1000"
-
-config SYS_VENDOR
-	default "atmel"
-
-config SYS_SOC
-	default "at32ap700x"
-
-config SYS_CONFIG_NAME
-	default "atstk1002"
-
-endif

board/atmel/atstk1000/MAINTAINERS

@@ -1,6 +0,0 @@
-ATSTK1000 BOARD
-M:	Andreas Bießmann <andreas.biessmann@corscience.de>
-S:	Maintained
-F:	board/atmel/atstk1000/
-F:	include/configs/atstk1002.h
-F:	configs/atstk1002_defconfig

board/atmel/atstk1000/atstk1000.c

@@ -1,89 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <asm/io.h>
-#include <asm/sdram.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hmatrix.h>
-#include <asm/arch/mmu.h>
-#include <asm/arch/portmux.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
-	{
-		.virt_pgno	= CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_NONE,
-	}, {
-		.virt_pgno	= CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
-		.nr_pages	= EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
-		.phys		= (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
-					| MMU_VMR_CACHE_WRBACK,
-	},
-};
-
-static const struct sdram_config sdram_config = {
-	.data_bits	= SDRAM_DATA_32BIT,
-#ifdef CONFIG_ATSTK1000_16MB_SDRAM
-	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
-	.row_bits	= 12,
-#else
-	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
-	.row_bits	= 11,
-#endif
-	.col_bits	= 8,
-	.bank_bits	= 2,
-	.cas		= 3,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 5,
-	.txsr		= 5,
-	/* 15.6 us */
-	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
-
-int board_early_init_f(void)
-{
-	/* Enable SDRAM in the EBI mux */
-	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
-
-	portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
-	sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
-
-	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
-
-#if defined(CONFIG_MACB)
-	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
-	portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
-#endif
-#if defined(CONFIG_MMC)
-	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
-#endif
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	gd->bd->bi_phy_id[0] = 0x10;
-	gd->bd->bi_phy_id[1] = 0x11;
-	return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bi)
-{
-	macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
-	macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
-	return 0;
-}
-#endif

board/cssi/MAINTAINERS

@@ -0,0 +1,6 @@
+BOARDS from CS Systemes d'Information
+M:	Christophe Leroy <christophe.leroy@c-s.fr>
+S:	Maintained
+F:	board/cssi/
+F:	include/configs/MCR3000.h
+F:	configs/MCR3000_defconfig

board/cssi/MCR3000/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_MCR3000
+
+config SYS_BOARD
+	default "MCR3000"
+
+config SYS_VENDOR
+	default "cssi"
+
+config SYS_CONFIG_NAME
+	default "MCR3000"
+
+config SYS_TEXT_BASE
+	default 0x04000000
+
+endif

board/cssi/MCR3000/MCR3000.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2010-2017 CS Systemes d'Information
+ * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
+ * Christophe Leroy <christophe.leroy@c-s.fr>
+ *
+ * Board specific routines for the MCR3000 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <mpc8xx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const uint cs1_dram_table_66[] = {
+	/* DRAM - single read. (offset 0 in upm RAM) */
+	0x0F3DFC04, 0x0FEFBC04, 0x00BE7804, 0x0FFDF400,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - burst read. (offset 8 in upm RAM) */
+	0x0F3DFC04, 0x0FEFBC04, 0x00BF7C04, 0x00FFFC00,
+	0x00FFFC00, 0x00FEF800, 0x0FFDF400, 0x1FFFFC05,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - single write. (offset 18 in upm RAM) */
+	0x0F3DFC04, 0x0FEFB800, 0x00BF7404, 0x0FFEF804,
+	0x0FFDF404, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* DRAM - burst write. (offset 20 in upm RAM) */
+	0x0F3DFC04, 0x0FEFB800, 0x00BF7400, 0x00FFFC00,
+	0x00FFFC00, 0x00FFFC04,	0x0FFEF804, 0x0FFDF404,
+	0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+	0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+
+	/* refresh  (offset 30 in upm RAM) */
+	0x0FFDF404, 0x0FFEBC04, 0x0FFD7C84, 0x0FFFFC04,
+	0x0FFFFC04, 0x0FFFFC04, 0x1FFFFC85, 0xFFFFFFFF,
+
+	/* init */
+	0x0FEEB874, 0x0FBD7474, 0x1FFFFC45, 0xFFFFFFFF,
+
+	/* exception. (offset 3c in upm RAM) */
+	0xFFFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	const char *sync = "receive";
+
+	ft_cpu_setup(blob, bd);
+
+	/* BRG */
+	do_fixup_by_path_u32(blob, "/soc/cpm", "brg-frequency",
+			     bd->bi_busfreq, 1);
+
+	/* MAC addr */
+	fdt_fixup_ethernet(blob);
+
+	/* Bus Frequency for CPM */
+	do_fixup_by_path_u32(blob, "/soc", "bus-frequency", bd->bi_busfreq, 1);
+
+	/* E1 interface - Set data rate */
+	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "data-rate", 2, 1);
+
+	/* E1 interface - Set channel phase to 0 */
+	do_fixup_by_path_u32(blob, "/localbus/e1-wan", "channel-phase", 0, 1);
+
+	/* E1 interface - rising edge sync pulse transmit */
+	do_fixup_by_path(blob, "/localbus/e1-wan", "rising-edge-sync-pulse",
+			 sync, strlen(sync), 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	serial_puts("BOARD: MCR3000 CSSI\n");
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	memctl8xx_t __iomem *memctl = &immap->im_memctl;
+
+	printf("UPMA init for SDRAM (CAS latency 2), ");
+	printf("init address 0x%08x, size ", (int)dram_init);
+	/* Configure UPMA for cs1 */
+	upmconfig(UPMA, (uint *)cs1_dram_table_66,
+		  sizeof(cs1_dram_table_66) / sizeof(uint));
+	udelay(10);
+	out_be16(&memctl->memc_mptpr, 0x0200);
+	out_be32(&memctl->memc_mamr, 0x14904000);
+	udelay(10);
+	out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
+	out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
+	udelay(10);
+	out_be32(&memctl->memc_mcr, 0x80002830);
+	out_be32(&memctl->memc_mar, 0x00000088);
+	out_be32(&memctl->memc_mcr, 0x80002038);
+	udelay(200);
+
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    SDRAM_MAX_SIZE);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+	iop8xx_t __iomem *iop = &immr->im_ioport;
+
+	/* Set port C13 as GPIO (BTN_ACQ_AL) */
+	clrbits_be16(&iop->iop_pcpar, 0x4);
+	clrbits_be16(&iop->iop_pcdir, 0x4);
+
+	/* if BTN_ACQ_AL is pressed then bootdelay is changed to 60 second */
+	if ((in_be16(&iop->iop_pcdat) & 0x0004) == 0)
+		setenv("bootdelay", "60");
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Erase FPGA(s) for reboot
+	 */
+	clrbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA down */
+	setbits_be32(&immr->im_cpm.cp_pbdir, 0x00020000); /* PROGFPGA output */
+	udelay(1);				/* Wait more than 300ns */
+	setbits_be32(&immr->im_cpm.cp_pbdat, 0x00020000); /* PROGFPGA up */
+
+	return 0;
+}

board/cssi/MCR3000/Makefile

@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2010-2017 CS Systemes d'Information
+# Christophe Leroy <christophe.leroy@c-s.fr>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+#
+
+obj-y += MCR3000.o
+obj-$(CONFIG_CMD_NAND) += nand.o