Prepare v2017.11

Signed-off-by: Tom Rini <trini@konsulko.com>

Makefile

@@ -5,7 +5,7 @@
 VERSION = 2017
 PATCHLEVEL = 11
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION =
 NAME =
 
 # *DOCUMENTATION*

arch/arm/Kconfig

@@ -341,17 +341,6 @@ config TARGET_WORK_92105
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
 
-config TARGET_MX25PDK
-	bool "Support mx25pdk"
-	select BOARD_LATE_INIT
-	select CPU_ARM926EJS
-	select BOARD_EARLY_INIT_F
-
-config TARGET_ZMX25
-	bool "Support zmx25"
-	select BOARD_LATE_INIT
-	select CPU_ARM926EJS
-
 config TARGET_APF27
 	bool "Support apf27"
 	select CPU_ARM926EJS
@@ -599,6 +588,10 @@ config ARCH_MESON
 	  targeted at media players and tablet computers. We currently
 	  support the S905 (GXBaby) 64-bit SoC.
 
+config ARCH_MX25
+	bool "NXP MX25"
+	select CPU_ARM926EJS
+
 config ARCH_MX7ULP
         bool "NXP MX7ULP"
         select CPU_V7
@@ -1162,6 +1155,8 @@ source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
+source "arch/arm/mach-imx/mx2/Kconfig"
+
 source "arch/arm/mach-imx/mx7ulp/Kconfig"
 
 source "arch/arm/mach-imx/mx7/Kconfig"
@@ -1244,7 +1239,6 @@ source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
-source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
 source "board/freescale/mx31ads/Kconfig"
 source "board/freescale/mx31pdk/Kconfig"
@@ -1270,7 +1264,6 @@ source "board/spear/spear320/Kconfig"
 source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st/stv0991/Kconfig"
-source "board/syteco/zmx25/Kconfig"
 source "board/tcl/sl50/Kconfig"
 source "board/birdland/bav335x/Kconfig"
 source "board/timll/devkit3250/Kconfig"

arch/arm/cpu/armv7/stv0991/Makefile

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2014
-# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

arch/arm/cpu/armv7/stv0991/clock.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/cpu/armv7/stv0991/pinmux.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/cpu/armv7/stv0991/reset.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/cpu/armv7/stv0991/timer.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/cpu/armv7m/cache.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2017
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/cpu/armv7m/mpu.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2017
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/dts/exynos5422-odroidxu3.dts

@@ -124,8 +124,8 @@
 
 				ldo15_reg: LDO15 {
 					regulator-name = "vdd_ldo15";
-					regulator-min-microvolt = <3100000>;
-					regulator-max-microvolt = <3100000>;
+					regulator-min-microvolt = <3300000>;
+					regulator-max-microvolt = <3300000>;
 					regulator-always-on;
 				};
 
@@ -137,7 +137,7 @@
 				};
 
 				ldo17_reg: LDO17 {
-					regulator-name = "tsp_avdd";
+					regulator-name = "vdd_ldo17";
 					regulator-min-microvolt = <3300000>;
 					regulator-max-microvolt = <3300000>;
 					regulator-always-on;

arch/arm/dts/imx6q-display5.dts

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+
+/ {
+	model = "Liebherr (LWN) display5 i.MX6 Quad Board";
+	compatible = "lwn,display5", "fsl,imx6q";
+};

arch/arm/dts/rk3368-lion.dts

@@ -68,7 +68,7 @@
 	phy-supply = <&vcc33_io>;
 	phy-mode = "rgmii";
 	clock_in_out = "input";
-	snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+	snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <2 10000 50000>;
 	assigned-clocks = <&cru SCLK_MAC>;

arch/arm/dts/rk3399-firefly.dts

@@ -332,10 +332,10 @@
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-max-microvolt = <3000000>;
 				regulator-state-mem {
 					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
+					regulator-suspend-microvolt = <3000000>;
 				};
 			};
 

arch/arm/dts/rk3399-puma.dtsi

@@ -36,13 +36,13 @@
 
 		module_led {
 			label = "module_led";
-			gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "heartbeat";
 		};
 
 		sd_card_led {
 			label = "sd_card_led";
-			gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
 			linux,default-trigger = "mmc0";
 		};
 	};
@@ -94,8 +94,7 @@
 		compatible = "regulator-fixed";
 		regulator-name = "usbhub_enable";
 		enable-active-low;
-		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
-		regulator-always-on;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
 		regulator-boot-on;
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
@@ -111,8 +110,8 @@
 		compatible = "regulator-fixed";
 		u-boot,dm-pre-reloc;
 		regulator-name = "bios_enable";
-		enable-active-low;
-		gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
 		regulator-always-on;
 		regulator-boot-on;
 		regulator-min-microvolt = <1800000>;
@@ -140,7 +139,7 @@
 	vcc5v0_otg: vcc5v0-otg-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
-		gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&otg_vbus_drv>;
 		regulator-name = "vcc5v0_otg";
@@ -150,7 +149,7 @@
 	vcc5v0_host: vcc5v0-host-regulator {
 		compatible = "regulator-fixed";
 		enable-active-low;
-		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&host_vbus_drv>;
 		regulator-name = "vcc5v0_host";
@@ -196,7 +195,7 @@
 	phy-supply = <&vcc_phy>;
 	phy-mode = "rgmii";
 	clock_in_out = "input";
-	snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
+	snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
 	snps,reset-active-low;
 	snps,reset-delays-us = <2 10000 50000>;
 	assigned-clocks = <&cru SCLK_RMII_SRC>;
@@ -224,7 +223,7 @@
 	vdd_gpu: fan535555@60 {
 		compatible = "fcs,fan53555";
 		reg = <0x60>;
-		vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
 		vin-supply = <&vcc5v0_sys>;
 		regulator-compatible = "fan53555-reg";
 		regulator-name = "vdd_gpu";
@@ -348,11 +347,11 @@
 				regulator-always-on;
 				regulator-boot-on;
 				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
+				regulator-max-microvolt = <3000000>;
 				regulator-name = "vcc_sd";
 				regulator-state-mem {
 					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
+					regulator-suspend-microvolt = <3000000>;
 				};
 			};
 
@@ -426,7 +425,7 @@
 	vdd_cpu_b: fan53555@60 {
 		compatible = "fcs,fan53555";
 		reg = <0x60>;
-		vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+		vsel-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
 		vin-supply = <&vcc5v0_sys>;
 		regulator-compatible = "fan53555-reg";
 		regulator-name = "vdd_cpu_b";
@@ -469,7 +468,7 @@
 	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
 	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
 	assigned-clock-rates = <100000000>;
-	ep-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+	ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie_clkreqn>;
@@ -524,23 +523,23 @@
 };
 
 &usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host0_ohci {
-	status = "okay";
-};
-
-&dwc3_typec0 {
 	status = "disabled";
 };
 
-&usb_host1_ehci {
+&usb_host0_ohci {
+	status = "disabled";
+};
+
+&dwc3_typec0 {
 	status = "okay";
 };
 
+&usb_host1_ehci {
+	status = "disabled";
+};
+
 &usb_host1_ohci {
-	status = "okay";
+	status = "disabled";
 };
 
 &dwc3_typec1 {
@@ -564,42 +563,43 @@
 		puma_pin_hog: puma_pin_hog {
 			rockchip,pins =
 				/* We need pull-ups on Q7 buttons */
-				<0  4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
-				<0 10 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
-				<0 11 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
-				<0  9 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
+				<RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, /* LID_BTN# */
+				<RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, /* BATLOW# */
+				<RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, /* SLP_BTN# */
+				<RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; /* BIOS_DISABLE# */
 		};
 	};
 
 	pmic {
 		pmic_int_l: pmic-int-l {
 			rockchip,pins =
-				<1 22 RK_FUNC_GPIO &pcfg_pull_up>;
+				<RK_GPIO1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
 		};
 	};
 
 	leds_pins_puma: led_pins@0 {
 			rockchip,pins =
-				<2 25 RK_FUNC_GPIO &pcfg_pull_none>,
-				<1 2 RK_FUNC_GPIO &pcfg_pull_none>;
+				<RK_GPIO2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
+				<RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 	};
 
 	usb2 {
 		otg_vbus_drv: otg-vbus-drv {
 			rockchip,pins =
-				<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+				<RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 
 		host_vbus_drv: host-vbus-drv {
 			rockchip,pins =
-				<0 2 RK_FUNC_GPIO &pcfg_pull_none>;
+				<RK_GPIO4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
 
 	i2c8 {
 		i2c8_xfer_a: i2c8-xfer {
-			rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>,
-					<1 20 RK_FUNC_1 &pcfg_pull_up>;
+			rockchip,pins =
+				<RK_GPIO1 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
+				<RK_GPIO1 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
 		};
 	};
 };
@@ -624,8 +624,8 @@
 &i2c6_xfer {
 	/* Enable pull-ups, the pins would float otherwise. */
 	rockchip,pins =
-		<2 10 RK_FUNC_2 &pcfg_pull_up>,
-		<2 9 RK_FUNC_2 &pcfg_pull_up>;
+		<RK_GPIO2 RK_PB2 RK_FUNC_2 &pcfg_pull_up>,
+		<RK_GPIO2 RK_PB1 RK_FUNC_2 &pcfg_pull_up>;
 };
 
 &i2c7 {

arch/arm/dts/salvator-common.dtsi

@@ -438,7 +438,7 @@
 	sdhi2_pins: sd2 {
 		groups = "sdhi2_data8", "sdhi2_ctrl";
 		function = "sdhi2";
-		power-source = <3300>;
+		power-source = <1800>;
 	};
 
 	sdhi2_pins_uhs: sd2_uhs {

arch/arm/include/asm/arch-mx5/sys_proto.h

@@ -4,5 +4,9 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+#ifndef __SYS_PROTO_IMX5_
+#define __SYS_PROTO_IMX5_
 
 #include <asm/mach-imx/sys_proto.h>
+
+#endif /* __SYS_PROTO_IMX5_ */

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -346,6 +346,9 @@
 #define IOMUXC_SNVS_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x90000)
 #define SNVS_GPR_BASE_ADDR          (AIPS3_ARB_BASE_ADDR + 0x94000)
 #endif
+
+#define NOC_DDR_BASE_ADDR           (GPV0_BASE_ADDR + 0xB0000)
+
 /* Only for i.MX6SX */
 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)

arch/arm/include/asm/arch-mx6/iomux.h

@@ -178,4 +178,17 @@
 				|IOMUXC_GPR13_SATA_PHY_3_MASK \
 				|IOMUXC_GPR13_SATA_PHY_2_MASK \
 				|IOMUXC_GPR13_SATA_PHY_1_MASK)
+
+/*
+ * Setup RGMII voltage levels on iMX6 SoC - the
+ *
+ * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register
+ *
+ * 1P2V_IO - USB_HSIC, MIPI_HSI
+ * 1P5V_IO - ENET pins
+ */
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII	0x020e0790
+#define DDR_SEL_1P2V_IO (0x2 << 18)
+#define DDR_SEL_1P5V_IO (0x3 << 18)
+
 #endif	/* __ASM_ARCH_IOMUX_H__ */

arch/arm/include/asm/arch-mx6/sys_proto.h

@@ -5,7 +5,11 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#ifndef __SYS_PROTO_IMX6_
+#define __SYS_PROTO_IMX6_
+
 #include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/iomux.h>
 
 #define USBPHY_PWD		0x00000000
 
@@ -16,3 +20,15 @@
 
 int imx6_pcie_toggle_power(void);
 int imx6_pcie_toggle_reset(void);
+
+/**
+ * iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins
+ *
+ * @param io_vol - the voltage IO level of pins
+ */
+static inline void iomuxc_set_rgmii_io_voltage(int io_vol)
+{
+	__raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII);
+}
+
+#endif /* __SYS_PROTO_IMX6_ */

arch/arm/include/asm/arch-mx7/sys_proto.h

@@ -3,8 +3,12 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+#ifndef __SYS_PROTO_IMX7_
+#define __SYS_PROTO_IMX7_
 
 #include <asm/mach-imx/sys_proto.h>
 
 void set_wdog_reset(struct wdog_regs *wdog);
 enum boot_device get_boot_device(void);
+
+#endif /* __SYS_PROTO_IMX7_ */

arch/arm/include/asm/arch-spear/clk.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2010
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ * Copyright (C) 2010, STMicroelectronics - All Rights Reserved
+ * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-spear/hardware.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2009
- * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
+ * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stih410/sdhci.h

@@ -1,5 +1,6 @@
 /*
- * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stih410/sys_proto.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2017
- * Patrice Chotard <patrice.chotard@st.com>
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f4/stm32_defs.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f4/stm32_periph.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f7/gpio.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, <vikas.manocha@st.com>
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f7/gpt.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f7/rcc.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f7/stm32.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f7/stm32_defs.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32f7/stm32_periph.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32h7/gpio.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stm32h7/stm32.h

@@ -1,6 +1,6 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/gpio.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/hardware.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/stv0991_cgu.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/stv0991_creg.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/stv0991_defs.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/stv0991_gpt.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/stv0991_periph.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/arch-stv0991/stv0991_wdru.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/include/asm/armv7m_mpu.h

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2017
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/mach-imx/mx2/Kconfig

@@ -0,0 +1,30 @@
+if ARCH_MX25
+
+config MX25
+	bool
+	default y
+	select SYS_FSL_ERRATUM_ESDHC_A001
+choice
+	prompt "MX25 board select"
+	optional
+
+config TARGET_MX25PDK
+	bool "Support mx25pdk"
+	select BOARD_LATE_INIT
+	select CPU_ARM926EJS
+	select BOARD_EARLY_INIT_F
+
+config TARGET_ZMX25
+	bool "Support zmx25"
+	select BOARD_LATE_INIT
+	select CPU_ARM926EJS1
+
+endchoice
+
+config SYS_SOC
+	default "mx25"
+
+source "board/freescale/mx25pdk/Kconfig"
+source "board/syteco/zmx25/Kconfig"
+
+endif

arch/arm/mach-imx/mx5/Kconfig

@@ -6,6 +6,7 @@ config MX5
 
 config MX51
 	bool
+	select SYS_FSL_ERRATUM_ESDHC_A001
 
 config MX53
 	bool
@@ -52,7 +53,6 @@ config TARGET_MX53SMD
 config TARGET_TS4800
 	bool "Support TS4800"
 	select MX51
-	select SYS_FSL_ERRATUM_ESDHC_A001
 
 config TARGET_USBARMORY
 	bool "Support USB armory"

arch/arm/mach-imx/mx6/Kconfig

@@ -138,6 +138,12 @@ config TARGET_DHCOMIMX6
 	select DM_THERMAL
 	imply CMD_SPL
 
+config TARGET_DISPLAY5
+	bool "LWN DISPLAY5 board"
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
@@ -459,6 +465,7 @@ source "board/phytec/pfla02/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
+source "board/liebherr/display5/Kconfig"
 source "board/liebherr/mccmon6/Kconfig"
 source "board/logicpd/imx6/Kconfig"
 source "board/seco/Kconfig"

arch/arm/mach-rmobile/Kconfig.32

@@ -1,7 +1,7 @@
 if RCAR_32
 
 choice
-	prompt "Renesus ARM SoCs board select"
+	prompt "Renesas ARM SoCs board select"
 	optional
 
 config TARGET_ARMADILLO_800EVA

arch/arm/mach-rockchip/rk3328/clk_rk3328.c

@@ -25,7 +25,7 @@ void *rockchip_get_cru(void)
 	if (ret)
 		return ERR_PTR(ret);
 
-	priv = devfdt_get_addr_ptr(dev);
+	priv = dev_get_priv(dev);
 
 	return priv->cru;
 }

arch/arm/mach-stm32/stm32f7/Makefile

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2016
-# Vikas Manocha, <vikas.manocha@gmail.com>
+# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

arch/arm/mach-stm32/stm32f7/timer.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

arch/arm/mach-stm32/stm32h7/Makefile

@@ -1,6 +1,6 @@
 #
-# Copyright (c) 2017
-# Patrice Chotard <patrice.chotard@st.com>
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

arch/arm/mach-stm32/stm32h7/soc.c

@@ -1,6 +1,6 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

board/CZ.NIC/turris_omnia/MAINTAINERS

@@ -0,0 +1,6 @@
+TURRIS OMNIA BOARD
+M:	Marek Behún <marek.behun@nic.cz>
+S:	Maintained
+F:	board/CZ.NIC/turris_omnia/
+F:	include/configs/turris_omnia.h
+F:	configs/turris_omnia_defconfig

board/Marvell/mvebu_armada-37xx/MAINTAINERS

@@ -4,3 +4,8 @@ S:	Maintained
 F:	board/Marvell/mvebu_armada-37xx/
 F:	include/configs/mvebu_armada-37xx.h
 F:	configs/mvebu_db-88f3720_defconfig
+
+ESPRESSOBin BOARD
+M:	Konstantin Porotchkin <kostap@marvell.com>
+S:	Maintained
+F:	configs/mvebu_espressobin-88f3720_defconfig

board/Marvell/mvebu_armada-8k/MAINTAINERS

@@ -3,5 +3,10 @@ M:	Stefan Roese <sr@denx.de>
 S:	Maintained
 F:	board/Marvell/mvebu_armada-8k/
 F:	include/configs/mvebu_armada-8k.h
-F:	configs/mvebu_db-88f7040_defconfig
-F:	configs/mvebu_db-88f8040_defconfig
+F:	configs/mvebu_db_armada8k_defconfig
+
+
+MACCHIATOBin BOARD
+M:	Konstantin Porotchkin <kostap@marvell.com>
+S:	Maintained
+F:	configs/mvebu_mcbin-88f8040_defconfig

board/Synology/ds414/MAINTAINERS

@@ -0,0 +1,6 @@
+DS414 BOARD
+M:	Phil Sutter <phil@nwl.cc>
+S:	Maintained
+F:	board/Synology/ds414/
+F:	include/configs/ds414.h
+F:	configs/ds414_defconfig

board/altera/arria10-socdk/MAINTAINERS

@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M:	Dinh Nguyen <dinguyen@kernel.org>
+M:	Chin-Liang See <clsee@altera.com>
+S:	Maintained
+F:	board/altera/arria10-socdk/
+F:	include/configs/socfpga_arria10_socdk.h
+F:	configs/socfpga_arria10_defconfig

board/aspeed/evb_ast2500/MAINTAINERS

@@ -0,0 +1,6 @@
+EVB AST2500 BOARD
+M:	Maxim Sloyko <maxims@google.com>
+S:	Maintained
+F:	board/aspeed/evb_ast2500/
+F:	include/configs/evb_ast2500.h
+F:	configs/evb-ast2500_defconfig

board/atmel/sama5d3xek/MAINTAINERS

@@ -6,3 +6,6 @@ F:	include/configs/sama5d3xek.h
 F:	configs/sama5d3xek_mmc_defconfig
 F:	configs/sama5d3xek_nandflash_defconfig
 F:	configs/sama5d3xek_spiflash_defconfig
+F:	configs/sama5d36ek_cmp_mmc_defconfig
+F:	configs/sama5d36ek_cmp_nandflash_defconfig
+F:	configs/sama5d36ek_cmp_spiflash_defconfig

board/dhelectronics/dh_imx6/MAINTAINERS

@@ -1,7 +1,7 @@
 DH_IMX6 BOARD
-M:	Andreas Geisreiter <ageisreiter@dh-electronics.de>, Ludwig Zenz <lzenz@dh-electronics.de>
+M:	Andreas Geisreiter <ageisreiter@dh-electronics.de>
+M:	Ludwig Zenz <lzenz@dh-electronics.de>
 S:	Maintained
 F:	board/dhelectronics/dh_imx6/
 F:	include/configs/dh_imx6.h
-F:	configs/dh_mx6q_defconfig
-F:	configs/dh_mx6dl_defconfig
+F:	configs/dh_imx6_defconfig

board/dhelectronics/dh_imx6/dh_imx6.c

@@ -252,17 +252,11 @@ static void setup_usb(void)
 }
 
 int board_usb_phy_mode(int port)
-{
-	return USB_INIT_HOST;
-}
-
-/* Use only Port 1 == DHCOM USB Host 1 */
-int board_ehci_hcd_init(int port)
 {
 	if (port == 1)
-		return 0;
+		return USB_INIT_HOST;
 	else
-		return -ENODEV;
+		return USB_INIT_DEVICE;
 }
 
 int board_ehci_power(int port, int on)

board/embest/mx6boards/mx6boards.c

@@ -36,7 +36,7 @@
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 #include <asm/io.h>
-#include <asm/arch/sys_proto.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\

board/engicam/geam6ul/MAINTAINERS

@@ -2,7 +2,7 @@ GEAM6UL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/geam6ul
-F:	include/configs/imx6ul_geam.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6ul_geam_mmc_defconfig
 F:	configs/imx6ul_geam_nand_defconfig
 F:	arch/arm/dts/imx6ul-geam-kit.dts

board/engicam/icorem6/MAINTAINERS

@@ -2,7 +2,7 @@ ICOREM6QDL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6
-F:	include/configs/imx6qdl_icore.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6qdl_icore_mmc_defconfig
 F:	configs/imx6qdl_icore_nand_defconfig
 F:	arch/arm/dts/imx6qdl-icore.dtsi

board/engicam/icorem6/README

@@ -3,11 +3,8 @@ How to use U-Boot on Engicam i.CoreM6 Solo/DualLite and Quad/Dual Starter Kit:
 
 $ make mrproper
 
-- Configure U-Boot for Engicam i.CoreM6 Quad/Dual:
-$ make imx6q_icore_mmc_defconfig
-
-- Configure U-Boot for Engicam i.CoreM6 Solo/DualLite:
-$ make imx6dl_icore_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 Quad/Dual/Solo/DualLite:
+$ make imx6qdl_icore_mmc_defconfig
 
 - Build U-Boot
 $ make

board/engicam/icorem6_rqs/MAINTAINERS

@@ -2,7 +2,7 @@ ICOREM6QDL_RQS BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/icorem6_rqs
-F:	include/configs/imx6qdl_icore_rqs.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6qdl_icore_rqs_defconfig
 F:	arch/arm/dts/imx6qdl-icore-rqs.dtsi
 F:	arch/arm/dts/imx6q-icore-rqs.dts

board/engicam/icorem6_rqs/README

@@ -3,11 +3,8 @@ How to use U-Boot on Engicam i.CoreM6 RQS Solo/DualLite and Quad/Dual Starter Ki
 
 $ make mrproper
 
-- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual:
-$ make imx6q_icore_rqs_mmc_defconfig
-
-- Configure U-Boot for Engicam i.CoreM6 RQS Solo/DualLite:
-$ make imx6dl_icore_rqs_mmc_defconfig
+- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual/Solo/DualLite:
+$ make imx6qdl_icore_rqs_defconfig
 
 - Build U-Boot
 $ make

board/engicam/isiotmx6ul/MAINTAINERS

@@ -2,7 +2,7 @@ ISIOTMX6UL BOARD
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained
 F:	board/engicam/isiotmx6ul
-F:	include/configs/imx6ul_isiot.h
+F:	include/configs/imx6-engicam.h
 F:	configs/imx6ul_isiot_mmc_defconfig
 F:	configs/imx6ul_isiot_emmc_defconfig
 F:	configs/imx6ul_isiot_nand_defconfig

board/freescale/ls1046aqds/MAINTAINERS

@@ -8,6 +8,7 @@ F:	configs/ls1046aqds_nand_defconfig
 F:	configs/ls1046aqds_sdcard_ifc_defconfig
 F:	configs/ls1046aqds_sdcard_qspi_defconfig
 F:	configs/ls1046aqds_qspi_defconfig
+F:	configs/ls1046aqds_lpuart_defconfig
 
 M:	Sumit Garg <sumit.garg@nxp.com>
 S:	Maintained

board/freescale/mx6slevk/mx6slevk.c

@@ -27,8 +27,6 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
-#include <usb.h>
-#include <usb/ehci-ci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -223,49 +221,6 @@ static int setup_fec(void)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-#define USB_OTHERREGS_OFFSET	0x800
-#define UCTRL_PWR_POL		(1 << 9)
-
-static iomux_v3_cfg_t const usb_otg_pads[] = {
-	/* OTG1 */
-	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
-	/* OTG2 */
-	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
-};
-
-static void setup_usb(void)
-{
-	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
-					 ARRAY_SIZE(usb_otg_pads));
-}
-
-int board_usb_phy_mode(int port)
-{
-	if (port == 1)
-		return USB_INIT_HOST;
-	else
-		return usb_phy_mode(port);
-}
-
-int board_ehci_hcd_init(int port)
-{
-	u32 *usbnc_usb_ctrl;
-
-	if (port > 1)
-		return -EINVAL;
-
-	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
-				 port * 4);
-
-	/* Set Power polarity */
-	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
-
-	return 0;
-}
-#endif
-
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -287,10 +242,6 @@ int board_init(void)
 	setup_fec();
 #endif
 
-#ifdef CONFIG_USB_EHCI_MX6
-	setup_usb();
-#endif
-
 	return 0;
 }
 
@@ -322,12 +273,15 @@ int board_mmc_getcd(struct mmc *mmc)
 
 	switch (cfg->esdhc_base) {
 	case USDHC1_BASE_ADDR:
+		gpio_request(USDHC1_CD_GPIO, "cd1_gpio");
 		ret = !gpio_get_value(USDHC1_CD_GPIO);
 		break;
 	case USDHC2_BASE_ADDR:
+		gpio_request(USDHC2_CD_GPIO, "cd2_gpio");
 		ret = !gpio_get_value(USDHC2_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
+		gpio_request(USDHC3_CD_GPIO, "cd3_gpio");
 		ret = !gpio_get_value(USDHC3_CD_GPIO);
 		break;
 	}

board/gdsys/mpc8308/MAINTAINERS

@@ -7,4 +7,6 @@ F:	configs/hrcon_defconfig
 F:	configs/hrcon_dh_defconfig
 F:	include/configs/strider.h
 F:	configs/strider_cpu_defconfig
+F:	configs/strider_cpu_dp_defconfig
 F:	configs/strider_con_defconfig
+F:	configs/strider_con_dp_defconfig

board/isee/igep003x/MAINTAINERS

@@ -3,4 +3,4 @@ M:	Enric Balletbo i Serra <eballetbo@gmail.com>
 S:	Maintained
 F:	board/isee/igep003x/
 F:	include/configs/am335x_igep003x.h
-F:	configs/am335x_igep0033_defconfig
+F:	configs/am335x_igep003x_defconfig

board/liebherr/display5/Kconfig

@@ -0,0 +1,18 @@
+if TARGET_DISPLAY5
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "display5"
+
+config SYS_VENDOR
+	default "liebherr"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "display5"
+
+endif

board/liebherr/display5/MAINTAINERS

@@ -0,0 +1,7 @@
+DISPLAY5 BOARD
+M:	Lukasz Majewski <lukma@denx.de>
+S:	Maintained
+F:	board/liebherr/display5/
+F:	include/configs/display5.h
+F:	configs/display5_defconfig
+F:	configs/display5_factory_defconfig

board/liebherr/display5/Makefile

@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2017, DENX Software Engineering
+# Lukasz Majewski <lukma@denx.de>
+#
+# SPDX-License-Identifier:    GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+obj-y = common.o spl.o
+else
+obj-y := common.o display5.o
+endif

board/liebherr/display5/common.c

@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/mx6-pins.h>
+#include "common.h"
+
+iomux_v3_cfg_t const uart_pads[] = {
+	/* UART4 */
+	MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart_console_pads[] = {
+	/* UART5 */
+	MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void displ5_set_iomux_uart_spl(void)
+{
+	SETUP_IOMUX_PADS(uart_console_pads);
+}
+
+void displ5_set_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart_pads);
+}
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi_pads[] = {
+	/* SPI3 */
+	MX6_PAD_DISP0_DAT2__ECSPI3_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT1__ECSPI3_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT0__ECSPI3_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_DISP0_DAT3__ECSPI3_SS0	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT4__ECSPI3_SS1	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT5__ECSPI3_SS2	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT6__ECSPI3_SS3	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_DISP0_DAT7__ECSPI3_RDY	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi2_pads[] = {
+	/* SPI2, NOR Flash nWP, CS0 */
+	MX6_PAD_CSI0_DAT10__ECSPI2_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI0_DAT11__GPIO5_IO29	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
+{
+	if (bus != 1 || cs != (IMX_GPIO_NR(5, 29) << 8))
+		return -EINVAL;
+
+	return IMX_GPIO_NR(5, 29);
+}
+
+void displ5_set_iomux_ecspi_spl(void)
+{
+	SETUP_IOMUX_PADS(ecspi2_pads);
+}
+
+void displ5_set_iomux_ecspi(void)
+{
+	SETUP_IOMUX_PADS(ecspi_pads);
+}
+
+#else
+void displ5_set_iomux_ecspi_spl(void) {}
+void displ5_set_iomux_ecspi(void) {}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NANDF_ALE__SD4_RESET	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void displ5_set_iomux_usdhc_spl(void)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+void displ5_set_iomux_usdhc(void)
+{
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+#else
+void displ5_set_iomux_usdhc_spl(void) {}
+void displ5_set_iomux_usdhc(void) {}
+#endif

board/liebherr/display5/common.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DISPL5_COMMON_H_
+#define __DISPL5_COMMON_H_
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+void displ5_set_iomux_uart_spl(void);
+void displ5_set_iomux_uart(void);
+void displ5_set_iomux_ecspi_spl(void);
+void displ5_set_iomux_ecspi(void);
+void displ5_set_iomux_usdhc_spl(void);
+void displ5_set_iomux_usdhc(void);
+
+#endif /* __DISPL5_COMMON_H_ */

board/liebherr/display5/display5.c

@@ -0,0 +1,384 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <malloc.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <i2c.h>
+
+#include <dm.h>
+#include <dm/platform_data/serial_mxc.h>
+#include <dm/platdata.h>
+
+#ifndef CONFIG_MXC_SPI
+#error "CONFIG_SPI must be set for this board"
+#error "Please check your config file"
+#endif
+
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool hw_ids_valid;
+static bool sw_ids_valid;
+static u32 cpu_id;
+static u32 unit_id;
+
+#define SW0	IMX_GPIO_NR(2, 4)
+#define SW1	IMX_GPIO_NR(2, 5)
+#define SW2	IMX_GPIO_NR(2, 6)
+#define SW3	IMX_GPIO_NR(2, 7)
+#define HW0	IMX_GPIO_NR(6, 7)
+#define HW1	IMX_GPIO_NR(6, 9)
+#define HW2	IMX_GPIO_NR(6, 10)
+#define HW3	IMX_GPIO_NR(6, 11)
+#define HW4	IMX_GPIO_NR(4, 7)
+#define HW5	IMX_GPIO_NR(4, 11)
+#define HW6	IMX_GPIO_NR(4, 13)
+#define HW7	IMX_GPIO_NR(4, 15)
+
+int gpio_table_sw_ids[] = {
+	SW0, SW1, SW2, SW3
+};
+
+const char *gpio_table_sw_ids_names[] = {
+	"sw0", "sw1", "sw2", "sw3"
+};
+
+int gpio_table_hw_ids[] = {
+	HW0, HW1, HW2, HW3, HW4, HW5, HW6, HW7
+};
+
+const char *gpio_table_hw_ids_names[] = {
+	"hw0", "hw1", "hw2", "hw3", "hw4", "hw5", "hw6", "hw7"
+};
+
+static int get_board_id(int *ids, const char **c, int size,
+			bool *valid, u32 *id)
+{
+	int i, ret, val;
+
+	*valid = false;
+
+	for (i = 0; i < size; i++) {
+		ret = gpio_request(ids[i], c[i]);
+		if (ret) {
+			printf("Can't request SWx gpios\n");
+			return ret;
+		}
+	}
+
+	for (i = 0; i < size; i++) {
+		ret = gpio_direction_input(ids[i]);
+		if (ret) {
+			printf("Can't set SWx gpios direction\n");
+			return ret;
+		}
+	}
+
+	for (i = 0; i < size; i++) {
+		val = gpio_get_value(ids[i]);
+		if (val < 0) {
+			printf("Can't get SW%d ID\n", i);
+			*id = 0;
+			return val;
+		}
+		*id |= val << i;
+	}
+	*valid = true;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1: TFA9879 */
+struct i2c_pads_info i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+		.gp = IMX_GPIO_NR(3, 28)
+	}
+};
+
+/* I2C2: TIVO TM4C123 */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.gp = IMX_GPIO_NR(2, 30)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+		.gp = IMX_GPIO_NR(3, 16)
+	}
+};
+
+/* I2C3: PMIC PF0100, EEPROM AT24C256C */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+		.gp = IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+iomux_v3_cfg_t const misc_pads[] = {
+	/* Prod ID GPIO pins */
+	MX6_PAD_NANDF_D4__GPIO2_IO04    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D5__GPIO2_IO05    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_D7__GPIO2_IO07    | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* HW revision GPIO pins */
+	MX6_PAD_NANDF_CLE__GPIO6_IO07   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_WP_B__GPIO6_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_RB0__GPIO6_IO10   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NANDF_CS0__GPIO6_IO11   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* XTALOSC */
+	MX6_PAD_GPIO_3__XTALOSC_REF_CLK_24M | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{ USDHC4_BASE_ADDR, 0, 8, },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	displ5_set_iomux_usdhc();
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static void displ5_setup_ecspi(void)
+{
+	int ret;
+
+	displ5_set_iomux_ecspi();
+
+	ret = gpio_request(IMX_GPIO_NR(5, 29), "spi2_cs0");
+	if (!ret)
+		gpio_direction_output(IMX_GPIO_NR(5, 29), 1);
+
+	ret = gpio_request(IMX_GPIO_NR(7, 0), "spi2_#wp");
+	if (!ret)
+		gpio_direction_output(IMX_GPIO_NR(7, 0), 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+iomux_v3_cfg_t const enet_pads[] = {
+	MX6_PAD_ENET_TXD1__ENET_1588_EVENT0_IN	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* for old evalboard with R159 present and R160 not populated */
+	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/*INT#_GBE*/
+	MX6_PAD_ENET_TX_EN__GPIO1_IO28		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+	gpio_direction_input(IMX_GPIO_NR(1, 28)); /*INT#_GBE*/
+}
+
+int board_eth_init(bd_t *bd)
+{
+	struct phy_device *phydev;
+	struct mii_dev *bus;
+	int ret;
+
+	setup_iomux_enet();
+
+	iomuxc_set_rgmii_io_voltage(DDR_SEL_1P5V_IO);
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	bus = fec_get_miibus(IMX_FEC_BASE, -1);
+	if (!bus)
+		return -ENODEV;
+
+	/*
+	 * We use here the "rgmii-id" mode of operation and allow M88E1512
+	 * PHY to use its internally callibrated RX/TX delays
+	 */
+	phydev = phy_find_by_mask(bus, 0xffffffff /* (0xf << 4) */,
+				  PHY_INTERFACE_MODE_RGMII_ID);
+	if (!phydev) {
+		ret = -ENODEV;
+		goto err_phy;
+	}
+
+	/* display5 due to PCB routing can only work with 100 Mbps */
+	phydev->advertising &= ~(ADVERTISED_1000baseX_Half |
+				 ADVERTISED_1000baseX_Full |
+				 SUPPORTED_1000baseT_Half |
+				 SUPPORTED_1000baseT_Full);
+
+	ret  = fec_probe(bd, -1, IMX_FEC_BASE, bus, phydev);
+	if (ret)
+		goto err_sw;
+
+	return 0;
+
+err_sw:
+	free(phydev);
+err_phy:
+	mdio_unregister(bus);
+	free(bus);
+	return ret;
+}
+#endif /* CONFIG_FEC_MXC */
+
+/*
+ * Do not overwrite the console
+ * Always use serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	fdt_fixup_ethernet(blob);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	debug("board init\n");
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Setup iomux for non console UARTS */
+	displ5_set_iomux_uart();
+
+	displ5_setup_ecspi();
+
+	SETUP_IOMUX_PADS(misc_pads);
+
+	get_board_id(gpio_table_sw_ids, &gpio_table_sw_ids_names[0],
+		     ARRAY_SIZE(gpio_table_sw_ids), &sw_ids_valid, &unit_id);
+	debug("SWx unit_id 0x%x\n", unit_id);
+
+	get_board_id(gpio_table_hw_ids, &gpio_table_hw_ids_names[0],
+		     ARRAY_SIZE(gpio_table_hw_ids), &hw_ids_valid, &cpu_id);
+	debug("HWx cpu_id 0x%x\n", cpu_id);
+
+	if (hw_ids_valid && sw_ids_valid)
+		printf("ID:    unit type 0x%x rev 0x%x\n", unit_id, cpu_id);
+
+	udelay(25);
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* eMMC, USDHC-4, 8-bit bus width */
+	/* SPI-NOR, ECSPI-2 SS0, 3-bytes addressing */
+	{"emmc",    MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{"spinor",  MAKE_CFGVAL(0x30, 0x00, 0x00, 0x09)},
+	{NULL,	0},
+};
+
+static void setup_boot_modes(void)
+{
+	add_board_boot_modes(board_boot_modes);
+}
+#else
+static inline void setup_boot_modes(void) {}
+#endif
+
+int misc_init_r(void)
+{
+	setup_boot_modes();
+	return 0;
+}
+
+static struct mxc_serial_platdata mxc_serial_plat = {
+	.reg = (struct mxc_uart *)UART5_BASE,
+};
+
+U_BOOT_DEVICE(mxc_serial) = {
+	.name = "serial_mxc",
+	.platdata = &mxc_serial_plat,
+};

board/liebherr/display5/spl.c

@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2017 DENX Software Engineering
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <libfdt.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include "asm/arch/crm_regs.h"
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/imx-regs.h>
+#include "asm/arch/iomux.h"
+#include <asm/mach-imx/iomux-v3.h>
+#include <environment.h>
+#include <fsl_esdhc.h>
+#include <netdev.h>
+#include "common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdclk_1 = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_reset = 0x00000030,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = 0x00000030,
+	.dram_sdodt1 = 0x00000030,
+
+	.dram_sdqs0 = 0x00000030,
+	.dram_sdqs1 = 0x00000030,
+	.dram_sdqs2 = 0x00000030,
+	.dram_sdqs3 = 0x00000030,
+	.dram_sdqs4 = 0x00000030,
+	.dram_sdqs5 = 0x00000030,
+	.dram_sdqs6 = 0x00000030,
+	.dram_sdqs7 = 0x00000030,
+
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_dqm2 = 0x00000030,
+	.dram_dqm3 = 0x00000030,
+	.dram_dqm4 = 0x00000030,
+	.dram_dqm5 = 0x00000030,
+	.dram_dqm6 = 0x00000030,
+	.dram_dqm7 = 0x00000030,
+};
+
+static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_b2ds = 0x00000030,
+	.grp_b3ds = 0x00000030,
+	.grp_b4ds = 0x00000030,
+	.grp_b5ds = 0x00000030,
+	.grp_b6ds = 0x00000030,
+	.grp_b7ds = 0x00000030,
+};
+
+/* 4x128Mx16.cfg */
+static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x002D0028,
+	.p0_mpwldectrl1 = 0x0032002D,
+	.p1_mpwldectrl0 = 0x00210036,
+	.p1_mpwldectrl1 = 0x0019002E,
+	.p0_mpdgctrl0 = 0x4349035C,
+	.p0_mpdgctrl1 = 0x0348033D,
+	.p1_mpdgctrl0 = 0x43550362,
+	.p1_mpdgctrl1 = 0x03520316,
+	.p0_mprddlctl = 0x41393940,
+	.p1_mprddlctl = 0x3F3A3C47,
+	.p0_mpwrdlctl = 0x413A423A,
+	.p1_mpwrdlctl = 0x4042483E,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
+static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC3F, &ccm->CCGR1);
+	writel(0x0FFFCFC0, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void spl_dram_init(void)
+{
+	struct mx6_ddr_sysinfo sysinfo = {
+		/* width of data bus:0=16,1=32,2=64 */
+		.dsize = 2,
+		/* config for full 4GB range so that get_mem_size() works */
+		.cs_density = 32, /* 32Gb per CS */
+		/* single chip select */
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
+		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
+		.walat = 1,	/* Write additional latency */
+		.ralat = 5,	/* Read additional latency */
+		.mif3_mode = 3,	/* Command prediction working mode */
+		.bi_on = 1,	/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
+		.ddr_type = DDR_TYPE_DDR3,
+		.refsel = 1,	/* Refresh cycles at 32KHz */
+		.refr = 7,	/* 8 refresh commands per refresh cycle */
+	};
+
+	mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
+}
+
+#ifdef CONFIG_SPL_SPI_SUPPORT
+static void displ5_init_ecspi(void)
+{
+	displ5_set_iomux_ecspi_spl();
+	enable_spi_clk(1, 1);
+}
+#else
+static inline void displ5_init_ecspi(void) { }
+#endif
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static struct fsl_esdhc_cfg usdhc_cfg = {
+	.esdhc_base = USDHC4_BASE_ADDR,
+	.max_bus_width = 8,
+};
+
+int board_mmc_init(bd_t *bd)
+{
+	displ5_set_iomux_usdhc_spl();
+
+	usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+	gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
+
+	return fsl_esdhc_initialize(bd, &usdhc_cfg);
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	arch_cpu_init();
+
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	displ5_set_iomux_uart_spl();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	displ5_init_ecspi();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	/* Default boot sequence SPI -> MMC */
+	spl_boot_list[0] = spl_boot_device();
+	spl_boot_list[1] = BOOT_DEVICE_MMC1;
+	spl_boot_list[2] = BOOT_DEVICE_UART;
+	spl_boot_list[3] = BOOT_DEVICE_NONE;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	/* 'fastboot' */
+	const char *s;
+
+	env_init();
+	env_load();
+
+	s = env_get("BOOT_FROM");
+	if (s && strcmp(s, "ACTIVE") == 0) {
+		spl_boot_list[0] = BOOT_DEVICE_MMC1;
+		spl_boot_list[1] = spl_boot_device();
+	}
+#endif
+}
+
+void reset_cpu(ulong addr) {}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
+int spl_start_uboot(void)
+{
+	/* break into full u-boot on 'c' */
+	if (serial_tstc() && serial_getc() == 'c')
+		return 1;
+
+#ifdef CONFIG_SPL_ENV_SUPPORT
+	if (env_get_yesno("boot_os") != 1)
+		return 1;
+#endif
+	return 0;
+}
+#endif

board/nvidia/p2771-0000/MAINTAINERS

@@ -3,4 +3,5 @@ M:	Stephen Warren <swarren@nvidia.com>
 S:	Maintained
 F:	board/nvidia/p2771-0000/
 F:	include/configs/p2771-0000.h
-F:	configs/p2771-0000_defconfig
+F:	configs/p2771-0000-000_defconfig
+F:	configs/p2771-0000-500_defconfig

board/phytec/pcm052/MAINTAINERS

@@ -2,5 +2,7 @@ PCM052 BOARD
 M:	Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
 S:	Maintained
 F:	board/phytec/pcm052/
+F:	include/configs/bk4r1.h
 F:	include/configs/pcm052.h
+F:	configs/bk4r1_defconfig
 F:	configs/pcm052_defconfig

board/renesas/blanche/MAINTAINERS

@@ -0,0 +1,7 @@
+BLANCHE BOARD
+M:	Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com>
+S:	Maintained
+F:	board/renesas/blanche/
+F:	include/configs/blanche.h
+F:	configs/blanche_defconfig
+

board/rockchip/evb_rk3399/MAINTAINERS

@@ -4,3 +4,4 @@ S:      Maintained
 F:      board/rockchip/evb_rk3399
 F:      include/configs/evb_rk3399.h
 F:      configs/evb-rk3399_defconfig
+F:      configs/firefly-rk3399_defconfig

board/samsung/espresso7420/MAINTAINERS

@@ -3,3 +3,4 @@ M:	Thomas Abraham <thomas.ab@samsung.com>
 S:	Maintained
 F:	board/samsung/espresso7420/
 F:	include/configs/espresso7420.h
+F:	configs/espresso7420_defconfig

board/st/stih410-b2260/Makefile

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2017
-# Patrice Chotard, <patrice.chotard@st.com>
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

board/st/stih410-b2260/board.c

@@ -1,7 +1,6 @@
 /*
- * Board init file for STiH410-B2260
- *
- * (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

board/st/stm32f746-disco/Makefile

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2016
-# Vikas Manocha <vikas.manocha@st.com>
+# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

board/st/stm32f746-disco/stm32f746-disco.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2016
- * Vikas Manocha, <vikas.manocha@st.com>
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

board/st/stm32h743-disco/Makefile

@@ -1,6 +1,6 @@
 #
-# Copyright (C) STMicroelectronics SA 2017
-# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.#
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

board/st/stm32h743-disco/stm32h743-disco.c

@@ -1,6 +1,6 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

board/st/stm32h743-eval/Makefile

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2017
-# Patrice Chotard, <patrice.chotard@st.com>
+# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

board/st/stm32h743-eval/stm32h743-eval.c

@@ -1,6 +1,6 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

board/st/stv0991/Makefile

@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2014
-# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
+# Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #

board/st/stv0991/stv0991.c

@@ -1,6 +1,6 @@
 /*
- * (C) Copyright 2014
- * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
+ * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

board/sunxi/MAINTAINERS

@@ -26,6 +26,7 @@ F:	configs/A13-OLinuXinoM_defconfig
 F:	configs/Auxtek-T003_defconfig
 F:	configs/Auxtek-T004_defconfig
 F:	configs/CHIP_defconfig
+F:	configs/CHIP_pro_defconfig
 F:	configs/difrnce_dit4350_defconfig
 F:	configs/Empire_electronix_d709_defconfig
 F:	configs/Empire_electronix_m712_defconfig
@@ -44,6 +45,7 @@ F:	configs/Mele_M9_defconfig
 F:	configs/Sinovoip_BPI_M2_defconfig
 F:	include/configs/sun7i.h
 F:	configs/A20-OLinuXino_MICRO_defconfig
+F:	configs/A20-OLinuXino_MICRO-eMMC_defconfig
 F:	configs/Bananapi_defconfig
 F:	configs/Bananapro_defconfig
 F:	configs/i12-tvbox_defconfig
@@ -54,6 +56,7 @@ F:	configs/Orangepi_mini_defconfig
 F:	configs/qt840a_defconfig
 F:	configs/Wits_Pro_A20_DKT_defconfig
 F:	include/configs/sun8i.h
+F:	configs/sun8i_a23_evb_defconfig
 F:	configs/ga10h_v1_1_defconfig
 F:	configs/gt90h_v4_defconfig
 F:	configs/inet86dz_defconfig
@@ -129,6 +132,12 @@ S:	Maintained
 F:	configs/Bananapi_M2_Ultra_defconfig
 F:	arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
 
+BANANAPI M2 MAGIC BOARD
+M:	Maxime Ripard <maxime.ripard@free-electrons.com>
+S:	Maintained
+F:	configs/Bananapi_m2m_defconfig
+F:	arch/arm/dts/sun8i-r16-bananapi-m2m.dts
+
 BANANAPI M64
 M:	Jagan Teki <jagan@amarulasolutions.com>
 S:	Maintained

board/sunxi/board.c

@@ -217,6 +217,8 @@ int board_init(void)
 	satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
 	gpio_request(satapwr_pin, "satapwr");
 	gpio_direction_output(satapwr_pin, 1);
+	/* Give attached sata device time to power-up to avoid link timeouts */
+	mdelay(500);
 #endif
 #ifdef CONFIG_MACPWR
 	macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);

board/udoo/udoo.c

@@ -245,8 +245,7 @@ int board_init(void)
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #ifdef CONFIG_SATA
-	if (is_cpu_type(MXC_CPU_MX6Q))
-		setup_sata();
+	setup_sata();
 #endif
 	return 0;
 }

board/wandboard/spl.c

@@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define IMX6DQ_DRIVE_STRENGTH		0x30
 #define IMX6SDL_DRIVE_STRENGTH		0x28
+#define IMX6QP_DRIVE_STRENGTH		0x28
 
 /* configure MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
@@ -63,6 +64,36 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 };
 
+/* configure MX6QP mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_cas = IMX6QP_DRIVE_STRENGTH,
+	.dram_ras = IMX6QP_DRIVE_STRENGTH,
+	.dram_reset = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6QP_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6QP_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
+};
+
 /* configure MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
@@ -81,6 +112,24 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 };
 
+/* configure MX6QP mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6QP_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6QP_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6QP_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6QP_DRIVE_STRENGTH,
+};
+
 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
@@ -260,15 +309,87 @@ static void ccgr_init(void)
 	writel(0x00C03F3F, &ccm->CCGR0);
 	writel(0x0030FC03, &ccm->CCGR1);
 	writel(0x0FFFC000, &ccm->CCGR2);
-	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x3FF03000, &ccm->CCGR3);
 	writel(0x00FFF300, &ccm->CCGR4);
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003FF, &ccm->CCGR6);
 }
 
+static void spl_dram_init_imx6qp_lpddr3(void)
+{
+	/* MMDC0_MDSCR set the Configuration request bit during MMDC set up */
+	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+	/* Calibrations - ZQ */
+	writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800);
+	/* write leveling */
+	writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c);
+	writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810);
+	writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c);
+	writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810);
+	/*
+	 * DQS gating, read delay, write delay calibration values
+	 * based on calibration compare of 0x00ffff00
+	 */
+	writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c);
+	writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840);
+	writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c);
+	writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840);
+	writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848);
+	writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848);
+	writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850);
+	writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824);
+	writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824);
+	writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828);
+	writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0);
+	writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0);
+	writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8);
+	writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8);
+	/* MMDC init: in DDR3, 64-bit mode, only MMDC0 is initiated */
+	writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004);
+	writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008);
+	writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c);
+	writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010);
+	writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014);
+	writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018);
+	writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c);
+	writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030);
+	writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040);
+	writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400);
+	writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000);
+	writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890);
+	/* add NOC DDR configuration */
+	writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008);
+	writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c);
+	writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038);
+	writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014);
+	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028);
+	writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c);
+	writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c);
+	writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020);
+	writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818);
+	writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818);
+	writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004);
+	writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404);
+	writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c);
+}
+
 static void spl_dram_init(void)
 {
-	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+	if (is_mx6dqp()) {
+		mx6dq_dram_iocfg(64, &mx6qp_ddr_ioregs, &mx6qp_grp_ioregs);
+		spl_dram_init_imx6qp_lpddr3();
+	} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
 		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 		mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
 	} else if (is_cpu_type(MXC_CPU_MX6DL)) {

board/wandboard/wandboard.c

@@ -435,9 +435,7 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 #ifdef CONFIG_SATA
-	/* Only mx6q wandboard has SATA */
-	if (is_cpu_type(MXC_CPU_MX6Q))
-		setup_sata();
+	setup_sata();
 #endif
 
 	return 0;
@@ -512,7 +510,9 @@ int board_late_init(void)
 #endif
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (is_mx6dq())
+	if (is_mx6dqp())
+		env_set("board_rev", "MX6QP");
+	else if (is_mx6dq())
 		env_set("board_rev", "MX6Q");
 	else
 		env_set("board_rev", "MX6DL");
@@ -534,7 +534,7 @@ int board_init(void)
 
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
-	if (is_mx6dq()) {
+	if (is_mx6dq() || is_mx6dqp()) {
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
 	} else {

cmd/Kconfig

@@ -1404,13 +1404,14 @@ config CMD_MTDPARTS
 
 config MTDIDS_DEFAULT
 	string "Default MTD IDs"
-	depends on CMD_MTDPARTS
+	depends on CMD_MTDPARTS || CMD_NAND || CMD_FLASH
 	help
-	  Defines a default MTD ID
+	  Defines a default MTD IDs list for use with MTD partitions in the
+	  Linux MTD command line partitions format.
 
 config MTDPARTS_DEFAULT
 	string "Default MTD partition scheme"
-	depends on CMD_MTDPARTS
+	depends on CMD_MTDPARTS || CMD_NAND || CMD_FLASH
 	help
 	  Defines a default MTD partitioning scheme in the Linux MTD command
 	  line partitions format