mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
6c12873824
The original PolarFire SoC mailbox devicetree bindings described the control/status and interrupt registers as standalone reg regions of the mailbox device. This was incorrect, as these registers are shared system control blocks and should instead be modeled as syscon devices. Linux has since corrected this by introducing syscon-based bindings for the MPFS mailbox and updating the mailbox driver to access the control and interrupt registers via syscon/regmap. U-Boot, however, continued to expect the legacy binding, causing mailbox access to fail when using Linux-aligned devicetrees. Update the U-Boot MPFS mailbox driver to support the new syscon-based bindings by resolving the control and sysreg syscon nodes and accessing the registers through regmap. Support for the legacy mailbox binding is retained for backwards compatibility with existing firmware-provided devicetrees. This brings the U-Boot mailbox driver in line with the corrected hardware description and matches the behavior of the Linux mailbox driver. Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
89 lines
3.1 KiB
Plaintext
89 lines
3.1 KiB
Plaintext
menu "Mailbox Controller Support"
|
|
|
|
config DM_MAILBOX
|
|
bool "Enable mailbox controllers using Driver Model"
|
|
depends on DM && OF_CONTROL
|
|
help
|
|
Enable support for the mailbox driver class. Mailboxes provide the
|
|
ability to transfer small messages and/or notifications from one
|
|
CPU to another CPU, or sometimes to dedicated HW modules. They form
|
|
the basis of a variety of inter-process/inter-CPU communication
|
|
protocols.
|
|
|
|
config APPLE_MBOX
|
|
bool "Enable Apple IOP controller support"
|
|
depends on DM_MAILBOX && ARCH_APPLE
|
|
default y
|
|
help
|
|
Enable support for the mailboxes that provide a comminucation
|
|
channel with Apple IOP controllers integrated on Apple SoCs.
|
|
These IOP controllers are used to implement various functions
|
|
such as the System Management Controller (SMC) and NVMe and this
|
|
driver is required to get that functionality up and running.
|
|
|
|
config IMX_MU_MBOX
|
|
bool "Enable i.MX MU MBOX support"
|
|
depends on DM_MAILBOX
|
|
help
|
|
Enable support for i.MX Messaging Unit for communication with other
|
|
processors on the SoC using mailbox interface
|
|
|
|
config MPFS_MBOX
|
|
bool "Enable MPFS system controller support"
|
|
depends on DM_MAILBOX && ARCH_RV64I
|
|
select DEVRES
|
|
depends on SYSCON
|
|
depends on REGMAP
|
|
help
|
|
Enable support for the mailboxes that provide a communication
|
|
channel with the system controller integrated on PolarFire SoC.
|
|
|
|
config SANDBOX_MBOX
|
|
bool "Enable the sandbox mailbox test driver"
|
|
depends on DM_MAILBOX && SANDBOX
|
|
help
|
|
Enable support for a test mailbox implementation, which simply echos
|
|
back a modified version of any message that is sent.
|
|
|
|
config TEGRA_HSP
|
|
bool "Enable Tegra HSP controller support"
|
|
depends on DM_MAILBOX && ARCH_TEGRA
|
|
help
|
|
This enables support for the NVIDIA Tegra HSP Hw module, which
|
|
implements doorbells, mailboxes, semaphores, and shared interrupts.
|
|
|
|
config STM32_IPCC
|
|
bool "Enable STM32 IPCC controller support"
|
|
depends on DM_MAILBOX && ARCH_STM32MP
|
|
help
|
|
This enables support for the STM32MP IPCC Hw module, which
|
|
implements doorbells between 2 processors.
|
|
|
|
config K3_SEC_PROXY
|
|
bool "Texas Instruments K3 Secure Proxy Driver"
|
|
depends on DM_MAILBOX && ARCH_K3
|
|
help
|
|
An implementation of Secure proxy slave driver for K3 SoCs from
|
|
Texas Instruments. Secure proxy is a communication entity mainly
|
|
used for communication between multiple processors with the SoC.
|
|
Select this driver if your platform has support for this hardware
|
|
block.
|
|
|
|
config RCAR_MFIS_MBOX
|
|
bool "Renesas MFIS Multifunctional Interface mailbox driver"
|
|
depends on DM_MAILBOX && ARCH_RENESAS
|
|
help
|
|
This enables support for the Renesas MFIS mailbox module, which
|
|
provides an interface between the different CPU Cores, such as AP
|
|
System Core domain and the Realtime Core domain, SCP Core domain
|
|
and AP System Core domain or Realtime Core domain and AP System
|
|
Core domain or Realtime Core domain.
|
|
|
|
config ZYNQMP_IPI
|
|
bool "Xilinx ZynqMP IPI controller support"
|
|
depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2)
|
|
help
|
|
This enables support for the Xilinx ZynqMP Inter Processor Interrupt
|
|
communication controller.
|
|
endmenu
|