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https://source.denx.de/u-boot/u-boot.git
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8c1ffb09d5
At this point there are no users of this driver which do not enable DM_RTC, so remove the legacy code and express the depdendency in Kconfig. We can further remove code related to RTC chips / options that are neither available in Kconfig nor set by any platforms. Signed-off-by: Tom Rini <trini@konsulko.com>
161 lines
4.4 KiB
C
161 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2001-2008
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* Copyright 2020 NXP
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Keith Outwater, keith_outwater@mvis.com`
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*/
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/*
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* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
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* DS1337 Real Time Clock (RTC).
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*/
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#include <config.h>
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#include <command.h>
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#include <dm.h>
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#include <log.h>
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#include <rtc.h>
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#include <i2c.h>
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/*
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* RTC register addresses
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*/
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#define RTC_SEC_REG_ADDR 0x0
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#define RTC_MIN_REG_ADDR 0x1
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#define RTC_HR_REG_ADDR 0x2
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#define RTC_DAY_REG_ADDR 0x3
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#define RTC_DATE_REG_ADDR 0x4
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#define RTC_MON_REG_ADDR 0x5
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#define RTC_YR_REG_ADDR 0x6
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#define RTC_CTL_REG_ADDR 0x0e
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#define RTC_STAT_REG_ADDR 0x0f
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#define RTC_TC_REG_ADDR 0x10
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/*
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* RTC control register bits
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*/
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#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
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#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
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#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
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#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
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#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
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#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
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/*
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* RTC status register bits
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*/
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#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
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#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
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#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
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static uchar rtc_read(struct udevice *dev, uchar reg)
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{
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return dm_i2c_reg_read(dev, reg);
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}
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static void rtc_write(struct udevice *dev, uchar reg, uchar val)
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{
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dm_i2c_reg_write(dev, reg, val);
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}
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static int ds1337_rtc_get(struct udevice *dev, struct rtc_time *tmp)
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{
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int rel = 0;
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uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
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control = rtc_read(dev, RTC_CTL_REG_ADDR);
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status = rtc_read(dev, RTC_STAT_REG_ADDR);
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sec = rtc_read(dev, RTC_SEC_REG_ADDR);
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min = rtc_read(dev, RTC_MIN_REG_ADDR);
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hour = rtc_read(dev, RTC_HR_REG_ADDR);
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wday = rtc_read(dev, RTC_DAY_REG_ADDR);
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mday = rtc_read(dev, RTC_DATE_REG_ADDR);
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mon_cent = rtc_read(dev, RTC_MON_REG_ADDR);
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year = rtc_read(dev, RTC_YR_REG_ADDR);
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debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x\n",
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year, mon_cent, mday, wday);
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debug("hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
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hour, min, sec, control, status);
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if (status & RTC_STAT_BIT_OSF) {
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printf("### Warning: RTC oscillator has stopped\n");
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/* clear the OSF flag */
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rtc_write(dev, RTC_STAT_REG_ADDR,
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rtc_read(dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
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rel = -1;
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}
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tmp->tm_sec = bcd2bin(sec & 0x7F);
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tmp->tm_min = bcd2bin(min & 0x7F);
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tmp->tm_hour = bcd2bin(hour & 0x3F);
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tmp->tm_mday = bcd2bin(mday & 0x3F);
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tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
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tmp->tm_year = bcd2bin(year) + ((mon_cent & 0x80) ? 2000 : 1900);
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tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
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tmp->tm_yday = 0;
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tmp->tm_isdst = 0;
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debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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return rel;
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}
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static int ds1337_rtc_set(struct udevice *dev, const struct rtc_time *tmp)
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{
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uchar century;
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debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
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tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
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tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
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rtc_write(dev, RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
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century = (tmp->tm_year >= 2000) ? 0x80 : 0;
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rtc_write(dev, RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon) | century);
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rtc_write(dev, RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
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rtc_write(dev, RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
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rtc_write(dev, RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
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rtc_write(dev, RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
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rtc_write(dev, RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
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return 0;
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}
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#ifdef CONFIG_RTC_DS1337_NOOSC
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#define RTC_DS1337_RESET_VAL \
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(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
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#else
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#define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
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#endif
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static int ds1337_rtc_reset(struct udevice *dev)
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{
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rtc_write(dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
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return 0;
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}
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static const struct rtc_ops ds1337_rtc_ops = {
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.get = ds1337_rtc_get,
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.set = ds1337_rtc_set,
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.reset = ds1337_rtc_reset,
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};
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static const struct udevice_id ds1337_rtc_ids[] = {
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{ .compatible = "ds1337" },
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{ .compatible = "ds1338" },
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{ .compatible = "ds1339" },
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{ }
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};
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U_BOOT_DRIVER(rtc_ds1337) = {
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.name = "rtc-ds1337",
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.id = UCLASS_RTC,
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.of_match = ds1337_rtc_ids,
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.ops = &ds1337_rtc_ops,
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};
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