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4f7057962d
Provide support for Tegra watchdog functionality. The WATCHDOG index 0 in conjunction with TIMER 5 is used inline with existing Linux kernel driver. Signed-off-by: Lukasz Majewski <lukma@nabladev.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* NVIDIA Tegra Watchdog driver
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*
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* Copyright (C) 2025 NABLA Software Engineering
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* Lukasz Majewski, NABLA Software Engineering, lukma@nabladev.com
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*/
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#include <dm.h>
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#include <wdt.h>
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#include <hang.h>
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#include <asm/io.h>
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#include <watchdog.h>
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/* Timer registers */
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#define TIMER_PTV 0x0
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#define TIMER_EN BIT(31)
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#define TIMER_PERIODIC BIT(30)
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/* WDT registers */
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#define WDT_CFG 0x0
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#define WDT_CFG_PERIOD_SHIFT 4
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#define WDT_CFG_PERIOD_MASK GENMASK(7, 0)
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#define WDT_CFG_INT_EN BIT(12)
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#define WDT_CFG_PMC2CAR_RST_EN BIT(15)
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#define WDT_CMD 0x8
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#define WDT_CMD_START_COUNTER BIT(0)
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#define WDT_CMD_DISABLE_COUNTER BIT(1)
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#define WDT_UNLOCK 0xc
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#define WDT_UNLOCK_PATTERN 0xc45a
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/* Use watchdog ID 0 */
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#define WDT_BASE 0x100
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/* Use Timer 5 as WDT counter */
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#define WDT_TIMER_BASE 0x60
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#define WDT_TIMER_ID 5
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struct tegra_wdt_priv {
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void __iomem *wdt_base;
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void __iomem *tmr_base;
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};
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static int tegra_wdt_reset(struct udevice *dev)
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{
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struct tegra_wdt_priv *priv = dev_get_priv(dev);
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writel(WDT_CMD_START_COUNTER, priv->wdt_base + WDT_CMD);
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return 0;
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}
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static int tegra_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct tegra_wdt_priv *priv = dev_get_priv(dev);
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u32 timeout_sec = timeout / 1000;
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/* Support for timeout from 1 to 255 seconds */
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if (timeout_sec < 1 || timeout_sec > 255)
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return -EINVAL;
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/*
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* Timer for WDT has a fixed 1MHz clock, so for 1 second period one
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* shall write 1000000ul.
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*
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* On Tegra the watchdog reset actually occurs on the 4th expiration
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* of this counter, so we set the period to 1/4.
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*/
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writel(TIMER_EN | TIMER_PERIODIC | (1000000ul / 4),
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priv->tmr_base + TIMER_PTV);
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writel(WDT_CFG_PMC2CAR_RST_EN | (timeout_sec << WDT_CFG_PERIOD_SHIFT) |
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WDT_TIMER_ID, priv->wdt_base + WDT_CFG);
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writel(WDT_CMD_START_COUNTER, priv->wdt_base + WDT_CMD);
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return 0;
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}
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static int tegra_wdt_stop(struct udevice *dev)
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{
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struct tegra_wdt_priv *priv = dev_get_priv(dev);
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writel(WDT_UNLOCK_PATTERN, priv->wdt_base + WDT_UNLOCK);
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writel(WDT_CMD_DISABLE_COUNTER, priv->wdt_base + WDT_CMD);
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writel(0, priv->tmr_base + TIMER_PTV);
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return 0;
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}
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static int tegra_wdt_probe(struct udevice *dev)
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{
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struct tegra_wdt_priv *priv = dev_get_priv(dev);
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void __iomem *base;
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base = dev_read_addr_ptr(dev);
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if (!base)
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return -ENOENT;
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priv->wdt_base = base + WDT_BASE;
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priv->tmr_base = base + WDT_TIMER_BASE;
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return 0;
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}
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static const struct wdt_ops tegra_wdt_ops = {
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.start = tegra_wdt_start,
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.stop = tegra_wdt_stop,
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.reset = tegra_wdt_reset,
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};
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U_BOOT_DRIVER(tegra_wdt) = {
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.name = "tegra_wdt",
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.id = UCLASS_WDT,
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.probe = tegra_wdt_probe,
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.ops = &tegra_wdt_ops,
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.priv_auto = sizeof(struct tegra_wdt_priv),
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};
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