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0b97991fa0
Peripheral registers on MPC83xx-series chips are declared in immap_83xx.h as a set of structs that ultimately fill the entire MMIO space of 1 MiB. This patch introduces a compile-time check of the size of each peripheral struct. The purpose of these checks is two-fold: 1. To quickly tell readers of the code the total size of each struct 2. To verify that the size does not change when a struct is edited If the size of a peripheral struct were to change by a few bytes due to an editing error, the result would be mayhem for all following peripherals, because all offsets would shift by the amount of the error. All new checks have been compile-tested. Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
84 lines
1.9 KiB
C
84 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Freescale I2C Controller
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*
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* Copyright 2006 Freescale Semiconductor, Inc.
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*
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* Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>,
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* Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com),
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* and Jeff Brown.
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* Some bits are taken from linux driver writen by adrian@humboldt.co.uk.
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*/
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#ifndef _ASM_FSL_I2C_H_
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#define _ASM_FSL_I2C_H_
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#include <asm/types.h>
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#include <linux/compiler.h>
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#include <linux/build_bug.h>
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typedef struct fsl_i2c_base {
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u8 adr; /* I2C slave address */
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u8 res0[3];
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#define I2C_ADR 0xFE
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#define I2C_ADR_SHIFT 1
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#define I2C_ADR_RES ~(I2C_ADR)
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u8 fdr; /* I2C frequency divider register */
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u8 res1[3];
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#define IC2_FDR 0x3F
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#define IC2_FDR_SHIFT 0
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#define IC2_FDR_RES ~(IC2_FDR)
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u8 cr; /* I2C control redister */
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u8 res2[3];
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#define I2C_CR_MEN 0x80
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#define I2C_CR_MIEN 0x40
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#define I2C_CR_MSTA 0x20
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#define I2C_CR_MTX 0x10
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#define I2C_CR_TXAK 0x08
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#define I2C_CR_RSTA 0x04
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#define I2C_CR_BIT6 0x02 /* required for workaround A004447 */
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#define I2C_CR_BCST 0x01
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u8 sr; /* I2C status register */
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u8 res3[3];
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#define I2C_SR_MCF 0x80
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#define I2C_SR_MAAS 0x40
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#define I2C_SR_MBB 0x20
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#define I2C_SR_MAL 0x10
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#define I2C_SR_BCSTM 0x08
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#define I2C_SR_SRW 0x04
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#define I2C_SR_MIF 0x02
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#define I2C_SR_RXAK 0x01
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u8 dr; /* I2C data register */
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u8 res4[3];
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#define I2C_DR 0xFF
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#define I2C_DR_SHIFT 0
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#define I2C_DR_RES ~(I2C_DR)
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u8 dfsrr; /* I2C digital filter sampling rate register */
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u8 res5[3];
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#define I2C_DFSRR 0x3F
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#define I2C_DFSRR_SHIFT 0
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#define I2C_DFSRR_RES ~(I2C_DR)
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/* Fill out the reserved block */
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u8 res6[0xE8];
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} fsl_i2c_t;
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static_assert(sizeof(fsl_i2c_t) == 0x100);
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct fsl_i2c_dev {
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struct fsl_i2c_base __iomem *base; /* register base */
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u32 i2c_clk;
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u32 index;
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u8 slaveadd;
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uint speed;
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};
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#endif
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#endif /* _ASM_I2C_H_ */
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