Patrick Delaunay 0cb1aa9409 stm32mp1: ram: increase the delay after reset to 128 cycles ...

Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

2019-05-23 11:38:10 +02:00

..

mediatek

ram: MediaTek: add DDR3 driver for MT7629 SoC

2018-11-28 23:04:53 -05:00

rockchip

rockchip: ram: rk3399: update for TPL

2019-05-08 17:34:12 +08:00

stm32mp1

stm32mp1: ram: increase the delay after reset to 128 cycles

2019-05-23 11:38:10 +02:00

bmips_ram.c

ram: bmips: Remove DM_FLAG_PRE_RELOC flag

2018-11-14 09:16:28 -08:00

k3-am654-ddrss.c

ram: Introduce K3 AM654 DDR Sub System driver

2018-11-16 16:51:58 -05:00

k3-am654-ddrss.h

ram: Introduce K3 AM654 DDR Sub System driver

2018-11-16 16:51:58 -05:00

Kconfig

ram: Introduce K3 AM654 DDR Sub System driver

2018-11-16 16:51:58 -05:00

Makefile

ram: MediaTek: add DDR3 driver for MT7629 SoC

2018-11-28 23:04:53 -05:00

mpc83xx_sdram.c

mpc83xx: Introduce ARCH_MPC837X

2019-05-20 13:50:34 +02:00

ram-uclass.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

sandbox_ram.c

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07 09:34:12 -04:00

stm32_sdram.c

ram: stm32_sdram: Adds stm32f429-disco fixes for HardFault at booting

2018-05-26 18:19:17 -04:00