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8b3f2eb7d8
Since commitf98cd471f0("clk: clk-composite: Resolve parent clock by name") the StarFive VisionFive 2 board fails to boot. Before that patch the SPL debug UART showed warnings like: clk_register: failed to get pll0_out device (parent of perh_root) clk_register: failed to get pll0_out device (parent of qspi_ref_src) clk_register: failed to get pll0_out device (parent of usb_125m) clk_register: failed to get pll0_out device (parent of gmac_src) clk_register: failed to get pll0_out device (parent of gmac1_gtxclk) clk_register: failed to get pll0_out device (parent of gmac0_gtxclk) The &pllclk clock needs to be enabled early. Fixes:f98cd471f0("clk: clk-composite: Resolve parent clock by name") Suggested-by: Marek Vasut <marex@denx.de> Tested-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>