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1b734e0190
Add pinctrl driver for the TLMM block found in the ipq9574 SoC. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250226064505.1178054-6-quic_varada@quicinc.com Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
227 lines
7.5 KiB
C
227 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* pinctrl driver for Qualcomm ipq9574
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*
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* (C) Copyright 2025 Linaro Ltd.
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*/
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#include <dm.h>
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#include "pinctrl-qcom.h"
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#define MAX_PIN_NAME_LEN 32
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static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
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enum ipq9574_functions {
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msm_mux_blsp0_spi,
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msm_mux_blsp0_uart,
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msm_mux_blsp1_i2c,
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msm_mux_blsp1_spi,
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msm_mux_blsp1_uart,
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msm_mux_blsp2_i2c,
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msm_mux_blsp2_spi,
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msm_mux_blsp2_uart,
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msm_mux_blsp3_i2c,
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msm_mux_blsp3_spi,
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msm_mux_blsp3_uart,
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msm_mux_blsp4_i2c,
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msm_mux_blsp4_spi,
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msm_mux_blsp4_uart,
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msm_mux_blsp5_i2c,
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msm_mux_blsp5_uart,
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msm_mux_gpio,
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msm_mux_mdc,
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msm_mux_mdio,
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msm_mux_pcie0_clk,
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msm_mux_pcie0_wake,
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msm_mux_pcie1_clk,
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msm_mux_pcie1_wake,
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msm_mux_pcie2_clk,
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msm_mux_pcie2_wake,
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msm_mux_pcie3_clk,
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msm_mux_pcie3_wake,
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msm_mux_qspi_data,
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msm_mux_qspi_clk,
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msm_mux_qspi_cs,
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msm_mux_sdc_data,
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msm_mux_sdc_clk,
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msm_mux_sdc_cmd,
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msm_mux_sdc_rclk,
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msm_mux_NA,
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};
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#define MSM_PIN_FUNCTION(fname) \
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[msm_mux_##fname] = {#fname, msm_mux_##fname}
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static const struct pinctrl_function msm_pinctrl_functions[] = {
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MSM_PIN_FUNCTION(blsp0_spi),
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MSM_PIN_FUNCTION(blsp0_uart),
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MSM_PIN_FUNCTION(blsp1_i2c),
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MSM_PIN_FUNCTION(blsp1_spi),
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MSM_PIN_FUNCTION(blsp1_uart),
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MSM_PIN_FUNCTION(blsp2_i2c),
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MSM_PIN_FUNCTION(blsp2_spi),
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MSM_PIN_FUNCTION(blsp2_uart),
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MSM_PIN_FUNCTION(blsp3_i2c),
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MSM_PIN_FUNCTION(blsp3_spi),
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MSM_PIN_FUNCTION(blsp3_uart),
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MSM_PIN_FUNCTION(blsp4_i2c),
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MSM_PIN_FUNCTION(blsp4_spi),
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MSM_PIN_FUNCTION(blsp4_uart),
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MSM_PIN_FUNCTION(blsp5_i2c),
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MSM_PIN_FUNCTION(blsp5_uart),
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MSM_PIN_FUNCTION(gpio),
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MSM_PIN_FUNCTION(mdc),
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MSM_PIN_FUNCTION(mdio),
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MSM_PIN_FUNCTION(pcie0_clk),
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MSM_PIN_FUNCTION(pcie0_wake),
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MSM_PIN_FUNCTION(pcie1_clk),
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MSM_PIN_FUNCTION(pcie1_wake),
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MSM_PIN_FUNCTION(pcie2_clk),
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MSM_PIN_FUNCTION(pcie2_wake),
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MSM_PIN_FUNCTION(pcie3_clk),
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MSM_PIN_FUNCTION(pcie3_wake),
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MSM_PIN_FUNCTION(qspi_data),
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MSM_PIN_FUNCTION(qspi_clk),
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MSM_PIN_FUNCTION(qspi_cs),
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MSM_PIN_FUNCTION(sdc_data),
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MSM_PIN_FUNCTION(sdc_clk),
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MSM_PIN_FUNCTION(sdc_cmd),
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MSM_PIN_FUNCTION(sdc_rclk),
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};
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typedef unsigned int msm_pin_function[10];
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#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
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[id] = { msm_mux_gpio, /* gpio mode */ \
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msm_mux_##f1, \
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msm_mux_##f2, \
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msm_mux_##f3, \
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msm_mux_##f4, \
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msm_mux_##f5, \
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msm_mux_##f6, \
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msm_mux_##f7, \
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msm_mux_##f8, \
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msm_mux_##f9, \
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}
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static const msm_pin_function ipq9574_pin_functions[] = {
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PINGROUP(0, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(1, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(2, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(3, sdc_data, qspi_data, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(4, sdc_cmd, qspi_cs, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(5, sdc_clk, qspi_clk, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(6, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(7, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(8, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(9, sdc_data, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(10, sdc_rclk, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(11, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(12, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(13, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(14, blsp0_spi, blsp0_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
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PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, NA, NA, NA, NA, NA, NA),
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PINGROUP(17, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(18, blsp3_spi, blsp3_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(19, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(20, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(21, blsp3_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(22, pcie0_clk, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(24, pcie0_wake, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(25, pcie1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(27, pcie1_wake, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(28, pcie2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(30, pcie2_wake, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(31, pcie3_clk, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(33, pcie3_wake, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
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PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, NA, NA, NA, NA, NA),
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PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
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PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, NA, NA, NA, NA, NA, NA),
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PINGROUP(38, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(39, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(48, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(49, blsp5_i2c, blsp5_uart, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
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PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, NA, NA, NA, NA, NA, NA),
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PINGROUP(52, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(53, blsp4_uart, blsp4_spi, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(61, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(62, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(63, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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PINGROUP(64, blsp1_spi, NA, NA, NA, NA, NA, NA, NA, NA),
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};
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static const char *ipq9574_get_function_name(struct udevice *dev,
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unsigned int selector)
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{
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return msm_pinctrl_functions[selector].name;
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}
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static const char *ipq9574_get_pin_name(struct udevice *dev,
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unsigned int selector)
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{
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snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
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return pin_name;
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}
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static int ipq9574_get_function_mux(unsigned int pin, unsigned int selector)
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{
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unsigned int i;
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const msm_pin_function *func = ipq9574_pin_functions + pin;
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for (i = 0; i < 10; i++)
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if ((*func)[i] == selector)
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return i;
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debug("Can't find requested function for pin:selector %u:%u\n",
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pin, selector);
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return -EINVAL;
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}
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static const struct msm_pinctrl_data ipq9574_data = {
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.pin_data = {
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.pin_count = 65,
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},
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.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
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.get_function_name = ipq9574_get_function_name,
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.get_function_mux = ipq9574_get_function_mux,
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.get_pin_name = ipq9574_get_pin_name,
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};
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static const struct udevice_id msm_pinctrl_ids[] = {
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{ .compatible = "qcom,ipq9574-tlmm", .data = (ulong)&ipq9574_data },
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{ /* Sentinal */ }
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};
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U_BOOT_DRIVER(pinctrl_ipq9574) = {
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.name = "pinctrl_ipq9574",
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.id = UCLASS_NOP,
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.of_match = msm_pinctrl_ids,
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.ops = &msm_pinctrl_ops,
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.bind = msm_pinctrl_bind,
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.flags = DM_FLAG_PRE_RELOC,
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};
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