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433a17aca1
The subclass_code member of the pci_ep_header structure is a 1-byte
field. The macro PCI_CLASS_MEMORY_RAM is a concetation of baseclass_code
and subclass_code as follows:
PCI_BASE_CLASS_MEMORY: 0x05
Subclass Code for RAM: 0x00
PCI_CLASS_MEMORY_RAM: 0x0500
Hence, instead of extracting it via an implicity type conversion from int
to u8 which throws a warning, explicitly mask the bits to extract the
subclass_code.
Fixes: cde77583cf ("spl: Add support for Device Firmware Upgrade (DFU) over PCIe")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tested-by: Anshul Dalal <anshuld@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Tested-by: Mattijs Korpershoek <mkorpershoek@kernel.org> # am62x_evm_a53
Link: https://lore.kernel.org/r/20260305103815.999886-1-s-vadapalli@ti.com
Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
148 lines
3.2 KiB
C
148 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016
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* Texas Instruments, <www.ti.com>
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*
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* Ravi B <ravibabu@ti.com>
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*/
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#include <env.h>
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#include <spl.h>
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#include <linux/compiler.h>
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#include <errno.h>
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#include <watchdog.h>
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#include <console.h>
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#include <g_dnl.h>
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#include <usb.h>
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#include <dfu.h>
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#include <linux/printk.h>
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#include <pci_ep.h>
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#include <dm/uclass.h>
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#include <cpu_func.h>
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#include <linux/io.h>
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/*
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* Macros define size of magic word and boot phase string
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* in bytes.
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*/
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#define MAGIC_WORD_SIZE 4
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#define BOOT_PHASE_STRING_SIZE 63
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static int run_dfu(int usb_index, char *interface, char *devstring)
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{
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int ret;
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ret = dfu_init_env_entities(interface, devstring);
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if (ret) {
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dfu_free_entities();
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goto exit;
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}
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run_usb_dnl_gadget(usb_index, "usb_dnl_dfu");
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exit:
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dfu_free_entities();
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return ret;
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}
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#ifdef CONFIG_SPL_PCI_DFU
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static int dfu_over_pcie(void)
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{
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u32 offset, magic_word;
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volatile void *addr;
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struct udevice *dev;
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struct pci_bar bar;
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struct pci_ep_header hdr;
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uint fn = 0;
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int ret;
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char *bootphase;
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uclass_get_device_by_seq(UCLASS_PCI_EP, 0, &dev);
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if (!dev) {
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pr_err("Failed to get pci ep device\n");
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return -ENODEV;
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}
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hdr.deviceid = CONFIG_SPL_PCI_DFU_DEVICE_ID;
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hdr.vendorid = CONFIG_SPL_PCI_DFU_VENDOR_ID;
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hdr.baseclass_code = PCI_BASE_CLASS_MEMORY;
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hdr.subclass_code = PCI_CLASS_MEMORY_RAM & 0xff;
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ret = pci_ep_write_header(dev, fn, &hdr);
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if (ret) {
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pr_err("Failed to write header: %d\n", ret);
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return ret;
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}
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bar.barno = BAR_0;
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bar.phys_addr = (dma_addr_t)CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS;
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bar.flags = PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_32 |
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PCI_BASE_ADDRESS_MEM_PREFETCH;
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bar.size = CONFIG_SPL_PCI_DFU_BAR_SIZE;
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ret = pci_ep_set_bar(dev, fn, &bar);
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if (ret) {
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pr_err("Failed to set bar: %d\n", ret);
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return ret;
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}
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ret = pci_ep_start(dev);
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if (ret) {
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pr_err("Failed to start ep: %d\n", ret);
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return ret;
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}
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addr = (void *)CONFIG_SPL_PCI_DFU_SPL_LOAD_FIT_ADDRESS;
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offset = CONFIG_SPL_PCI_DFU_BAR_SIZE - MAGIC_WORD_SIZE;
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if (sizeof(CONFIG_SPL_PCI_DFU_BOOT_PHASE) > BOOT_PHASE_STRING_SIZE) {
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pr_err("Not copying boot phase. String too long\n");
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} else {
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bootphase = (char *)(addr + CONFIG_SPL_PCI_DFU_BAR_SIZE -
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(BOOT_PHASE_STRING_SIZE + MAGIC_WORD_SIZE + 1));
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strlcpy(bootphase, CONFIG_SPL_PCI_DFU_BOOT_PHASE,
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sizeof(CONFIG_SPL_PCI_DFU_BOOT_PHASE) + 1);
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}
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addr = addr + offset;
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magic_word = CONFIG_SPL_PCI_DFU_MAGIC_WORD;
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(*(int *)addr) = 0;
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flush_dcache_all();
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for (;;) {
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if (*(int *)addr == magic_word)
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break;
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invalidate_dcache_all();
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}
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return 0;
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}
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#endif
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int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr)
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{
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char *str_env;
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int ret;
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#ifdef CONFIG_SPL_PCI_DFU
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if (spl_boot_device() == BOOT_DEVICE_PCIE)
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return dfu_over_pcie();
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#endif
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/* set default environment */
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env_set_default(NULL, 0);
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str_env = env_get(dfu_alt_info);
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if (!str_env) {
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pr_err("\"%s\" env variable not defined!\n", dfu_alt_info);
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return -EINVAL;
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}
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ret = env_set("dfu_alt_info", str_env);
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if (ret) {
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pr_err("unable to set env variable \"dfu_alt_info\"!\n");
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return -EINVAL;
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}
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/* invoke dfu command */
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return run_dfu(usbctrl, interface, devstr);
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}
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