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5416a3a306
Refactor system manager initialization by searching for system manager alias in Agilex5 device tree instead of manually passing node name to the device model calling function Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Intel Corporation <www.intel.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <hang.h>
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#include <spl.h>
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#include <asm/arch/base_addr_soc64.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <wdt.h>
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#include <dm/uclass.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 reset_flag(void)
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{
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/* Check rstmgr.stat for warm reset status */
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u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
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/* Check whether any L4 watchdogs or SDM had triggered warm reset */
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u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
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if (status & warm_reset_mask)
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return 0;
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return 1;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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struct udevice *dev;
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/* Enable Async */
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asm volatile("msr daifclr, #4");
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#ifdef CONFIG_SPL_BUILD
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spl_save_restore_data();
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#endif
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ret = spl_early_init();
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if (ret)
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hang();
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socfpga_get_sys_mgr_addr();
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socfpga_get_managers_addr();
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sysmgr_pinmux_init();
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/* Ensure watchdog is paused when debugging is happening */
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writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
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timer_init();
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mbox_init();
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mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
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ret = uclass_get_device(UCLASS_CLK, 0, &dev);
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if (ret) {
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debug("Clock init failed: %d\n", ret);
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hang();
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}
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/*
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* Enable watchdog as early as possible before initializing other
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* component. Watchdog need to be enabled after clock driver because
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* it will retrieve the clock frequency from clock driver.
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*/
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if (CONFIG_IS_ENABLED(WDT))
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initr_watchdog();
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preloader_console_init();
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print_reset_info();
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cm_print_clock_quick_summary();
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev);
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if (ret) {
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printf("HPS CCU settings init failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev);
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if (ret) {
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printf("HPS firewall settings init failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &dev);
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if (ret) {
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debug("PSS SRAM power-off failed: %d\n", ret);
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hang();
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}
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if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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hang();
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}
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}
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if (IS_ENABLED(CONFIG_CADENCE_QSPI))
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mbox_qspi_open();
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/* Enable non secure access to ocram */
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clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0));
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}
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