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[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git - Remove netc_timerX nodes from arch/arm/dts/imx943-u-boot.dtsi as they are now upstream - Move dts/upstream/include/dt-bindings/reset/bcm6318-reset.h to include/dt-bindings/reset/bcm6318-reset.h as upstream has removed this file as unused (but we use it). Signed-off-by: Tom Rini <trini@konsulko.com>
78 lines
2.0 KiB
YAML
78 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller on SM8450
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maintainers:
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- Konrad Dybcio <konradybcio@kernel.org>
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description: |
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Qualcomm graphics clock control module provides the clocks, resets and power
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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,kaanapali-gpucc.h
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include/dt-bindings/clock/qcom,milos-gpucc.h
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include/dt-bindings/clock/qcom,sar2130p-gpucc.h
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include/dt-bindings/clock/qcom,sm4450-gpucc.h
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/clock/qcom,sm8550-gpucc.h
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include/dt-bindings/reset/qcom,sm8450-gpucc.h
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include/dt-bindings/reset/qcom,sm8650-gpucc.h
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include/dt-bindings/reset/qcom,x1e80100-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,kaanapali-gpucc
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- qcom,milos-gpucc
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- qcom,sar2130p-gpucc
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- qcom,sm4450-gpucc
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- qcom,sm8450-gpucc
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- qcom,sm8475-gpucc
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- qcom,sm8550-gpucc
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- qcom,sm8650-gpucc
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- qcom,x1e80100-gpucc
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- qcom,x1p42100-gpucc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 main branch source
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- description: GPLL0 div branch source
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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clock-controller@3d90000 {
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compatible = "qcom,sm8450-gpucc";
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reg = <0 0x03d90000 0 0xa000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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};
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...
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