Files
u-boot/dts/upstream/Bindings/connector/pcie-m2-m-connector.yaml
Tom Rini 5d401bfbdf Subtree merge tag 'v7.0-dts' of dts repo [1] into dts/upstream
[1] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git

- Remove netc_timerX nodes from arch/arm/dts/imx943-u-boot.dtsi as they
  are now upstream
- Move dts/upstream/include/dt-bindings/reset/bcm6318-reset.h to
  include/dt-bindings/reset/bcm6318-reset.h as upstream has removed this
  file as unused (but we use it).

Signed-off-by: Tom Rini <trini@konsulko.com>
2026-04-20 11:43:11 -06:00

146 lines
4.4 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe M.2 Mechanical Key M Connector
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
description:
A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M
connector. The Mechanical Key M connectors are used to connect SSDs to the
host system over PCIe/SATA interfaces. These connectors also offer optional
interfaces like USB, SMBus.
properties:
compatible:
const: pcie-m2-m-connector
vpcie3v3-supply:
description: A phandle to the regulator for 3.3v supply.
vpcie1v8-supply:
description: A phandle to the regulator for VIO 1.8v supply.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: OF graph bindings modeling the interfaces exposed on the
connector. Since a single connector can have multiple interfaces, every
interface has an assigned OF graph port number as described below.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: PCIe interface
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: SATA interface
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: USB 2.0 interface
anyOf:
- required:
- port@0
- required:
- port@1
i2c-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: I2C interface
clocks:
description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
more details.
maxItems: 1
pedet-gpios:
description: GPIO input to PEDET signal. This signal is used by the host
systems to determine the communication protocol that the M.2 card uses;
SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2
Specification r4.0, sec 3.3.4.2 for more details.
maxItems: 1
viocfg-gpios:
description: GPIO input to IO voltage configuration (VIO_CFG) signal. This
signal is used by the host systems to determine whether the card supports
an independent IO voltage domain for the sideband signals or not. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
maxItems: 1
pwrdis-gpios:
description: GPIO output to Power Disable (PWRDIS) signal. This signal is
used by the host system to disable power on the M.2 card. Refer, PCI
Express M.2 Specification r4.0, sec 3.3.5.2 for more details.
maxItems: 1
pln-gpios:
description: GPIO output to Power Loss Notification (PLN#) signal. This
signal is used by the host system to notify the M.2 card that the power
loss event is about to occur. Refer, PCI Express M.2 Specification r4.0,
sec 3.2.17.1 for more details.
maxItems: 1
plas3-gpios:
description: GPIO input to Power Loss Acknowledge (PLA_S3#) signal. This
signal is used by the host system to receive the acknowledgment of the M.2
card's preparation for power loss.
maxItems: 1
required:
- compatible
- vpcie3v3-supply
additionalProperties: false
examples:
# PCI M.2 Key M connector for SSDs with PCIe interface
- |
#include <dt-bindings/gpio/gpio.h>
connector {
compatible = "pcie-m2-m-connector";
vpcie3v3-supply = <&vreg_nvme>;
i2c-parent = <&i2c0>;
pedet-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>;
viocfg-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
pwrdis-gpios = <&tlmm 97 GPIO_ACTIVE_HIGH>;
pln-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>;
plas3-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
endpoint@0 {
reg = <0>;
remote-endpoint = <&pcie6_port0_ep>;
};
};
port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
endpoint@0 {
reg = <0>;
remote-endpoint = <&usb_hs_ep>;
};
};
};
};