Files
u-boot/arch/riscv/lib
Yu Chien Peter Lin bc35b49a5c riscv: andes_plicsw: Fix IPI during OpenSBI invocation
On some AE350 boards, we need to explicitly initialize the priority
registers to a non-zero value so the boot hart can instruct secondary
harts to jump to OpenSBI.

This patch also updates the information about PLICSW.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-06 17:28:08 +08:00
..
2022-09-26 14:29:13 +08:00
2020-05-18 18:36:55 -04:00
2023-02-10 07:41:39 -05:00
2021-04-08 15:37:29 +08:00
2022-09-29 16:11:31 -04:00